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Searched refs:hwss (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
Ddc.c420 dc->hwss.set_drr(&pipe, in dc_stream_adjust_vmin_vmax()
486 dc->hwss.get_position(&pipe, 1, &position); in dc_stream_get_crtc_position()
745 dc->hwss.program_gamut_remap(pipes); in dc_stream_set_gamut_remap()
764 dc->hwss.program_output_csc(dc, in dc_stream_program_csc_matrix()
797 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params); in dc_stream_set_static_screen_params()
1056 if (dc->hwss.interdependent_update_lock) in apply_ctx_interdependent_lock()
1057 dc->hwss.interdependent_update_lock(dc, context, lock); in apply_ctx_interdependent_lock()
1067 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock); in apply_ctx_interdependent_lock()
1163 if (dc->hwss.blank_phantom) in disable_dangling_plane()
1164 dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height); in disable_dangling_plane()
[all …]
Ddc_stream.c272 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_attributes()
274 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); in program_cursor_attributes()
277 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
280 if (dc->hwss.set_cursor_sdr_white_level) in program_cursor_attributes()
281 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
285 dc->hwss.cursor_lock(dc, pipe_to_program, false); in program_cursor_attributes()
287 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); in program_cursor_attributes()
303 return (dc->hwss.optimize_timing_for_fsft && in dc_optimize_timing_for_fsft()
304 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); in dc_optimize_timing_for_fsft()
421 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_position()
[all …]
Ddc_hw_sequencer.c488 if (dc->hwss.subvp_pipe_control_lock_fast) { in hwss_build_fast_sequence()
495 if (dc->hwss.pipe_control_lock) { in hwss_build_fast_sequence()
515 …if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state && current_mpc_pipe->plane_stat… in hwss_build_fast_sequence()
521 …if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->up… in hwss_build_fast_sequence()
528 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) { in hwss_build_fast_sequence()
543 …if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_c… in hwss_build_fast_sequence()
594 if (dc->hwss.pipe_control_lock) { in hwss_build_fast_sequence()
601 if (dc->hwss.subvp_pipe_control_lock_fast) { in hwss_build_fast_sequence()
641 dc->hwss.subvp_pipe_control_lock_fast(params); in hwss_execute_sequence()
644 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc, in hwss_execute_sequence()
[all …]
Ddc_vm_helper.c42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
58 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_hw_sequencer.c50 dc->hwss.pipe_control_lock = dce_pipe_control_lock; in dce80_hw_sequencer_construct()
51 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce80_hw_sequencer_construct()
52 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce80_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_edp_panel_control.c366 link->dc->hwss.edp_power_control(link, true); in edp_panel_backlight_power_on()
368 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in edp_panel_backlight_power_on()
369 if (link->dc->hwss.edp_backlight_control) in edp_panel_backlight_power_on()
370 link->dc->hwss.edp_backlight_control(link, true); in edp_panel_backlight_power_on()
378 link->dc->hwss.edp_power_control(link, true); in edp_set_panel_power()
379 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in edp_set_panel_power()
382 if (link->dc->hwss.edp_backlight_control) in edp_set_panel_power()
383 link->dc->hwss.edp_backlight_control(link, true); in edp_set_panel_power()
392 if (link->dc->hwss.edp_backlight_control) in edp_set_panel_power()
393 link->dc->hwss.edp_backlight_control(link, false); in edp_set_panel_power()
[all …]
Dlink_dp_phy.c65 link->dc->hwss.enable_dp_link_output(link, link_res, signal, in dp_enable_link_phy()
80 dc->hwss.disable_link_output(link, link_res, signal); in dp_disable_link_phy()
/drivers/gpu/drm/amd/display/dc/link/accessories/
Dlink_fpga.c54 dc->hwss.enable_stream(pipe_ctx); in dp_fpga_hpo_enable_link_and_stream()
92 dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings); in dp_fpga_hpo_enable_link_and_stream()
93 dc->hwss.enable_audio_stream(pipe_ctx); in dp_fpga_hpo_enable_link_and_stream()
Dlink_dp_cts.c489 } else if (link->dc->hwss.set_disp_pattern_generator) { in set_crtc_test_pattern()
515 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
529 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
551 } else if (link->dc->hwss.set_disp_pattern_generator) { in set_crtc_test_pattern()
558 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
572 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
698 link->dc->hwss.unblank_stream( in dp_set_test_pattern()
735 link->dc->hwss.blank_stream(pipe_ctx); in dp_set_test_pattern()
912 link->dc->hwss.update_info_frame(pipe_ctx); in dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c411 dc->hwss.update_plane_addr(dc, pipe_ctx); in dce60_apply_ctx_for_surface()
426 dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface; in dce60_hw_sequencer_construct()
427 dc->hwss.cursor_lock = dce60_pipe_control_lock; in dce60_hw_sequencer_construct()
428 dc->hwss.pipe_control_lock = dce60_pipe_control_lock; in dce60_hw_sequencer_construct()
429 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce60_hw_sequencer_construct()
430 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce60_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c409 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
417 dc->hwss.update_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
420 dc->hwss.enable_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
424 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
544 dc->hwss.edp_backlight_control && in dcn30_init_hw()
545 dc->hwss.power_down && in dcn30_init_hw()
546 dc->hwss.edp_power_control) { in dcn30_init_hw()
547 dc->hwss.edp_backlight_control(edp_link, false); in dcn30_init_hw()
548 dc->hwss.power_down(dc); in dcn30_init_hw()
549 dc->hwss.edp_power_control(edp_link, false); in dcn30_init_hw()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c589 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn20_plane_atomic_disable()
600 dc->hwss.set_flip_control_gsl(pipe_ctx, false); in dcn20_plane_atomic_disable()
1073 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn20_blank_pixel_data()
1086 dc->hwss.set_disp_pattern_generator(dc, in dcn20_blank_pixel_data()
1099 dc->hwss.set_disp_pattern_generator(dc, in dcn20_blank_pixel_data()
1111 dc->hwss.set_pipe(pipe_ctx); in dcn20_blank_pixel_data()
1595 dc->hwss.set_cursor_position(pipe_ctx); in dcn20_update_dchubp_dpp()
1596 dc->hwss.set_cursor_attribute(pipe_ctx); in dcn20_update_dchubp_dpp()
1598 if (dc->hwss.set_cursor_sdr_white_level) in dcn20_update_dchubp_dpp()
1599 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in dcn20_update_dchubp_dpp()
[all …]
Ddcn20_init.c145 dc->hwss = dcn20_funcs; in dcn20_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/
Dclk_mgr.c108 if (dc->hwss.exit_optimized_pwr_state) in clk_mgr_exit_optimized_pwr_state()
109 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state); in clk_mgr_exit_optimized_pwr_state()
146 if (dc->hwss.optimize_pwr_state) in clk_mgr_optimize_pwr_state()
147 dc->hwss.optimize_pwr_state(dc, dc->current_state); in clk_mgr_optimize_pwr_state()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c139 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce100_hw_sequencer_construct()
140 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce100_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hwseq.c858 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) in dcn32_init_hw()
859 dc->hwss.enable_accelerated_mode(dc, dc->current_state); in dcn32_init_hw()
895 dc->hwss.edp_backlight_control && in dcn32_init_hw()
896 dc->hwss.power_down && in dcn32_init_hw()
897 dc->hwss.edp_power_control) { in dcn32_init_hw()
898 dc->hwss.edp_backlight_control(edp_link, false); in dcn32_init_hw()
899 dc->hwss.power_down(dc); in dcn32_init_hw()
900 dc->hwss.edp_power_control(edp_link, false); in dcn32_init_hw()
909 dc->hwss.power_down) { in dcn32_init_hw()
910 dc->hwss.power_down(dc); in dcn32_init_hw()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c119 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
121 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
865 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx); in false_optc_underflow_wa()
1026 dc->hwss.disable_audio_stream(pipe_ctx); in dcn10_reset_back_end_for_pipe()
1049 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn10_reset_back_end_for_pipe()
1265 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn10_plane_atomic_disable()
1422 dc->hwss.disable_plane(dc, pipe_ctx); in dcn10_init_pipes()
1634 dc->hwss.power_down && in dcn10_power_down_on_boot()
1635 dc->hwss.edp_power_control) { in dcn10_power_down_on_boot()
1637 dc->hwss.power_down(dc); in dcn10_power_down_on_boot()
[all …]
Ddcn10_init.c126 dc->hwss = dcn10_funcs; in dcn10_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/link/
Dlink_dpms.c721 dc->hwss.set_avmute(pipe_ctx, enable); in set_avmute()
1941 link->dc->hwss.edp_power_control(link, false); in disable_link_dp()
1962 link->dc->hwss.disable_link_output(link, link_res, signal); in disable_link()
2031 dc->hwss.enable_tmds_link_output( in enable_link_hdmi()
2092 link->dc->hwss.edp_power_control(link, true); in enable_link_dp()
2093 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in enable_link_dp()
2171 dc->hwss.enable_lvds_link_output( in enable_link_lvds()
2317 dc->hwss.disable_audio_stream(pipe_ctx); in link_set_dpms_off()
2320 dc->hwss.blank_stream(pipe_ctx); in link_set_dpms_off()
2367 dc->hwss.disable_stream(pipe_ctx); in link_set_dpms_off()
[all …]
DMakefile48 AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \
/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hwseq.c340 dc->hwss.disable_plane(dc, pipe_ctx); in dcn201_init_hw()
482 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
507 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); in dcn201_update_mpcc()
Ddcn201_init.c134 dc->hwss = dcn201_funcs; in dcn201_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c677 dc->hwss.update_info_frame(pipe_ctx); in dce110_enable_stream()
1173 dc->hwss.disable_audio_stream(pipe_ctx); in dce110_disable_stream()
1232 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); in dce110_blank_stream()
1685 dc->hwss.disable_plane(dc, in disable_vga_and_power_gate_all_controllers()
1812 dc->hwss.edp_power_control(edp_link_with_sink, false); in dce110_enable_accelerated_mode()
2138 dc->hwss.disable_plane(dc, pipe_ctx_old); in dce110_reset_hw_ctx_wrap()
2829 dc->hwss.update_plane_addr(dc, pipe_ctx); in dce110_apply_ctx_for_surface()
3064 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in dce110_enable_dp_link_output()
3118 link->dc->hwss.edp_backlight_control) in dce110_disable_link_output()
3119 link->dc->hwss.edp_backlight_control(link, false); in dce110_disable_link_output()
[all …]
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_init.c152 dc->hwss = dcn301_funcs; in dcn301_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_init.c151 dc->hwss = dcn21_funcs; in dcn21_hw_sequencer_construct()

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