| /drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_reg.c | 28 u32 reg; in analogix_dp_enable_video_mute() local
31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
32 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
36 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
43 u32 reg; in analogix_dp_stop_video() local
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
46 reg &= ~VIDEO_EN; in analogix_dp_stop_video()
[all …]
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| /drivers/scsi/qla2xxx/ |
| D | qla_dbg.c | 107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
118 if (qla_pci_disconnected(vha, reg)) in qla27xx_dump_mpi_ram()
125 wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
126 wrt_reg_word(®->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
127 wrt_reg_word(®->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
129 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
130 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram()
131 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
132 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
134 wrt_reg_word(®->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
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| /drivers/media/platform/samsung/s5p-jpeg/ |
| D | jpeg-hw-s5p.c | 19 unsigned long reg; in s5p_jpeg_reset() local
22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
24 while (reg != 0) { in s5p_jpeg_reset()
26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
47 reg |= m; in s5p_jpeg_input_raw_mode()
48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
53 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
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| D | jpeg-hw-exynos4.c | 18 unsigned int reg; in exynos4_jpeg_sw_reset() local
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
34 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
[all …]
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| D | jpeg-hw-exynos3250.c | 20 u32 reg = 1; in exynos3250_jpeg_reset() local
25 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
28 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
31 reg = 0; in exynos3250_jpeg_reset()
34 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
38 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
62 u32 reg; in exynos3250_jpeg_clk_set() local
64 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
71 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
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| /drivers/media/cec/platform/s5p/ |
| D | exynos_hdmi_cecctrl.c | 26 unsigned int reg; in s5p_cec_set_divider() local
30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { in s5p_cec_set_divider()
35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
52 u8 reg; in s5p_cec_enable_rx() local
54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
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| /drivers/memory/tegra/ |
| D | tegra210.c | 21 .reg = 0x228,
25 .reg = 0x2e8,
37 .reg = 0x228,
41 .reg = 0x2f4,
53 .reg = 0x228,
57 .reg = 0x2e8,
69 .reg = 0x228,
73 .reg = 0x2f4,
85 .reg = 0x228,
89 .reg = 0x2ec,
[all …]
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| D | tegra114.c | 20 .reg = 0x34c,
32 .reg = 0x228,
36 .reg = 0x2e8,
48 .reg = 0x228,
52 .reg = 0x2f4,
64 .reg = 0x228,
68 .reg = 0x2e8,
80 .reg = 0x228,
84 .reg = 0x2f4,
96 .reg = 0x228,
[all …]
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| D | tegra124.c | 21 .reg = 0x34c,
33 .reg = 0x228,
37 .reg = 0x2e8,
49 .reg = 0x228,
53 .reg = 0x2f4,
65 .reg = 0x228,
69 .reg = 0x2e8,
81 .reg = 0x228,
85 .reg = 0x2f4,
97 .reg = 0x228,
[all …]
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| D | tegra30.c | 42 .reg = 0x34c,
55 .reg = 0x228,
59 .reg = 0x2e8,
72 .reg = 0x228,
76 .reg = 0x2f4,
89 .reg = 0x228,
93 .reg = 0x2e8,
106 .reg = 0x228,
110 .reg = 0x2f4,
123 .reg = 0x228,
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 54 static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) in efx_reg() argument
56 return efx->reg_base + reg; in efx_reg()
61 unsigned int reg) in _efx_writeq() argument
63 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
65 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument
67 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq()
72 unsigned int reg) in _efx_writed() argument
74 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
76 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument
78 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | soc15_common.h | 36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument
37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
43 WREG32(reg, value))
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
48 RREG32(reg))
50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument
[all …]
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| /drivers/net/ethernet/microchip/ |
| D | encx24j600-regmap.c | 60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
71 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
81 switch (reg) { in regmap_encx24j600_sfr_read()
104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
120 { .tx_buf = ®, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | rt2400pci.c | 48 u32 reg; in rt2400pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
57 reg = 0; in rt2400pci_bbp_write()
58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
72 u32 reg; in rt2400pci_bbp_read() local
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
[all …]
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| D | rt2500pci.c | 48 u32 reg; in rt2500pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write()
57 reg = 0; in rt2500pci_bbp_write()
58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
72 u32 reg; in rt2500pci_bbp_read() local
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read()
[all …]
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| D | rt61pci.c | 57 u32 reg; in rt61pci_bbp_write() local
65 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
66 reg = 0; in rt61pci_bbp_write()
67 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
68 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
69 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
70 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
81 u32 reg; in rt61pci_bbp_read() local
94 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument
68 REG_SET_N(reg, 2, init_value, \
69 FN(reg, f1), v1,\
70 FN(reg, f2), v2)
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
73 REG_SET_N(reg, 3, init_value, \
74 FN(reg, f1), v1,\
75 FN(reg, f2), v2,\
76 FN(reg, f3), v3)
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
[all …]
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| /drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb_82598.c | 23 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
28 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
29 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
31 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
33 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
35 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
37 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
39 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
46 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
49 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
[all …]
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| /drivers/media/platform/nxp/imx-jpeg/ |
| D | mxc-jpeg-hw.c | 35 void print_cast_status(struct device *dev, void __iomem *reg, in print_cast_status() argument
39 print_wrapper_reg(dev, reg, CAST_STATUS0); in print_cast_status()
40 print_wrapper_reg(dev, reg, CAST_STATUS1); in print_cast_status()
41 print_wrapper_reg(dev, reg, CAST_STATUS2); in print_cast_status()
42 print_wrapper_reg(dev, reg, CAST_STATUS3); in print_cast_status()
43 print_wrapper_reg(dev, reg, CAST_STATUS4); in print_cast_status()
44 print_wrapper_reg(dev, reg, CAST_STATUS5); in print_cast_status()
45 print_wrapper_reg(dev, reg, CAST_STATUS6); in print_cast_status()
46 print_wrapper_reg(dev, reg, CAST_STATUS7); in print_cast_status()
47 print_wrapper_reg(dev, reg, CAST_STATUS8); in print_cast_status()
[all …]
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| /drivers/acpi/pmic/ |
| D | intel_pmic_bxtwc.c | 30 .reg = 0x63,
35 .reg = 0x65,
40 .reg = 0x67,
45 .reg = 0x6d,
50 .reg = 0x6f,
55 .reg = 0x70,
60 .reg = 0x71,
65 .reg = 0x72,
70 .reg = 0x73,
75 .reg = 0x74,
[all …]
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| /drivers/media/pci/cx23885/ |
| D | cx23885-ioctl.c | 32 struct v4l2_dbg_register *reg) in cx23417_g_register() argument
39 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) in cx23417_g_register()
42 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register()
45 reg->size = 4; in cx23417_g_register()
46 reg->val = value; in cx23417_g_register()
51 struct v4l2_dbg_register *reg) in cx23885_g_register() argument
55 if (reg->match.addr > 1) in cx23885_g_register()
57 if (reg->match.addr) in cx23885_g_register()
58 return cx23417_g_register(dev, reg); in cx23885_g_register()
60 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register()
[all …]
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | reg.h | 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
[all …]
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| /drivers/net/ethernet/sfc/siena/ |
| D | io.h | 78 static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) in efx_reg() argument
80 return efx->reg_base + reg; in efx_reg()
85 unsigned int reg) in _efx_writeq() argument
87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
89 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument
91 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq()
96 unsigned int reg) in _efx_writed() argument
98 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
100 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument
102 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd()
[all …]
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| /drivers/net/dsa/mv88e6xxx/ |
| D | port.c | 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
26 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_port_read()
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_wait_bit() argument
34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); in mv88e6xxx_port_wait_bit()
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
42 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_port_write()
53 u16 reg; in mv88e6185_port_set_pause() local
56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
[all …]
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