| /drivers/iommu/arm/arm-smmu-v3/pkvm/ |
| D | arm-smmu-v3.c | 534 struct hyp_arm_smmu_v3_domain *smmu_domain) in smmu_inv_domain() argument
536 struct kvm_hyp_iommu_domain *domain = smmu_domain->domain; in smmu_inv_domain()
539 if (smmu_domain->pgtable->cfg.fmt == ARM_64_LPAE_S2) { in smmu_inv_domain()
556 struct hyp_arm_smmu_v3_domain *smmu_domain = domain->priv; in smmu_tlb_flush_all() local
560 hyp_read_lock(&smmu_domain->lock); in smmu_tlb_flush_all()
561 list_for_each_entry(iommu_node, &smmu_domain->iommu_list, list) { in smmu_tlb_flush_all()
564 smmu_inv_domain(smmu, smmu_domain); in smmu_tlb_flush_all()
567 hyp_read_unlock(&smmu_domain->lock); in smmu_tlb_flush_all()
578 struct hyp_arm_smmu_v3_domain *smmu_domain = domain->priv; in smmu_tlb_inv_range_smmu() local
587 tg = __ffs(smmu_domain->pgtable->cfg.pgsize_bitmap); in smmu_tlb_inv_range_smmu()
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| /drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3.c | 773 static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, in arm_smmu_sync_cd() argument
780 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_sync_cd()
791 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_sync_cd()
792 list_for_each_entry(master, &smmu_domain->devices, domain_head) { in arm_smmu_sync_cd()
798 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_sync_cd()
828 static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, in arm_smmu_get_cd_ptr() argument
834 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_get_cd_ptr()
835 struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg; in arm_smmu_get_cd_ptr()
837 if (smmu_domain->s1_cfg.s1fmt == STRTAB_STE_0_S1FMT_LINEAR) in arm_smmu_get_cd_ptr()
849 arm_smmu_sync_cd(smmu_domain, ssid, false); in arm_smmu_get_cd_ptr()
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| D | arm-smmu-v3-sva.c | 51 struct arm_smmu_domain *smmu_domain; in arm_smmu_share_asid() local
65 smmu_domain = container_of(cd, struct arm_smmu_domain, s1_cfg.cd); in arm_smmu_share_asid()
66 smmu = smmu_domain->smmu; in arm_smmu_share_asid()
83 arm_smmu_write_ctx_desc(smmu_domain, IOMMU_NO_PASID, cd); in arm_smmu_share_asid()
204 struct arm_smmu_domain *smmu_domain = smmu_mn->domain; in arm_smmu_mm_arch_invalidate_secondary_tlbs() local
213 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { in arm_smmu_mm_arch_invalidate_secondary_tlbs()
221 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) { in arm_smmu_mm_arch_invalidate_secondary_tlbs()
223 arm_smmu_tlb_inv_asid(smmu_domain->smmu, in arm_smmu_mm_arch_invalidate_secondary_tlbs()
229 smmu_domain); in arm_smmu_mm_arch_invalidate_secondary_tlbs()
232 arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size); in arm_smmu_mm_arch_invalidate_secondary_tlbs()
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| D | arm-smmu-v3.h | 308 int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid,
313 struct arm_smmu_domain *smmu_domain);
315 int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid,
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| /drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu.c | 226 static void arm_smmu_tlb_sync_context(struct arm_smmu_domain *smmu_domain) in arm_smmu_tlb_sync_context() argument
228 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context()
231 spin_lock_irqsave(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
232 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
234 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
239 struct arm_smmu_domain *smmu_domain = cookie; in arm_smmu_tlb_inv_context_s1() local
245 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
246 ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid); in arm_smmu_tlb_inv_context_s1()
247 arm_smmu_tlb_sync_context(smmu_domain); in arm_smmu_tlb_inv_context_s1()
252 struct arm_smmu_domain *smmu_domain = cookie; in arm_smmu_tlb_inv_context_s2() local
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| D | arm-smmu-qcom.c | 62 struct arm_smmu_domain *smmu_domain = (void *)cookie; in qcom_adreno_smmu_get_fault_info() local
63 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
64 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info()
77 struct arm_smmu_domain *smmu_domain = (void *)cookie; in qcom_adreno_smmu_set_stall() local
78 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_stall()
79 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); in qcom_adreno_smmu_set_stall()
89 struct arm_smmu_domain *smmu_domain = (void *)cookie; in qcom_adreno_smmu_resume_translation() local
90 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_resume_translation()
91 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_resume_translation()
124 struct arm_smmu_domain *smmu_domain = (void *)cookie; in qcom_adreno_smmu_get_ttbr1_cfg() local
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| D | arm-smmu-impl.c | 71 static int cavium_init_context(struct arm_smmu_domain *smmu_domain, in cavium_init_context() argument
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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| D | arm-smmu-nvidia.c | 225 struct arm_smmu_domain *smmu_domain; in nvidia_smmu_context_fault() local
228 smmu_domain = container_of(domain, struct arm_smmu_domain, domain); in nvidia_smmu_context_fault()
229 smmu = smmu_domain->smmu; in nvidia_smmu_context_fault()
261 static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain, in nvidia_smmu_init_context() argument
265 struct arm_smmu_device *smmu = smmu_domain->smmu; in nvidia_smmu_init_context()
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| D | arm-smmu.h | 433 int (*init_context)(struct arm_smmu_domain *smmu_domain,
440 int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain,
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