1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
7 *
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10 */
11
12 #ifndef HANTRO_H_
13 #define HANTRO_H_
14
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <linux/wait.h>
18 #include <linux/clk.h>
19 #include <linux/reset.h>
20
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
27
28 #include "hantro_hw.h"
29
30 struct hantro_ctx;
31 struct hantro_codec_ops;
32 struct hantro_postproc_ops;
33
34 #define HANTRO_JPEG_ENCODER BIT(0)
35 #define HANTRO_ENCODERS 0x0000ffff
36 #define HANTRO_MPEG2_DECODER BIT(16)
37 #define HANTRO_VP8_DECODER BIT(17)
38 #define HANTRO_H264_DECODER BIT(18)
39 #define HANTRO_HEVC_DECODER BIT(19)
40 #define HANTRO_VP9_DECODER BIT(20)
41 #define HANTRO_AV1_DECODER BIT(21)
42 #define HANTRO_DECODERS 0xffff0000
43
44 /**
45 * struct hantro_irq - irq handler and name
46 *
47 * @name: irq name for device tree lookup
48 * @handler: interrupt handler
49 */
50 struct hantro_irq {
51 const char *name;
52 irqreturn_t (*handler)(int irq, void *priv);
53 };
54
55 /**
56 * struct hantro_variant - information about VPU hardware variant
57 *
58 * @enc_offset: Offset from VPU base to encoder registers.
59 * @dec_offset: Offset from VPU base to decoder registers.
60 * @enc_fmts: Encoder formats.
61 * @num_enc_fmts: Number of encoder formats.
62 * @dec_fmts: Decoder formats.
63 * @num_dec_fmts: Number of decoder formats.
64 * @postproc_fmts: Post-processor formats.
65 * @num_postproc_fmts: Number of post-processor formats.
66 * @postproc_ops: Post-processor ops.
67 * @codec: Supported codecs
68 * @codec_ops: Codec ops.
69 * @init: Initialize hardware, optional.
70 * @runtime_resume: reenable hardware after power gating, optional.
71 * @irqs: array of irq names and interrupt handlers
72 * @num_irqs: number of irqs in the array
73 * @clk_names: array of clock names
74 * @num_clocks: number of clocks in the array
75 * @reg_names: array of register range names
76 * @num_regs: number of register range names in the array
77 * @double_buffer: core needs double buffering
78 * @legacy_regs: core uses legacy register set
79 * @late_postproc: postproc must be set up at the end of the job
80 */
81 struct hantro_variant {
82 unsigned int enc_offset;
83 unsigned int dec_offset;
84 const struct hantro_fmt *enc_fmts;
85 unsigned int num_enc_fmts;
86 const struct hantro_fmt *dec_fmts;
87 unsigned int num_dec_fmts;
88 const struct hantro_fmt *postproc_fmts;
89 unsigned int num_postproc_fmts;
90 const struct hantro_postproc_ops *postproc_ops;
91 unsigned int codec;
92 const struct hantro_codec_ops *codec_ops;
93 int (*init)(struct hantro_dev *vpu);
94 int (*runtime_resume)(struct hantro_dev *vpu);
95 const struct hantro_irq *irqs;
96 int num_irqs;
97 const char * const *clk_names;
98 int num_clocks;
99 const char * const *reg_names;
100 int num_regs;
101 unsigned int double_buffer : 1;
102 unsigned int legacy_regs : 1;
103 unsigned int late_postproc : 1;
104 };
105
106 /**
107 * enum hantro_codec_mode - codec operating mode.
108 * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
109 * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
110 * @HANTRO_MODE_H264_DEC: H264 decoder.
111 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
112 * @HANTRO_MODE_VP8_DEC: VP8 decoder.
113 * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
114 * @HANTRO_MODE_VP9_DEC: VP9 decoder.
115 * @HANTRO_MODE_AV1_DEC: AV1 decoder
116 */
117 enum hantro_codec_mode {
118 HANTRO_MODE_NONE = -1,
119 HANTRO_MODE_JPEG_ENC,
120 HANTRO_MODE_H264_DEC,
121 HANTRO_MODE_MPEG2_DEC,
122 HANTRO_MODE_VP8_DEC,
123 HANTRO_MODE_HEVC_DEC,
124 HANTRO_MODE_VP9_DEC,
125 HANTRO_MODE_AV1_DEC,
126 };
127
128 /*
129 * struct hantro_ctrl - helper type to declare supported controls
130 * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
131 * @cfg: control configuration
132 */
133 struct hantro_ctrl {
134 unsigned int codec;
135 struct v4l2_ctrl_config cfg;
136 };
137
138 /*
139 * struct hantro_func - Hantro VPU functionality
140 *
141 * @id: processing functionality ID (can be
142 * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
143 * %MEDIA_ENT_F_PROC_VIDEO_DECODER)
144 * @vdev: &struct video_device that exposes the encoder or
145 * decoder functionality
146 * @source_pad: &struct media_pad with the source pad.
147 * @sink: &struct media_entity pointer with the sink entity
148 * @sink_pad: &struct media_pad with the sink pad.
149 * @proc: &struct media_entity pointer with the M2M device itself.
150 * @proc_pads: &struct media_pad with the @proc pads.
151 * @intf_devnode: &struct media_intf devnode pointer with the interface
152 * with controls the M2M device.
153 *
154 * Contains everything needed to attach the video device to the media device.
155 */
156 struct hantro_func {
157 unsigned int id;
158 struct video_device vdev;
159 struct media_pad source_pad;
160 struct media_entity sink;
161 struct media_pad sink_pad;
162 struct media_entity proc;
163 struct media_pad proc_pads[2];
164 struct media_intf_devnode *intf_devnode;
165 };
166
167 static inline struct hantro_func *
hantro_vdev_to_func(struct video_device * vdev)168 hantro_vdev_to_func(struct video_device *vdev)
169 {
170 return container_of(vdev, struct hantro_func, vdev);
171 }
172
173 /**
174 * struct hantro_dev - driver data
175 * @v4l2_dev: V4L2 device to register video devices for.
176 * @m2m_dev: mem2mem device associated to this device.
177 * @mdev: media device associated to this device.
178 * @encoder: encoder functionality.
179 * @decoder: decoder functionality.
180 * @pdev: Pointer to VPU platform device.
181 * @dev: Pointer to device for convenient logging using
182 * dev_ macros.
183 * @clocks: Array of clock handles.
184 * @resets: Array of reset handles.
185 * @reg_bases: Mapped addresses of VPU registers.
186 * @enc_base: Mapped address of VPU encoder register for convenience.
187 * @dec_base: Mapped address of VPU decoder register for convenience.
188 * @ctrl_base: Mapped address of VPU control block.
189 * @vpu_mutex: Mutex to synchronize V4L2 calls.
190 * @irqlock: Spinlock to synchronize access to data structures
191 * shared with interrupt handlers.
192 * @variant: Hardware variant-specific parameters.
193 * @watchdog_work: Delayed work for hardware timeout handling.
194 */
195 struct hantro_dev {
196 struct v4l2_device v4l2_dev;
197 struct v4l2_m2m_dev *m2m_dev;
198 struct media_device mdev;
199 struct hantro_func *encoder;
200 struct hantro_func *decoder;
201 struct platform_device *pdev;
202 struct device *dev;
203 struct clk_bulk_data *clocks;
204 struct reset_control *resets;
205 void __iomem **reg_bases;
206 void __iomem *enc_base;
207 void __iomem *dec_base;
208 void __iomem *ctrl_base;
209
210 struct mutex vpu_mutex; /* video_device lock */
211 spinlock_t irqlock;
212 const struct hantro_variant *variant;
213 struct delayed_work watchdog_work;
214 };
215
216 /**
217 * struct hantro_ctx - Context (instance) private data.
218 *
219 * @dev: VPU driver data to which the context belongs.
220 * @fh: V4L2 file handler.
221 * @is_encoder: Decoder or encoder context?
222 *
223 * @sequence_cap: Sequence counter for capture queue
224 * @sequence_out: Sequence counter for output queue
225 *
226 * @vpu_src_fmt: Descriptor of active source format.
227 * @src_fmt: V4L2 pixel format of active source format.
228 * @vpu_dst_fmt: Descriptor of active destination format.
229 * @dst_fmt: V4L2 pixel format of active destination format.
230 *
231 * @ctrl_handler: Control handler used to register controls.
232 * @jpeg_quality: User-specified JPEG compression quality.
233 * @bit_depth: Bit depth of current frame
234 * @need_postproc: Set to true if the bitstream features require to
235 * use the post-processor.
236 *
237 * @codec_ops: Set of operations related to codec mode.
238 * @postproc: Post-processing context.
239 * @h264_dec: H.264-decoding context.
240 * @jpeg_enc: JPEG-encoding context.
241 * @mpeg2_dec: MPEG-2-decoding context.
242 * @vp8_dec: VP8-decoding context.
243 * @hevc_dec: HEVC-decoding context.
244 * @vp9_dec: VP9-decoding context.
245 * @av1_dec: AV1-decoding context.
246 */
247 struct hantro_ctx {
248 struct hantro_dev *dev;
249 struct v4l2_fh fh;
250 bool is_encoder;
251
252 u32 sequence_cap;
253 u32 sequence_out;
254
255 const struct hantro_fmt *vpu_src_fmt;
256 struct v4l2_pix_format_mplane src_fmt;
257 const struct hantro_fmt *vpu_dst_fmt;
258 struct v4l2_pix_format_mplane dst_fmt;
259
260 struct v4l2_ctrl_handler ctrl_handler;
261 int jpeg_quality;
262 int bit_depth;
263
264 const struct hantro_codec_ops *codec_ops;
265 struct hantro_postproc_ctx postproc;
266 bool need_postproc;
267
268 /* Specific for particular codec modes. */
269 union {
270 struct hantro_h264_dec_hw_ctx h264_dec;
271 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
272 struct hantro_vp8_dec_hw_ctx vp8_dec;
273 struct hantro_hevc_dec_hw_ctx hevc_dec;
274 struct hantro_vp9_dec_hw_ctx vp9_dec;
275 struct hantro_av1_dec_hw_ctx av1_dec;
276 };
277 };
278
279 /**
280 * struct hantro_fmt - information about supported video formats.
281 * @name: Human readable name of the format.
282 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
283 * @codec_mode: Codec mode related to this format. See
284 * enum hantro_codec_mode.
285 * @header_size: Optional header size. Currently used by JPEG encoder.
286 * @max_depth: Maximum depth, for bitstream formats
287 * @enc_fmt: Format identifier for encoder registers.
288 * @frmsize: Supported range of frame sizes (only for bitstream formats).
289 * @postprocessed: Indicates if this format needs the post-processor.
290 * @match_depth: Indicates if format bit depth must match video bit depth
291 */
292 struct hantro_fmt {
293 char *name;
294 u32 fourcc;
295 enum hantro_codec_mode codec_mode;
296 int header_size;
297 int max_depth;
298 enum hantro_enc_fmt enc_fmt;
299 struct v4l2_frmsize_stepwise frmsize;
300 bool postprocessed;
301 bool match_depth;
302 };
303
304 struct hantro_reg {
305 u32 base;
306 u32 shift;
307 u32 mask;
308 };
309
310 struct hantro_postproc_regs {
311 struct hantro_reg pipeline_en;
312 struct hantro_reg max_burst;
313 struct hantro_reg clk_gate;
314 struct hantro_reg out_swap32;
315 struct hantro_reg out_endian;
316 struct hantro_reg out_luma_base;
317 struct hantro_reg input_width;
318 struct hantro_reg input_height;
319 struct hantro_reg output_width;
320 struct hantro_reg output_height;
321 struct hantro_reg input_fmt;
322 struct hantro_reg output_fmt;
323 struct hantro_reg orig_width;
324 struct hantro_reg display_width;
325 };
326
327 struct hantro_vp9_decoded_buffer_info {
328 /* Info needed when the decoded frame serves as a reference frame. */
329 unsigned short width;
330 unsigned short height;
331 u32 bit_depth : 4;
332 };
333
334 struct hantro_decoded_buffer {
335 /* Must be the first field in this struct. */
336 struct v4l2_m2m_buffer base;
337
338 union {
339 struct hantro_vp9_decoded_buffer_info vp9;
340 };
341 };
342
343 /* Logging helpers */
344
345 /**
346 * DOC: hantro_debug: Module parameter to control level of debugging messages.
347 *
348 * Level of debugging messages can be controlled by bits of
349 * module parameter called "debug". Meaning of particular
350 * bits is as follows:
351 *
352 * bit 0 - global information: mode, size, init, release
353 * bit 1 - each run start/result information
354 * bit 2 - contents of small controls from userspace
355 * bit 3 - contents of big controls from userspace
356 * bit 4 - detail fmt, ctrl, buffer q/dq information
357 * bit 5 - detail function enter/leave trace information
358 * bit 6 - register write/read information
359 */
360 extern int hantro_debug;
361
362 #define vpu_debug(level, fmt, args...) \
363 do { \
364 if (hantro_debug & BIT(level)) \
365 pr_info("%s:%d: " fmt, \
366 __func__, __LINE__, ##args); \
367 } while (0)
368
369 #define vpu_err(fmt, args...) \
370 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
371
372 /* Structure access helpers. */
fh_to_ctx(struct v4l2_fh * fh)373 static __always_inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
374 {
375 return container_of(fh, struct hantro_ctx, fh);
376 }
377
378 /* Register accessors. */
vepu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)379 static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,
380 u32 val, u32 reg)
381 {
382 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
383 writel_relaxed(val, vpu->enc_base + reg);
384 }
385
vepu_write(struct hantro_dev * vpu,u32 val,u32 reg)386 static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
387 {
388 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
389 writel(val, vpu->enc_base + reg);
390 }
391
vepu_read(struct hantro_dev * vpu,u32 reg)392 static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
393 {
394 u32 val = readl(vpu->enc_base + reg);
395
396 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
397 return val;
398 }
399
vdpu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)400 static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,
401 u32 val, u32 reg)
402 {
403 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
404 writel_relaxed(val, vpu->dec_base + reg);
405 }
406
vdpu_write(struct hantro_dev * vpu,u32 val,u32 reg)407 static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
408 {
409 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
410 writel(val, vpu->dec_base + reg);
411 }
412
hantro_write_addr(struct hantro_dev * vpu,unsigned long offset,dma_addr_t addr)413 static __always_inline void hantro_write_addr(struct hantro_dev *vpu,
414 unsigned long offset,
415 dma_addr_t addr)
416 {
417 vdpu_write(vpu, addr & 0xffffffff, offset);
418 }
419
vdpu_read(struct hantro_dev * vpu,u32 reg)420 static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
421 {
422 u32 val = readl(vpu->dec_base + reg);
423
424 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
425 return val;
426 }
427
vdpu_read_mask(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)428 static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,
429 const struct hantro_reg *reg,
430 u32 val)
431 {
432 u32 v;
433
434 v = vdpu_read(vpu, reg->base);
435 v &= ~(reg->mask << reg->shift);
436 v |= ((val & reg->mask) << reg->shift);
437 return v;
438 }
439
hantro_reg_write(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)440 static __always_inline void hantro_reg_write(struct hantro_dev *vpu,
441 const struct hantro_reg *reg,
442 u32 val)
443 {
444 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
445 }
446
hantro_reg_write_relaxed(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)447 static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,
448 const struct hantro_reg *reg,
449 u32 val)
450 {
451 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
452 }
453
454 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
455 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
456
457 static inline struct vb2_v4l2_buffer *
hantro_get_src_buf(struct hantro_ctx * ctx)458 hantro_get_src_buf(struct hantro_ctx *ctx)
459 {
460 return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
461 }
462
463 static inline struct vb2_v4l2_buffer *
hantro_get_dst_buf(struct hantro_ctx * ctx)464 hantro_get_dst_buf(struct hantro_ctx *ctx)
465 {
466 return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
467 }
468
469 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
470 const struct hantro_fmt *fmt);
471
472 static inline dma_addr_t
hantro_get_dec_buf_addr(struct hantro_ctx * ctx,struct vb2_buffer * vb)473 hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
474 {
475 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
476 return ctx->postproc.dec_q[vb->index].dma;
477 return vb2_dma_contig_plane_dma_addr(vb, 0);
478 }
479
480 static inline struct hantro_decoded_buffer *
vb2_to_hantro_decoded_buf(struct vb2_buffer * buf)481 vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
482 {
483 return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
484 }
485
486 void hantro_postproc_disable(struct hantro_ctx *ctx);
487 void hantro_postproc_enable(struct hantro_ctx *ctx);
488 void hantro_postproc_free(struct hantro_ctx *ctx);
489 int hantro_postproc_alloc(struct hantro_ctx *ctx);
490 int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
491 struct v4l2_frmsizeenum *fsize);
492
493 #endif /* HANTRO_H_ */
494