1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/bitops.h>
5
6 #define ENETC_MM_VERIFY_SLEEP_US USEC_PER_MSEC
7 #define ENETC_MM_VERIFY_RETRIES 3
8
9 /* ENETC device IDs */
10 #define ENETC_DEV_ID_PF 0xe100
11 #define ENETC_DEV_ID_VF 0xef00
12 #define ENETC_DEV_ID_PTP 0xee02
13
14 /* ENETC register block BAR */
15 #define ENETC_BAR_REGS 0
16
17 /** SI regs, offset: 0h */
18 #define ENETC_SIMR 0
19 #define ENETC_SIMR_EN BIT(31)
20 #define ENETC_SIMR_RSSE BIT(0)
21 #define ENETC_SICTR0 0x18
22 #define ENETC_SICTR1 0x1c
23 #define ENETC_SIPCAPR0 0x20
24 #define ENETC_SIPCAPR0_PSFP BIT(9)
25 #define ENETC_SIPCAPR0_RSS BIT(8)
26 #define ENETC_SIPCAPR0_QBV BIT(4)
27 #define ENETC_SIPCAPR0_QBU BIT(3)
28 #define ENETC_SIPCAPR1 0x24
29 #define ENETC_SITGTGR 0x30
30 #define ENETC_SIRBGCR 0x38
31 /* cache attribute registers for transactions initiated by ENETC */
32 #define ENETC_SICAR0 0x40
33 #define ENETC_SICAR1 0x44
34 #define ENETC_SICAR2 0x48
35 /* rd snoop, no alloc
36 * wr snoop, no alloc, partial cache line update for BDs and full cache line
37 * update for data
38 */
39 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
40 #define ENETC_SICAR_WR_COHERENT 0x00006727
41 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
42
43 #define ENETC_SIPMAR0 0x80
44 #define ENETC_SIPMAR1 0x84
45
46 /* VF-PF Message passing */
47 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
48 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
enetc_vsi_set_msize(u32 size)49 static inline u32 enetc_vsi_set_msize(u32 size)
50 {
51 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
52 }
53
54 #define ENETC_PSIMSGRR 0x204
55 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
56 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
57 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
58 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
59
60 #define ENETC_VSIMSGSR 0x204 /* RO */
61 #define ENETC_VSIMSGSR_MB BIT(0)
62 #define ENETC_VSIMSGSR_MS BIT(1)
63 #define ENETC_VSIMSGSNDAR0 0x210
64 #define ENETC_VSIMSGSNDAR1 0x214
65
66 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
67 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
68
69 /* SI statistics */
70 #define ENETC_SIROCT 0x300
71 #define ENETC_SIRFRM 0x308
72 #define ENETC_SIRUCA 0x310
73 #define ENETC_SIRMCA 0x318
74 #define ENETC_SITOCT 0x320
75 #define ENETC_SITFRM 0x328
76 #define ENETC_SITUCA 0x330
77 #define ENETC_SITMCA 0x338
78 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
79
80 /* Control BDR regs */
81 #define ENETC_SICBDRMR 0x800
82 #define ENETC_SICBDRSR 0x804 /* RO */
83 #define ENETC_SICBDRBAR0 0x810
84 #define ENETC_SICBDRBAR1 0x814
85 #define ENETC_SICBDRPIR 0x818
86 #define ENETC_SICBDRCIR 0x81c
87 #define ENETC_SICBDRLENR 0x820
88
89 #define ENETC_SICAPR0 0x900
90 #define ENETC_SICAPR1 0x904
91
92 #define ENETC_PSIIER 0xa00
93 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
94 #define ENETC_PSIIDR 0xa08
95 #define ENETC_SITXIDR 0xa18
96 #define ENETC_SIRXIDR 0xa28
97 #define ENETC_SIMSIVR 0xa30
98
99 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
100 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
101
102 #define ENETC_SIUEFDCR 0xe28
103
104 #define ENETC_SIRFSCAPR 0x1200
105 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
106 #define ENETC_SIRSSCAPR 0x1600
107 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
108
109 /** SI BDR sub-blocks, n = 0..7 */
110 enum enetc_bdr_type {TX, RX};
111 #define ENETC_BDR_OFF(i) ((i) * 0x200)
112 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
113 /* RX BDR reg offsets */
114 #define ENETC_RBMR 0
115 #define ENETC_RBMR_BDS BIT(2)
116 #define ENETC_RBMR_CM BIT(4)
117 #define ENETC_RBMR_VTE BIT(5)
118 #define ENETC_RBMR_EN BIT(31)
119 #define ENETC_RBSR 0x4
120 #define ENETC_RBBSR 0x8
121 #define ENETC_RBCIR 0xc
122 #define ENETC_RBBAR0 0x10
123 #define ENETC_RBBAR1 0x14
124 #define ENETC_RBPIR 0x18
125 #define ENETC_RBLENR 0x20
126 #define ENETC_RBIER 0xa0
127 #define ENETC_RBIER_RXTIE BIT(0)
128 #define ENETC_RBIDR 0xa4
129 #define ENETC_RBICR0 0xa8
130 #define ENETC_RBICR0_ICEN BIT(31)
131 #define ENETC_RBICR0_ICPT_MASK 0x1ff
132 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK)
133 #define ENETC_RBICR1 0xac
134
135 /* TX BDR reg offsets */
136 #define ENETC_TBMR 0
137 #define ENETC_TBSR_BUSY BIT(0)
138 #define ENETC_TBMR_VIH BIT(9)
139 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
140 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
141 #define ENETC_TBMR_EN BIT(31)
142 #define ENETC_TBSR 0x4
143 #define ENETC_TBBAR0 0x10
144 #define ENETC_TBBAR1 0x14
145 #define ENETC_TBPIR 0x18
146 #define ENETC_TBCIR 0x1c
147 #define ENETC_TBCIR_IDX_MASK 0xffff
148 #define ENETC_TBLENR 0x20
149 #define ENETC_TBIER 0xa0
150 #define ENETC_TBIER_TXTIE BIT(0)
151 #define ENETC_TBIDR 0xa4
152 #define ENETC_TBICR0 0xa8
153 #define ENETC_TBICR0_ICEN BIT(31)
154 #define ENETC_TBICR0_ICPT_MASK 0xf
155 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK)
156 #define ENETC_TBICR1 0xac
157
158 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
159
160 /* Port regs, offset: 1_0000h */
161 #define ENETC_PORT_BASE 0x10000
162 #define ENETC_PMR 0x0000
163 #define ENETC_PMR_EN GENMASK(18, 16)
164 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
165 #define ENETC_PMR_PSPEED_10M 0
166 #define ENETC_PMR_PSPEED_100M BIT(8)
167 #define ENETC_PMR_PSPEED_1000M BIT(9)
168 #define ENETC_PMR_PSPEED_2500M BIT(10)
169 #define ENETC_PSR 0x0004 /* RO */
170 #define ENETC_PSIPMR 0x0018
171 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
172 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
173 #define ENETC_PSIPVMR 0x001c
174 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
175 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
176 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
177 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
178 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
179 #define ENETC_PVCLCTR 0x0208
180 #define ENETC_PCVLANR1 0x0210
181 #define ENETC_PCVLANR2 0x0214
182 #define ENETC_VLAN_TYPE_C BIT(0)
183 #define ENETC_VLAN_TYPE_S BIT(1)
184 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
185 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
186 #define ENETC_PSIVLAN_EN BIT(31)
187 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
188 #define ENETC_PPAUONTR 0x0410
189 #define ENETC_PPAUOFFTR 0x0414
190 #define ENETC_PTXMBAR 0x0608
191 #define ENETC_PCAPR0 0x0900
192 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
193 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
194 #define ENETC_PCAPR1 0x0904
195 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
196 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
197 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
198 #define ENETC_PSICFGR0_VTE BIT(12)
199 #define ENETC_PSICFGR0_SIVIE BIT(14)
200 #define ENETC_PSICFGR0_ASE BIT(15)
201 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
202
203 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
204 #define ENETC_CBSE BIT(31)
205 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
206 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
207 #define ENETC_RSSHASH_KEY_SIZE 40
208 #define ENETC_PRSSCAPR 0x1404
209 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
210 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
211 #define ENETC_PSIVLANFMR 0x1700
212 #define ENETC_PSIVLANFMR_VS BIT(0)
213 #define ENETC_PRFSMR 0x1800
214 #define ENETC_PRFSMR_RFSE BIT(31)
215 #define ENETC_PRFSCAPR 0x1804
216 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
217 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
218 #define ENETC_PFPMR 0x1900
219 #define ENETC_PFPMR_PMACE BIT(1)
220 #define ENETC_EMDIO_BASE 0x1c00
221 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
222 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
223 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
224 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
225 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
226 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
227 #define ENETC_MMCSR 0x1f00
228 #define ENETC_MMCSR_LINK_FAIL BIT(31)
229 #define ENETC_MMCSR_VT_MASK GENMASK(29, 23) /* Verify Time */
230 #define ENETC_MMCSR_VT(x) (((x) << 23) & ENETC_MMCSR_VT_MASK)
231 #define ENETC_MMCSR_GET_VT(x) (((x) & ENETC_MMCSR_VT_MASK) >> 23)
232 #define ENETC_MMCSR_TXSTS_MASK GENMASK(22, 21) /* Merge Status */
233 #define ENETC_MMCSR_GET_TXSTS(x) (((x) & ENETC_MMCSR_TXSTS_MASK) >> 21)
234 #define ENETC_MMCSR_VSTS_MASK GENMASK(20, 18) /* Verify Status */
235 #define ENETC_MMCSR_GET_VSTS(x) (((x) & ENETC_MMCSR_VSTS_MASK) >> 18)
236 #define ENETC_MMCSR_VDIS BIT(17) /* Verify Disabled */
237 #define ENETC_MMCSR_ME BIT(16) /* Merge Enabled */
238 #define ENETC_MMCSR_RAFS_MASK GENMASK(9, 8) /* Remote Additional Fragment Size */
239 #define ENETC_MMCSR_RAFS(x) (((x) << 8) & ENETC_MMCSR_RAFS_MASK)
240 #define ENETC_MMCSR_GET_RAFS(x) (((x) & ENETC_MMCSR_RAFS_MASK) >> 8)
241 #define ENETC_MMCSR_LAFS_MASK GENMASK(4, 3) /* Local Additional Fragment Size */
242 #define ENETC_MMCSR_GET_LAFS(x) (((x) & ENETC_MMCSR_LAFS_MASK) >> 3)
243 #define ENETC_MMCSR_LPA BIT(2) /* Local Preemption Active */
244 #define ENETC_MMCSR_LPE BIT(1) /* Local Preemption Enabled */
245 #define ENETC_MMCSR_LPS BIT(0) /* Local Preemption Supported */
246 #define ENETC_MMFAECR 0x1f08
247 #define ENETC_MMFSECR 0x1f0c
248 #define ENETC_MMFAOCR 0x1f10
249 #define ENETC_MMFCRXR 0x1f14
250 #define ENETC_MMFCTXR 0x1f18
251 #define ENETC_MMHCR 0x1f1c
252 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
253
254 #define ENETC_PMAC_OFFSET 0x1000
255
256 #define ENETC_PM0_CMD_CFG 0x8008
257 #define ENETC_PM0_TX_EN BIT(0)
258 #define ENETC_PM0_RX_EN BIT(1)
259 #define ENETC_PM0_PROMISC BIT(4)
260 #define ENETC_PM0_PAUSE_IGN BIT(8)
261 #define ENETC_PM0_CMD_XGLP BIT(10)
262 #define ENETC_PM0_CMD_TXP BIT(11)
263 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
264 #define ENETC_PM0_CMD_SFD BIT(21)
265 #define ENETC_PM0_MAXFRM 0x8014
266 #define ENETC_SET_TX_MTU(val) ((val) << 16)
267 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
268 #define ENETC_PM0_RX_FIFO 0x801c
269 #define ENETC_PM0_RX_FIFO_VAL 1
270
271 #define ENETC_PM_IMDIO_BASE 0x8030
272
273 #define ENETC_PM0_PAUSE_QUANTA 0x8054
274 #define ENETC_PM0_PAUSE_THRESH 0x8064
275
276 #define ENETC_PM0_SINGLE_STEP 0x80c0
277 #define ENETC_PM0_SINGLE_STEP_CH BIT(7)
278 #define ENETC_PM0_SINGLE_STEP_EN BIT(31)
279 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
280
281 #define ENETC_PM0_IF_MODE 0x8300
282 #define ENETC_PM0_IFM_RG BIT(2)
283 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
284 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
285 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)
286 #define ENETC_PM0_IFM_SSP_1000 (2 << 13)
287 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
288 #define ENETC_PM0_IFM_SSP_10 (1 << 13)
289 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
290 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
291 #define ENETC_PM0_IFM_IFMODE_XGMII 0
292 #define ENETC_PM0_IFM_IFMODE_GMII 2
293 #define ENETC_PSIDCAPR 0x1b08
294 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
295 #define ENETC_PSFCAPR 0x1b18
296 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
297 #define ENETC_PSGCAPR 0x1b28
298 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)
299 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
300 #define ENETC_PFMCAPR 0x1b38
301 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
302
303 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
304 * Port MAC 1 to the pMAC.
305 */
306 #define ENETC_PM_REOCT(mac) (0x8100 + ENETC_PMAC_OFFSET * (mac))
307 #define ENETC_PM_RALN(mac) (0x8110 + ENETC_PMAC_OFFSET * (mac))
308 #define ENETC_PM_RXPF(mac) (0x8118 + ENETC_PMAC_OFFSET * (mac))
309 #define ENETC_PM_RFRM(mac) (0x8120 + ENETC_PMAC_OFFSET * (mac))
310 #define ENETC_PM_RFCS(mac) (0x8128 + ENETC_PMAC_OFFSET * (mac))
311 #define ENETC_PM_RVLAN(mac) (0x8130 + ENETC_PMAC_OFFSET * (mac))
312 #define ENETC_PM_RERR(mac) (0x8138 + ENETC_PMAC_OFFSET * (mac))
313 #define ENETC_PM_RUCA(mac) (0x8140 + ENETC_PMAC_OFFSET * (mac))
314 #define ENETC_PM_RMCA(mac) (0x8148 + ENETC_PMAC_OFFSET * (mac))
315 #define ENETC_PM_RBCA(mac) (0x8150 + ENETC_PMAC_OFFSET * (mac))
316 #define ENETC_PM_RDRP(mac) (0x8158 + ENETC_PMAC_OFFSET * (mac))
317 #define ENETC_PM_RPKT(mac) (0x8160 + ENETC_PMAC_OFFSET * (mac))
318 #define ENETC_PM_RUND(mac) (0x8168 + ENETC_PMAC_OFFSET * (mac))
319 #define ENETC_PM_R64(mac) (0x8170 + ENETC_PMAC_OFFSET * (mac))
320 #define ENETC_PM_R127(mac) (0x8178 + ENETC_PMAC_OFFSET * (mac))
321 #define ENETC_PM_R255(mac) (0x8180 + ENETC_PMAC_OFFSET * (mac))
322 #define ENETC_PM_R511(mac) (0x8188 + ENETC_PMAC_OFFSET * (mac))
323 #define ENETC_PM_R1023(mac) (0x8190 + ENETC_PMAC_OFFSET * (mac))
324 #define ENETC_PM_R1522(mac) (0x8198 + ENETC_PMAC_OFFSET * (mac))
325 #define ENETC_PM_R1523X(mac) (0x81A0 + ENETC_PMAC_OFFSET * (mac))
326 #define ENETC_PM_ROVR(mac) (0x81A8 + ENETC_PMAC_OFFSET * (mac))
327 #define ENETC_PM_RJBR(mac) (0x81B0 + ENETC_PMAC_OFFSET * (mac))
328 #define ENETC_PM_RFRG(mac) (0x81B8 + ENETC_PMAC_OFFSET * (mac))
329 #define ENETC_PM_RCNP(mac) (0x81C0 + ENETC_PMAC_OFFSET * (mac))
330 #define ENETC_PM_RDRNTP(mac) (0x81C8 + ENETC_PMAC_OFFSET * (mac))
331 #define ENETC_PM_TEOCT(mac) (0x8200 + ENETC_PMAC_OFFSET * (mac))
332 #define ENETC_PM_TOCT(mac) (0x8208 + ENETC_PMAC_OFFSET * (mac))
333 #define ENETC_PM_TCRSE(mac) (0x8210 + ENETC_PMAC_OFFSET * (mac))
334 #define ENETC_PM_TXPF(mac) (0x8218 + ENETC_PMAC_OFFSET * (mac))
335 #define ENETC_PM_TFRM(mac) (0x8220 + ENETC_PMAC_OFFSET * (mac))
336 #define ENETC_PM_TFCS(mac) (0x8228 + ENETC_PMAC_OFFSET * (mac))
337 #define ENETC_PM_TVLAN(mac) (0x8230 + ENETC_PMAC_OFFSET * (mac))
338 #define ENETC_PM_TERR(mac) (0x8238 + ENETC_PMAC_OFFSET * (mac))
339 #define ENETC_PM_TUCA(mac) (0x8240 + ENETC_PMAC_OFFSET * (mac))
340 #define ENETC_PM_TMCA(mac) (0x8248 + ENETC_PMAC_OFFSET * (mac))
341 #define ENETC_PM_TBCA(mac) (0x8250 + ENETC_PMAC_OFFSET * (mac))
342 #define ENETC_PM_TPKT(mac) (0x8260 + ENETC_PMAC_OFFSET * (mac))
343 #define ENETC_PM_TUND(mac) (0x8268 + ENETC_PMAC_OFFSET * (mac))
344 #define ENETC_PM_T64(mac) (0x8270 + ENETC_PMAC_OFFSET * (mac))
345 #define ENETC_PM_T127(mac) (0x8278 + ENETC_PMAC_OFFSET * (mac))
346 #define ENETC_PM_T255(mac) (0x8280 + ENETC_PMAC_OFFSET * (mac))
347 #define ENETC_PM_T511(mac) (0x8288 + ENETC_PMAC_OFFSET * (mac))
348 #define ENETC_PM_T1023(mac) (0x8290 + ENETC_PMAC_OFFSET * (mac))
349 #define ENETC_PM_T1522(mac) (0x8298 + ENETC_PMAC_OFFSET * (mac))
350 #define ENETC_PM_T1523X(mac) (0x82A0 + ENETC_PMAC_OFFSET * (mac))
351 #define ENETC_PM_TCNP(mac) (0x82C0 + ENETC_PMAC_OFFSET * (mac))
352 #define ENETC_PM_TDFR(mac) (0x82D0 + ENETC_PMAC_OFFSET * (mac))
353 #define ENETC_PM_TMCOL(mac) (0x82D8 + ENETC_PMAC_OFFSET * (mac))
354 #define ENETC_PM_TSCOL(mac) (0x82E0 + ENETC_PMAC_OFFSET * (mac))
355 #define ENETC_PM_TLCOL(mac) (0x82E8 + ENETC_PMAC_OFFSET * (mac))
356 #define ENETC_PM_TECOL(mac) (0x82F0 + ENETC_PMAC_OFFSET * (mac))
357
358 /* Port counters */
359 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
360 #define ENETC_PBFDSIR 0x0810
361 #define ENETC_PFDMSAPR 0x0814
362 #define ENETC_UFDMF 0x1680
363 #define ENETC_MFDMF 0x1684
364 #define ENETC_PUFDVFR 0x1780
365 #define ENETC_PMFDVFR 0x1784
366 #define ENETC_PBFDVFR 0x1788
367
368 /** Global regs, offset: 2_0000h */
369 #define ENETC_GLOBAL_BASE 0x20000
370 #define ENETC_G_EIPBRR0 0x0bf8
371 #define ENETC_G_EIPBRR1 0x0bfc
372 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
373 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
374
375 /* PCI device info */
376 struct enetc_hw {
377 /* SI registers, used by all PCI functions */
378 void __iomem *reg;
379 /* Port registers, PF only */
380 void __iomem *port;
381 /* IP global registers, PF only */
382 void __iomem *global;
383 };
384
385 /* ENETC register accessors */
386
387 /* MDIO issue workaround (on LS1028A) -
388 * Due to a hardware issue, an access to MDIO registers
389 * that is concurrent with other ENETC register accesses
390 * may lead to the MDIO access being dropped or corrupted.
391 * To protect the MDIO accesses a readers-writers locking
392 * scheme is used, where the MDIO register accesses are
393 * protected by write locks to insure exclusivity, while
394 * the remaining ENETC registers are accessed under read
395 * locks since they only compete with MDIO accesses.
396 */
397 extern rwlock_t enetc_mdio_lock;
398
399 /* use this locking primitive only on the fast datapath to
400 * group together multiple non-MDIO register accesses to
401 * minimize the overhead of the lock
402 */
enetc_lock_mdio(void)403 static inline void enetc_lock_mdio(void)
404 {
405 read_lock(&enetc_mdio_lock);
406 }
407
enetc_unlock_mdio(void)408 static inline void enetc_unlock_mdio(void)
409 {
410 read_unlock(&enetc_mdio_lock);
411 }
412
413 /* use these accessors only on the fast datapath under
414 * the enetc_lock_mdio() locking primitive to minimize
415 * the overhead of the lock
416 */
enetc_rd_reg_hot(void __iomem * reg)417 static inline u32 enetc_rd_reg_hot(void __iomem *reg)
418 {
419 lockdep_assert_held(&enetc_mdio_lock);
420
421 return ioread32(reg);
422 }
423
enetc_wr_reg_hot(void __iomem * reg,u32 val)424 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val)
425 {
426 lockdep_assert_held(&enetc_mdio_lock);
427
428 iowrite32(val, reg);
429 }
430
431 /* internal helpers for the MDIO w/a */
_enetc_rd_reg_wa(void __iomem * reg)432 static inline u32 _enetc_rd_reg_wa(void __iomem *reg)
433 {
434 u32 val;
435
436 enetc_lock_mdio();
437 val = ioread32(reg);
438 enetc_unlock_mdio();
439
440 return val;
441 }
442
_enetc_wr_reg_wa(void __iomem * reg,u32 val)443 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val)
444 {
445 enetc_lock_mdio();
446 iowrite32(val, reg);
447 enetc_unlock_mdio();
448 }
449
_enetc_rd_mdio_reg_wa(void __iomem * reg)450 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg)
451 {
452 unsigned long flags;
453 u32 val;
454
455 write_lock_irqsave(&enetc_mdio_lock, flags);
456 val = ioread32(reg);
457 write_unlock_irqrestore(&enetc_mdio_lock, flags);
458
459 return val;
460 }
461
_enetc_wr_mdio_reg_wa(void __iomem * reg,u32 val)462 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val)
463 {
464 unsigned long flags;
465
466 write_lock_irqsave(&enetc_mdio_lock, flags);
467 iowrite32(val, reg);
468 write_unlock_irqrestore(&enetc_mdio_lock, flags);
469 }
470
471 #ifdef ioread64
_enetc_rd_reg64(void __iomem * reg)472 static inline u64 _enetc_rd_reg64(void __iomem *reg)
473 {
474 return ioread64(reg);
475 }
476 #else
477 /* using this to read out stats on 32b systems */
_enetc_rd_reg64(void __iomem * reg)478 static inline u64 _enetc_rd_reg64(void __iomem *reg)
479 {
480 u32 low, high, tmp;
481
482 do {
483 high = ioread32(reg + 4);
484 low = ioread32(reg);
485 tmp = ioread32(reg + 4);
486 } while (high != tmp);
487
488 return le64_to_cpu((__le64)high << 32 | low);
489 }
490 #endif
491
_enetc_rd_reg64_wa(void __iomem * reg)492 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg)
493 {
494 u64 val;
495
496 enetc_lock_mdio();
497 val = _enetc_rd_reg64(reg);
498 enetc_unlock_mdio();
499
500 return val;
501 }
502
503 /* general register accessors */
504 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg))
505 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val))
506 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
507 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
508 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off))
509 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val)
510 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off))
511 /* port register accessors - PF only */
512 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
513 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
514 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off))
515 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\
516 (hw)->port + (off), val)
517 /* global register accessors - PF only */
518 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
519 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
520 /* BDR register accessors, see ENETC_BDR() */
521 #define enetc_bdr_rd(hw, t, n, off) \
522 enetc_rd(hw, ENETC_BDR(t, n, off))
523 #define enetc_bdr_wr(hw, t, n, off, val) \
524 enetc_wr(hw, ENETC_BDR(t, n, off), val)
525 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
526 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
527 #define enetc_txbdr_wr(hw, n, off, val) \
528 enetc_bdr_wr(hw, TX, n, off, val)
529 #define enetc_rxbdr_wr(hw, n, off, val) \
530 enetc_bdr_wr(hw, RX, n, off, val)
531
532 /* Buffer Descriptors (BD) */
533 union enetc_tx_bd {
534 struct {
535 __le64 addr;
536 __le16 buf_len;
537 __le16 frm_len;
538 union {
539 struct {
540 u8 reserved[3];
541 u8 flags;
542 }; /* default layout */
543 __le32 txstart;
544 __le32 lstatus;
545 };
546 };
547 struct {
548 __le32 tstamp;
549 __le16 tpid;
550 __le16 vid;
551 u8 reserved[6];
552 u8 e_flags;
553 u8 flags;
554 } ext; /* Tx BD extension */
555 struct {
556 __le32 tstamp;
557 u8 reserved[10];
558 u8 status;
559 u8 flags;
560 } wb; /* writeback descriptor */
561 };
562
563 enum enetc_txbd_flags {
564 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
565 ENETC_TXBD_FLAGS_TSE = BIT(1),
566 ENETC_TXBD_FLAGS_W = BIT(2),
567 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */
568 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
569 ENETC_TXBD_FLAGS_EX = BIT(6),
570 ENETC_TXBD_FLAGS_F = BIT(7)
571 };
572 #define ENETC_TXBD_STATS_WIN BIT(7)
573 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
574 #define ENETC_TXBD_FLAGS_OFFSET 24
575
enetc_txbd_set_tx_start(u64 tx_start,u8 flags)576 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags)
577 {
578 u32 temp;
579
580 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) |
581 (flags << ENETC_TXBD_FLAGS_OFFSET);
582
583 return cpu_to_le32(temp);
584 }
585
enetc_clear_tx_bd(union enetc_tx_bd * txbd)586 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
587 {
588 memset(txbd, 0, sizeof(*txbd));
589 }
590
591 /* Extension flags */
592 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
593 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1)
594 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
595
596 union enetc_rx_bd {
597 struct {
598 __le64 addr;
599 u8 reserved[8];
600 } w;
601 struct {
602 __le16 inet_csum;
603 __le16 parse_summary;
604 __le32 rss_hash;
605 __le16 buf_len;
606 __le16 vlan_opt;
607 union {
608 struct {
609 __le16 flags;
610 __le16 error;
611 };
612 __le32 lstatus;
613 };
614 } r;
615 struct {
616 __le32 tstamp;
617 u8 reserved[12];
618 } ext;
619 };
620
621 #define ENETC_RXBD_LSTATUS_R BIT(30)
622 #define ENETC_RXBD_LSTATUS_F BIT(31)
623 #define ENETC_RXBD_ERR_MASK 0xff
624 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
625 #define ENETC_RXBD_FLAG_VLAN BIT(9)
626 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
627 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
628
629 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
630 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
631 #define ENETC_MAX_NUM_VFS 2
632
633 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
634 #define ENETC_CBD_STATUS_MASK 0xf
635
636 struct enetc_cmd_rfse {
637 u8 smac_h[6];
638 u8 smac_m[6];
639 u8 dmac_h[6];
640 u8 dmac_m[6];
641 __be32 sip_h[4];
642 __be32 sip_m[4];
643 __be32 dip_h[4];
644 __be32 dip_m[4];
645 u16 ethtype_h;
646 u16 ethtype_m;
647 u16 ethtype4_h;
648 u16 ethtype4_m;
649 u16 sport_h;
650 u16 sport_m;
651 u16 dport_h;
652 u16 dport_m;
653 u16 vlan_h;
654 u16 vlan_m;
655 u8 proto_h;
656 u8 proto_m;
657 u16 flags;
658 u16 result;
659 u16 mode;
660 };
661
662 #define ENETC_RFSE_EN BIT(15)
663 #define ENETC_RFSE_MODE_BD 2
664
enetc_load_primary_mac_addr(struct enetc_hw * hw,struct net_device * ndev)665 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw,
666 struct net_device *ndev)
667 {
668 u8 addr[ETH_ALEN] __aligned(4);
669
670 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
671 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
672 eth_hw_addr_set(ndev, addr);
673 }
674
675 #define ENETC_SI_INT_IDX 0
676 /* base index for Rx/Tx interrupts */
677 #define ENETC_BDR_INT_BASE_IDX 1
678
679 /* Messaging */
680
681 /* Command completion status */
682 enum enetc_msg_cmd_status {
683 ENETC_MSG_CMD_STATUS_OK,
684 ENETC_MSG_CMD_STATUS_FAIL
685 };
686
687 /* VSI-PSI command message types */
688 enum enetc_msg_cmd_type {
689 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
690 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
691 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
692 };
693
694 /* VSI-PSI command action types */
695 enum enetc_msg_cmd_action_type {
696 ENETC_MSG_CMD_MNG_ADD = 1,
697 ENETC_MSG_CMD_MNG_REMOVE
698 };
699
700 /* PSI-VSI command header format */
701 struct enetc_msg_cmd_header {
702 u16 type; /* command class type */
703 u16 id; /* denotes the specific required action */
704 };
705
706 /* Common H/W utility functions */
707
enetc_bdr_enable_rxvlan(struct enetc_hw * hw,int idx,bool en)708 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx,
709 bool en)
710 {
711 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
712
713 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
714 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val);
715 }
716
enetc_bdr_enable_txvlan(struct enetc_hw * hw,int idx,bool en)717 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx,
718 bool en)
719 {
720 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
721
722 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
723 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val);
724 }
725
enetc_set_bdr_prio(struct enetc_hw * hw,int bdr_idx,int prio)726 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
727 int prio)
728 {
729 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
730
731 val &= ~ENETC_TBMR_PRIO_MASK;
732 val |= ENETC_TBMR_SET_PRIO(prio);
733 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
734 }
735
736 enum bdcr_cmd_class {
737 BDCR_CMD_UNSPEC = 0,
738 BDCR_CMD_MAC_FILTER,
739 BDCR_CMD_VLAN_FILTER,
740 BDCR_CMD_RSS,
741 BDCR_CMD_RFS,
742 BDCR_CMD_PORT_GCL,
743 BDCR_CMD_RECV_CLASSIFIER,
744 BDCR_CMD_STREAM_IDENTIFY,
745 BDCR_CMD_STREAM_FILTER,
746 BDCR_CMD_STREAM_GCL,
747 BDCR_CMD_FLOW_METER,
748 __BDCR_CMD_MAX_LEN,
749 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
750 };
751
752 /* class 5, command 0 */
753 struct tgs_gcl_conf {
754 u8 atc; /* init gate value */
755 u8 res[7];
756 struct {
757 u8 res1[4];
758 __le16 acl_len;
759 u8 res2[2];
760 };
761 };
762
763 /* gate control list entry */
764 struct gce {
765 __le32 period;
766 u8 gate;
767 u8 res[3];
768 };
769
770 /* tgs_gcl_conf address point to this data space */
771 struct tgs_gcl_data {
772 __le32 btl;
773 __le32 bth;
774 __le32 ct;
775 __le32 cte;
776 struct gce entry[];
777 };
778
779 /* class 7, command 0, Stream Identity Entry Configuration */
780 struct streamid_conf {
781 __le32 stream_handle; /* init gate value */
782 __le32 iports;
783 u8 id_type;
784 u8 oui[3];
785 u8 res[3];
786 u8 en;
787 };
788
789 #define ENETC_CBDR_SID_VID_MASK 0xfff
790 #define ENETC_CBDR_SID_VIDM BIT(12)
791 #define ENETC_CBDR_SID_TG_MASK 0xc000
792 /* streamid_conf address point to this data space */
793 struct streamid_data {
794 union {
795 u8 dmac[6];
796 u8 smac[6];
797 };
798 u16 vid_vidm_tg;
799 };
800
801 #define ENETC_CBDR_SFI_PRI_MASK 0x7
802 #define ENETC_CBDR_SFI_PRIM BIT(3)
803 #define ENETC_CBDR_SFI_BLOV BIT(4)
804 #define ENETC_CBDR_SFI_BLEN BIT(5)
805 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
806 #define ENETC_CBDR_SFI_FMITEN BIT(7)
807 #define ENETC_CBDR_SFI_ENABLE BIT(7)
808 /* class 8, command 0, Stream Filter Instance, Short Format */
809 struct sfi_conf {
810 __le32 stream_handle;
811 u8 multi;
812 u8 res[2];
813 u8 sthm;
814 /* Max Service Data Unit or Flow Meter Instance Table index.
815 * Depending on the value of FLT this represents either Max
816 * Service Data Unit (max frame size) allowed by the filter
817 * entry or is an index into the Flow Meter Instance table
818 * index identifying the policer which will be used to police
819 * it.
820 */
821 __le16 fm_inst_table_index;
822 __le16 msdu;
823 __le16 sg_inst_table_index;
824 u8 res1[2];
825 __le32 input_ports;
826 u8 res2[3];
827 u8 en;
828 };
829
830 /* class 8, command 2 stream Filter Instance status query short format
831 * command no need structure define
832 * Stream Filter Instance Query Statistics Response data
833 */
834 struct sfi_counter_data {
835 u32 matchl;
836 u32 matchh;
837 u32 msdu_dropl;
838 u32 msdu_droph;
839 u32 stream_gate_dropl;
840 u32 stream_gate_droph;
841 u32 flow_meter_dropl;
842 u32 flow_meter_droph;
843 };
844
845 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
846 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
847 #define ENETC_CBDR_SGI_CGTST BIT(6)
848 #define ENETC_CBDR_SGI_OGTST BIT(7)
849 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
850 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
851 #define ENETC_CBDR_SGI_OEX BIT(4)
852 #define ENETC_CBDR_SGI_OEXEN BIT(5)
853 #define ENETC_CBDR_SGI_IRX BIT(6)
854 #define ENETC_CBDR_SGI_IRXEN BIT(7)
855 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
856 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
857 #define ENETC_CBDR_SGI_EN BIT(7)
858 /* class 9, command 0, Stream Gate Instance Table, Short Format
859 * class 9, command 2, Stream Gate Instance Table entry query write back
860 * Short Format
861 */
862 struct sgi_table {
863 u8 res[8];
864 u8 oipv;
865 u8 res0[2];
866 u8 ocgtst;
867 u8 res1[7];
868 u8 gset;
869 u8 oacl_len;
870 u8 res2[2];
871 u8 en;
872 };
873
874 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
875 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
876 #define ENETC_CBDR_SGI_AGTST BIT(7)
877
878 /* class 9, command 1, Stream Gate Control List, Long Format */
879 struct sgcl_conf {
880 u8 aipv;
881 u8 res[2];
882 u8 agtst;
883 u8 res1[4];
884 union {
885 struct {
886 u8 res2[4];
887 u8 acl_len;
888 u8 res3[3];
889 };
890 u8 cct[8]; /* Config change time */
891 };
892 };
893
894 #define ENETC_CBDR_SGL_IOMEN BIT(0)
895 #define ENETC_CBDR_SGL_IPVEN BIT(3)
896 #define ENETC_CBDR_SGL_GTST BIT(4)
897 #define ENETC_CBDR_SGL_IPV_MASK 0xe
898 /* Stream Gate Control List Entry */
899 struct sgce {
900 u32 interval;
901 u8 msdu[3];
902 u8 multi;
903 };
904
905 /* stream control list class 9 , cmd 1 data buffer */
906 struct sgcl_data {
907 u32 btl;
908 u32 bth;
909 u32 ct;
910 u32 cte;
911 struct sgce sgcl[];
912 };
913
914 #define ENETC_CBDR_FMI_MR BIT(0)
915 #define ENETC_CBDR_FMI_MREN BIT(1)
916 #define ENETC_CBDR_FMI_DOY BIT(2)
917 #define ENETC_CBDR_FMI_CM BIT(3)
918 #define ENETC_CBDR_FMI_CF BIT(4)
919 #define ENETC_CBDR_FMI_NDOR BIT(5)
920 #define ENETC_CBDR_FMI_OALEN BIT(6)
921 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
922
923 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
924 struct fmi_conf {
925 __le32 cir;
926 __le32 cbs;
927 __le32 eir;
928 __le32 ebs;
929 u8 conf;
930 u8 res1;
931 u8 ir_fpp;
932 u8 res2[4];
933 u8 en;
934 };
935
936 struct enetc_cbd {
937 union{
938 struct sfi_conf sfi_conf;
939 struct sgi_table sgi_table;
940 struct fmi_conf fmi_conf;
941 struct {
942 __le32 addr[2];
943 union {
944 __le32 opt[4];
945 struct tgs_gcl_conf gcl_conf;
946 struct streamid_conf sid_set;
947 struct sgcl_conf sgcl_conf;
948 };
949 }; /* Long format */
950 __le32 data[6];
951 };
952 __le16 index;
953 __le16 length;
954 u8 cmd;
955 u8 cls;
956 u8 _res;
957 u8 status_flags;
958 };
959
960 #define ENETC_CLK 400000000ULL
enetc_cycles_to_usecs(u32 cycles)961 static inline u32 enetc_cycles_to_usecs(u32 cycles)
962 {
963 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK);
964 }
965
enetc_usecs_to_cycles(u32 usecs)966 static inline u32 enetc_usecs_to_cycles(u32 usecs)
967 {
968 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL);
969 }
970
971 /* Port traffic class frame preemption register */
972 #define ENETC_PTCFPR(n) (0x1910 + (n) * 4) /* n = [0 ..7] */
973 #define ENETC_PTCFPR_FPE BIT(31)
974
975 /* port time gating control register */
976 #define ENETC_PTGCR 0x11a00
977 #define ENETC_PTGCR_TGE BIT(31)
978 #define ENETC_PTGCR_TGPE BIT(30)
979
980 /* Port time gating capability register */
981 #define ENETC_PTGCAPR 0x11a08
982 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
983
984 /* Port time specific departure */
985 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
986 #define ENETC_TSDE BIT(31)
987
988 /* PSFP setting */
989 #define ENETC_PPSFPMR 0x11b00
990 #define ENETC_PPSFPMR_PSFPEN BIT(0)
991 #define ENETC_PPSFPMR_VS BIT(1)
992 #define ENETC_PPSFPMR_PVC BIT(2)
993 #define ENETC_PPSFPMR_PVZC BIT(3)
994