Lines Matching +full:uniphier +full:- +full:system +full:- +full:bus
1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
244 Patch phys-to-virt and virt-to-phys translation functions at
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
280 location of main memory in your system.
291 menu "System Type"
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
309 # The "ARM system type" choice list is ordered alphabetically by option
313 prompt "ARM system type"
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
349 bool "EBSA-110"
358 from Digital. It has limited hardware on-board, including an
363 bool "EP93xx-based"
391 bool "IOP32x-based"
404 bool "IXP4xx-based"
440 bool "PXA2xx/PXA3xx-based"
477 On the Acorn Risc-PC, Linux can support the internal IDE disk and
478 CD-ROM interface, serial and parallel port, and the floppy drive.
481 bool "SA1100-based"
579 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
608 # This is sorted alphabetically by mach-* pathname. However, plat-*
610 # plat- suffix) or along side the corresponding mach-* source.
612 source "arch/arm/mach-actions/Kconfig"
614 source "arch/arm/mach-alpine/Kconfig"
616 source "arch/arm/mach-artpec/Kconfig"
618 source "arch/arm/mach-asm9260/Kconfig"
620 source "arch/arm/mach-aspeed/Kconfig"
622 source "arch/arm/mach-at91/Kconfig"
624 source "arch/arm/mach-axxia/Kconfig"
626 source "arch/arm/mach-bcm/Kconfig"
628 source "arch/arm/mach-berlin/Kconfig"
630 source "arch/arm/mach-clps711x/Kconfig"
632 source "arch/arm/mach-cns3xxx/Kconfig"
634 source "arch/arm/mach-davinci/Kconfig"
636 source "arch/arm/mach-digicolor/Kconfig"
638 source "arch/arm/mach-dove/Kconfig"
640 source "arch/arm/mach-ep93xx/Kconfig"
642 source "arch/arm/mach-exynos/Kconfig"
644 source "arch/arm/mach-footbridge/Kconfig"
646 source "arch/arm/mach-gemini/Kconfig"
648 source "arch/arm/mach-highbank/Kconfig"
650 source "arch/arm/mach-hisi/Kconfig"
652 source "arch/arm/mach-imx/Kconfig"
654 source "arch/arm/mach-integrator/Kconfig"
656 source "arch/arm/mach-iop32x/Kconfig"
658 source "arch/arm/mach-ixp4xx/Kconfig"
660 source "arch/arm/mach-keystone/Kconfig"
662 source "arch/arm/mach-lpc32xx/Kconfig"
664 source "arch/arm/mach-mediatek/Kconfig"
666 source "arch/arm/mach-meson/Kconfig"
668 source "arch/arm/mach-milbeaut/Kconfig"
670 source "arch/arm/mach-mmp/Kconfig"
672 source "arch/arm/mach-moxart/Kconfig"
674 source "arch/arm/mach-mstar/Kconfig"
676 source "arch/arm/mach-mv78xx0/Kconfig"
678 source "arch/arm/mach-mvebu/Kconfig"
680 source "arch/arm/mach-mxs/Kconfig"
682 source "arch/arm/mach-nomadik/Kconfig"
684 source "arch/arm/mach-npcm/Kconfig"
686 source "arch/arm/mach-nspire/Kconfig"
688 source "arch/arm/plat-omap/Kconfig"
690 source "arch/arm/mach-omap1/Kconfig"
692 source "arch/arm/mach-omap2/Kconfig"
694 source "arch/arm/mach-orion5x/Kconfig"
696 source "arch/arm/mach-oxnas/Kconfig"
698 source "arch/arm/mach-picoxcell/Kconfig"
700 source "arch/arm/mach-prima2/Kconfig"
702 source "arch/arm/mach-pxa/Kconfig"
703 source "arch/arm/plat-pxa/Kconfig"
705 source "arch/arm/mach-qcom/Kconfig"
707 source "arch/arm/mach-rda/Kconfig"
709 source "arch/arm/mach-realtek/Kconfig"
711 source "arch/arm/mach-realview/Kconfig"
713 source "arch/arm/mach-rockchip/Kconfig"
715 source "arch/arm/mach-s3c/Kconfig"
717 source "arch/arm/mach-s5pv210/Kconfig"
719 source "arch/arm/mach-sa1100/Kconfig"
721 source "arch/arm/mach-shmobile/Kconfig"
723 source "arch/arm/mach-socfpga/Kconfig"
725 source "arch/arm/mach-spear/Kconfig"
727 source "arch/arm/mach-sti/Kconfig"
729 source "arch/arm/mach-stm32/Kconfig"
731 source "arch/arm/mach-sunxi/Kconfig"
733 source "arch/arm/mach-tango/Kconfig"
735 source "arch/arm/mach-tegra/Kconfig"
737 source "arch/arm/mach-u300/Kconfig"
739 source "arch/arm/mach-uniphier/Kconfig"
741 source "arch/arm/mach-ux500/Kconfig"
743 source "arch/arm/mach-versatile/Kconfig"
745 source "arch/arm/mach-vexpress/Kconfig"
747 source "arch/arm/mach-vt8500/Kconfig"
749 source "arch/arm/mach-zx/Kconfig"
751 source "arch/arm/mach-zynq/Kconfig"
753 # ARMv7-M architecture
770 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
779 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
780 with a range of available cores like Cortex-M3/M4/M7.
821 source "arch/arm/Kconfig-nommu"
839 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
842 Executing a SWP instruction to read-only memory does not set bit 11
860 This option enables the workaround for the 430973 Cortex-A8
863 same virtual address, whether due to self-modifying code or virtual
864 to physical address re-mapping, Cortex-A8 does not recover from the
865 stale interworking branch prediction. This results in Cortex-A8
870 available in non-secure mode.
877 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
884 register may not be available in non-secure mode.
891 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
895 workaround disables the write-allocate mode for the L2 cache via the
897 may not be available in non-secure mode.
904 This option enables the workaround for the 742230 Cortex-A9
908 the diagnostic register of the Cortex-A9 which causes the DMB
917 This option enables the workaround for the 742231 Cortex-A9
919 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
924 register of the Cortex-A9 which reduces the linefill issuing
932 This option enables the workaround for the 643719 Cortex-A9 (prior to
942 This option enables the workaround for the 720789 Cortex-A9 (prior to
946 invalidated are not, resulting in an incoherency in the system page
955 This option enables the workaround for the 743622 Cortex-A9
957 optimisation in the Cortex-A9 Store Buffer may lead to data
959 register of the Cortex-A9 which disables the Store Buffer
969 This option enables the workaround for the 751472 Cortex-A9 (prior
979 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
982 can populate the micro-TLB with a stale entry which may be hit with
990 This option enables the workaround for the 754327 Cortex-A9 (prior to
998 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1003 hit-under-miss enabled). It sets the undocumented bit 31 in
1005 register, thus disabling hit-under-miss without putting the
1014 affecting Cortex-A9 MPCore with two or more processors (all
1019 system. This workaround adds a DSB instruction before the
1027 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1034 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1037 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1047 This option enables the workaround for the 773022 Cortex-A15
1057 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1059 - Cortex-A12 852422: Execution of a sequence of instructions might
1061 any Cortex-A12 cores yet.
1070 This option enables the workaround for the 821420 Cortex-A12
1074 deadlock when the VMOV instructions are issued out-of-order.
1080 This option enables the workaround for the 825619 Cortex-A12
1083 and Device/Strongly-Ordered loads and stores might cause deadlock
1089 This option enables the workaround for the 857271 Cortex-A12
1097 This option enables the workaround for the 852421 Cortex-A17
1107 - Cortex-A17 852423: Execution of a sequence of instructions might
1109 any Cortex-A17 cores yet.
1110 This is identical to Cortex-A12 erratum 852422. It is a separate
1118 This option enables the workaround for the 857272 Cortex-A17 erratum.
1120 This is identical to Cortex-A12 erratum 857271. It is a separate
1128 menu "Bus support"
1134 name of a bus system, i.e. the way the CPU talks to the other stuff
1135 inside your box. Other bus systems are PCI, EISA, MicroChannel
1136 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1173 This option should be selected by machines which have an SMP-
1176 The only effect of this option is to make the SMP-related
1180 bool "Symmetric Multi-Processing"
1188 a system with only one CPU, say N. If you have a system with more
1191 If you say N here, the kernel will run on uni- and multiprocessor
1197 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1208 SMP kernels contain instructions which fail on non-SMP processors.
1222 topology of an ARM System.
1225 bool "Multi-core scheduler support"
1228 Multi-core scheduler support improves the CPU scheduler's decision
1229 making when dealing with multi-core CPU chips at a cost of slightly
1258 bool "Multi-Cluster Power Management"
1262 for (multi-)cluster based systems, such as big.LITTLE based
1280 system architecture.
1289 and a cluster of A7's in a big.LITTLE system.
1338 int "Maximum number of CPUs (2-32)"
1344 bool "Support for hot-pluggable CPUs"
1349 can be controlled through /sys/devices/system/cpu.
1356 Say Y here if you want Linux to communicate with system firmware
1357 implementing the PSCI specification for CPU-centric power
1359 0022A ("Power State Coordination Interface System Software on
1379 Maximum number of GPIOs in the system.
1427 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1433 Thumb-2 mode.
1483 The seccomp filter system will not be available when this is
1524 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1532 user-space 2nd level page tables to reside in high memory.
1535 bool "Enable use of CPU domains to implement privileged no-access"
1541 use-after-free bugs becoming an exploitable privilege escalation
1545 CPUs with low-vector mappings use a best-efforts implementation.
1578 Disabling this is usually safe for small single-platform
1604 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1605 address divisible by 4. On 32-bit ARM processors, these non-aligned
1608 correct operation of some network protocols. With an IP-only
1617 cores where a 8-word STM instruction give significantly higher
1624 However, if the CPU data cache is using a write-allocate mode,
1673 the entire duration that the system is up.
1729 The physical address at which the ROM-able zImage is to be
1731 ROM-able zImage formats normally set this to a suitable
1741 for the ROM-able zImage which must be available while the
1744 Platforms which normally make use of ROM-able zImage formats
1796 Uses the command-line options passed by the boot loader instead of
1803 The command-line arguments provided by the boot loader will be
1814 architectures, you should supply some command-line options at build
1825 Uses the command-line options passed by the boot loader. If
1832 The command-line arguments provided by the boot loader will be
1841 command-line options your boot loader passes to the kernel.
1845 bool "Kernel Execute-In-Place from ROM"
1848 Execute-In-Place allows the kernel to run from non-volatile storage
1851 to RAM. Read-write sections, such as the data section and stack,
1886 bool "Kexec system call (EXPERIMENTAL)"
1891 kexec is a system call that implements the ability to shutdown your
1893 but it is independent of the system firmware. And like a reboot
1913 loaded in the main kernel with kexec-tools into a specially
1918 For more details see Documentation/admin-guide/kdump/kdump.rst
1925 will be determined at run-time by masking the current IP with
1942 by UEFI firmware (such as non-volatile variables, realtime
1957 continue to boot on existing non-UEFI platforms.
1963 to be enabled much earlier than we do on ARM, which is non-trivial.
1986 your machine has an FPA or floating point co-processor podule.
1995 Say Y to include 80-bit support in the kernel floating-point
1996 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1997 Note that gcc does not generate 80-bit operations by default,
2010 It is very simple, and approximately 3-6 times faster than NWFPE.
2018 bool "VFP-format floating point maths"
2024 Please see <file:Documentation/arm/vfp/release-notes.rst> for