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1 # SPDX-License-Identifier: GPL-2.0-only
5 Mailbox is a framework to control hardware communication between
6 on-chip processors through queued messages and interrupt driven
17 used in Secure mode only.
33 which can be used in Secure mode only.
41 send short messages between Highbank's A9 cores and the EnergyCore
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
60 interprocessor communication involving DSP, IVA1.0 and IVA2 in
61 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
77 This driver provides support for inter-processor communication
78 between CPU cores and MCU processor on Some Rockchip SOCs.
88 between the OS and a platform such as the BMC. This medium
99 to send message between processors. Say Y here if you want to use the
124 and K3 architecture SoCs. These may be used for communication between
135 between application processors and other processors/MCU/DSP. Select
145 between application processors and MCU. Say Y here if you want to
161 providing an interface for invoking the inter-process communication
169 between different remote processors and host processors on Tegra186
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
179 It is used to send short messages between ARM64-bit cores and
181 want to use the APM X-Gene SLIMpro IPCM support.
207 with hardware for Inter-Processor Communication Controller (IPCC)
208 between processors. Say Y here if you want to have this support.
226 between processors with Xilinx ZynqMP IPI. It will place the
235 Mailbox implementation for the hardware message box present in
237 between the application CPUs and the power management coprocessor.
244 to send message between application processors and MCU. Say Y here if
251 Qualcomm Technologies, Inc. Inter-Processor Communication Controller