Lines Matching +full:0 +full:x4a8
32 #define DMA_MAX_BURST_LENGTH 0x10
36 #define CLEAR_ALL_HFB 0xFF
51 #define STATUS_RX_EXT_MASK 0x1FFFFF
52 #define STATUS_RX_CSUM_MASK 0xFFFF
53 #define STATUS_RX_CSUM_OK 0x10000
54 #define STATUS_RX_CSUM_FR 0x20000
55 #define STATUS_RX_PROTO_TCP 0
61 #define STATUS_FILTER_INDEX_MASK 0xFFFF
63 #define STATUS_TX_CSUM_START_MASK 0X7FFF
65 #define STATUS_TX_CSUM_PROTO_UDP 0x8000
66 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
67 #define STATUS_TX_CSUM_LV 0x80000000
70 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
71 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
72 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
91 u32 pkt; /* RO (0x428) Received pkt count*/
109 u32 rcrc; /* RO (0x470),# of CRC match pkt */
115 u32 pkts; /* RO (0x4a8) Transmited pkt */
133 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */
153 #define UMAC_HD_BKP_CTRL 0x004
154 #define HD_FC_EN (1 << 0)
157 #define IPG_CONFIG_RX_MASK 0x1F
159 #define UMAC_CMD 0x008
160 #define CMD_TX_EN (1 << 0)
162 #define UMAC_SPEED_10 0
186 #define UMAC_MAC0 0x00C
187 #define UMAC_MAC1 0x010
188 #define UMAC_MAX_FRAME_LEN 0x014
190 #define UMAC_MODE 0x44
193 #define UMAC_EEE_CTRL 0x064
194 #define EN_LPI_RX_PAUSE (1 << 0)
203 #define UMAC_EEE_LPI_TIMER 0x068
204 #define UMAC_EEE_WAKE_TIMER 0x06C
205 #define UMAC_EEE_REF_COUNT 0x070
206 #define EEE_REFERENCE_COUNT_MASK 0xffff
208 #define UMAC_TX_FLUSH 0x334
210 #define UMAC_MIB_START 0x400
212 #define UMAC_MDIO_CMD 0x614
218 #define MDIO_PMD_MASK 0x1F
220 #define MDIO_REG_MASK 0x1F
222 #define UMAC_RBUF_OVFL_CNT_V1 0x61C
223 #define RBUF_OVFL_CNT_V2 0x80
224 #define RBUF_OVFL_CNT_V3PLUS 0x94
226 #define UMAC_MPD_CTRL 0x620
227 #define MPD_EN (1 << 0)
230 #define MPD_MSEQ_LEN_MASK 0xFF
232 #define UMAC_MPD_PW_MS 0x624
233 #define UMAC_MPD_PW_LS 0x628
234 #define UMAC_RBUF_ERR_CNT_V1 0x634
235 #define RBUF_ERR_CNT_V2 0x84
236 #define RBUF_ERR_CNT_V3PLUS 0x98
237 #define UMAC_MDF_ERR_CNT 0x638
238 #define UMAC_MDF_CTRL 0x650
239 #define UMAC_MDF_ADDR 0x654
240 #define UMAC_MIB_CTRL 0x580
241 #define MIB_RESET_RX (1 << 0)
245 #define RBUF_CTRL 0x00
246 #define RBUF_64B_EN (1 << 0)
250 #define RBUF_STATUS 0x0C
251 #define RBUF_STATUS_WOL (1 << 0)
255 #define RBUF_CHK_CTRL 0x14
256 #define RBUF_RXCHK_EN (1 << 0)
260 #define RBUF_ENERGY_CTRL 0x9c
261 #define RBUF_EEE_EN (1 << 0)
264 #define RBUF_TBUF_SIZE_CTRL 0xb4
266 #define RBUF_HFB_CTRL_V1 0x38
268 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000
269 #define RBUF_HFB_EN (1 << 0)
273 #define RBUF_HFB_LEN_V1 0x3C
274 #define RBUF_FLTR_LEN_MASK 0xFF
277 #define TBUF_CTRL 0x00
278 #define TBUF_64B_EN (1 << 0)
279 #define TBUF_BP_MC 0x0C
280 #define TBUF_ENERGY_CTRL 0x14
281 #define TBUF_EEE_EN (1 << 0)
284 #define TBUF_CTRL_V1 0x80
285 #define TBUF_BP_MC_V1 0xA0
287 #define HFB_CTRL 0x00
288 #define HFB_FLT_ENABLE_V3PLUS 0x04
289 #define HFB_FLT_LEN_V2 0x04
290 #define HFB_FLT_LEN_V3PLUS 0x1C
293 #define INTRL2_CPU_STAT 0x00
294 #define INTRL2_CPU_SET 0x04
295 #define INTRL2_CPU_CLEAR 0x08
296 #define INTRL2_CPU_MASK_STATUS 0x0C
297 #define INTRL2_CPU_MASK_SET 0x10
298 #define INTRL2_CPU_MASK_CLEAR 0x14
300 /* INTRL2 instance 0 definitions */
301 #define UMAC_IRQ_SCB (1 << 0)
331 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
332 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
336 #define GENET_SYS_OFF 0x0000
337 #define GENET_GR_BRIDGE_OFF 0x0040
338 #define GENET_EXT_OFF 0x0080
339 #define GENET_INTRL2_0_OFF 0x0200
340 #define GENET_INTRL2_1_OFF 0x0240
341 #define GENET_RBUF_OFF 0x0300
342 #define GENET_UMAC_OFF 0x0800
345 #define SYS_REV_CTRL 0x00
346 #define SYS_PORT_CTRL 0x04
347 #define PORT_MODE_INT_EPHY 0
355 #define SYS_RBUF_FLUSH_CTRL 0x08
356 #define SYS_TBUF_FLUSH_CTRL 0x0C
357 #define RBUF_FLUSH_CTRL_V1 0x04
360 #define EXT_EXT_PWR_MGMT 0x00
361 #define EXT_PWR_DOWN_BIAS (1 << 0)
376 #define EXT_RGMII_OOB_CTRL 0x0C
377 #define RGMII_MODE_EN_V123 (1 << 0)
383 #define EXT_GPHY_CTRL 0x1C
384 #define EXT_CFG_IDDQ_BIAS (1 << 0)
390 #define DMA_RING_SIZE (0x40)
394 #define DMA_RW_POINTER_MASK 0x1FF
395 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
397 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
399 #define DMA_P_INDEX_MASK 0xFFFF
400 #define DMA_C_INDEX_MASK 0xFFFF
403 #define DMA_RING_SIZE_MASK 0xFFFF
405 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
408 #define DMA_INTR_THRESHOLD_MASK 0x01FF
411 #define DMA_XON_THREHOLD_MASK 0xFFFF
412 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF
416 #define DMA_FLOW_PERIOD_MASK 0xFFFF
417 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF
422 #define DMA_EN (1 << 0)
423 #define DMA_RING_BUF_EN_SHIFT 0x01
424 #define DMA_RING_BUF_EN_MASK 0xFFFF
428 #define DMA_DISABLED (1 << 0)
432 #define DMA_SCB_BURST_SIZE_MASK 0x1F
435 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
438 #define DMA_BACKPRESSURE_MASK 0x1FFFF
442 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
445 #define DMA_LITTLE_ENDIAN_MODE (1 << 0)
449 #define DMA_TIMEOUT_MASK 0xFFFF
453 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF
456 #define DMA_ARBITER_MODE_MASK 0x03
457 #define DMA_RING_BUF_PRIORITY_MASK 0x1F
461 #define DMA_RATE_ADJ_MASK 0xFF
464 #define DMA_BUFLENGTH_MASK 0x0fff
466 #define DMA_OWN 0x8000
467 #define DMA_EOP 0x4000
468 #define DMA_SOP 0x2000
469 #define DMA_WRAP 0x1000
471 #define DMA_TX_UNDERRUN 0x0200
472 #define DMA_TX_APPEND_CRC 0x0040
473 #define DMA_TX_OW_CRC 0x0020
474 #define DMA_TX_DO_CSUM 0x0010
478 #define DMA_RX_CHK_V3PLUS 0x8000
479 #define DMA_RX_CHK_V12 0x1000
480 #define DMA_RX_BRDCAST 0x0040
481 #define DMA_RX_MULT 0x0020
482 #define DMA_RX_LG 0x0010
483 #define DMA_RX_NO 0x0008
484 #define DMA_RX_RXER 0x0004
485 #define DMA_RX_CRC_ERROR 0x0002
486 #define DMA_RX_OV 0x0001
487 #define DMA_RX_FI_MASK 0x001F
488 #define DMA_RX_FI_SHIFT 0x0007
489 #define DMA_DESC_ALLOC_MASK 0x00FF
491 #define DMA_ARBITER_RR 0x00
492 #define DMA_ARBITER_WRR 0x01
493 #define DMA_ARBITER_SP 0x02
504 GENET_POWER_CABLE_SENSE = 0,
529 #define GENET_HAS_40BITS (1 << 0)
616 BCMGENET_RXNFC_STATE_UNUSED = 0,