Lines Matching +full:sg +full:- +full:micro
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
34 #include <linux/dma-mapping.h>
45 #include "amba-pl011.h"
226 struct scatterlist sg; member
248 struct scatterlist sg; member
264 unsigned int fifosize; /* vendor-specific */
266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
281 return uap->reg_offset[reg]; in pl011_reg_to_offset()
287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
289 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
298 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
323 uap->port.icount.rx++; in pl011_fifo_to_tty()
328 uap->port.icount.brk++; in pl011_fifo_to_tty()
329 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
332 uap->port.icount.parity++; in pl011_fifo_to_tty()
334 uap->port.icount.frame++; in pl011_fifo_to_tty()
336 uap->port.icount.overrun++; in pl011_fifo_to_tty()
338 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
348 spin_unlock(&uap->port.lock); in pl011_fifo_to_tty()
349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
350 spin_lock(&uap->port.lock); in pl011_fifo_to_tty()
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, in pl011_sgbuf_init() argument
374 sg->buf = dma_alloc_coherent(chan->device->dev, in pl011_sgbuf_init()
376 if (!sg->buf) in pl011_sgbuf_init()
377 return -ENOMEM; in pl011_sgbuf_init()
379 sg_init_table(&sg->sg, 1); in pl011_sgbuf_init()
380 sg_set_page(&sg->sg, phys_to_page(dma_addr), in pl011_sgbuf_init()
382 sg_dma_address(&sg->sg) = dma_addr; in pl011_sgbuf_init()
383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; in pl011_sgbuf_init()
388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, in pl011_sgbuf_free() argument
391 if (sg->buf) { in pl011_sgbuf_free()
392 dma_free_coherent(chan->device->dev, in pl011_sgbuf_free()
393 PL011_DMA_BUFFER_SIZE, sg->buf, in pl011_sgbuf_free()
394 sg_dma_address(&sg->sg)); in pl011_sgbuf_free()
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
402 struct device *dev = uap->port.dev; in pl011_dma_probe()
404 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
408 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
414 uap->dma_probed = true; in pl011_dma_probe()
417 if (PTR_ERR(chan) == -EPROBE_DEFER) { in pl011_dma_probe()
418 uap->dma_probed = false; in pl011_dma_probe()
423 if (!plat || !plat->dma_filter) { in pl011_dma_probe()
424 dev_info(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
432 chan = dma_request_channel(mask, plat->dma_filter, in pl011_dma_probe()
433 plat->dma_tx_param); in pl011_dma_probe()
435 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
441 uap->dmatx.chan = chan; in pl011_dma_probe()
443 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
444 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
449 if (!chan && plat && plat->dma_rx_param) { in pl011_dma_probe()
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); in pl011_dma_probe()
453 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
460 .src_addr = uap->port.mapbase + in pl011_dma_probe()
464 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
478 dev_info(uap->port.dev, in pl011_dma_probe()
479 "RX DMA disabled - no residue processing\n"); in pl011_dma_probe()
484 uap->dmarx.chan = chan; in pl011_dma_probe()
486 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
487 if (plat && plat->dma_rx_poll_enable) { in pl011_dma_probe()
489 if (plat->dma_rx_poll_rate) { in pl011_dma_probe()
490 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
498 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
499 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
502 if (plat->dma_rx_poll_timeout) in pl011_dma_probe()
503 uap->dmarx.poll_timeout = in pl011_dma_probe()
504 plat->dma_rx_poll_timeout; in pl011_dma_probe()
506 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
507 } else if (!plat && dev->of_node) { in pl011_dma_probe()
508 uap->dmarx.auto_poll_rate = of_property_read_bool( in pl011_dma_probe()
509 dev->of_node, "auto-poll"); in pl011_dma_probe()
510 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
513 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
514 "poll-rate-ms", &x)) in pl011_dma_probe()
515 uap->dmarx.poll_rate = x; in pl011_dma_probe()
517 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
518 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
519 "poll-timeout-ms", &x)) in pl011_dma_probe()
520 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
522 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
525 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
526 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
532 if (uap->dmatx.chan) in pl011_dma_remove()
533 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
534 if (uap->dmarx.chan) in pl011_dma_remove()
535 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
549 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
553 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_tx_callback()
554 if (uap->dmatx.queued) in pl011_dma_tx_callback()
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, in pl011_dma_tx_callback()
558 dmacr = uap->dmacr; in pl011_dma_tx_callback()
559 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
560 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
564 * some reason (eg, XOFF received, or we want to send an X-char.) in pl011_dma_tx_callback()
567 * and the rest of the driver - if the driver disables TX DMA while in pl011_dma_tx_callback()
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
572 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
573 uap->dmatx.queued = false; in pl011_dma_tx_callback()
574 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
581 * have data pending to be sent. Re-enable the TX IRQ. in pl011_dma_tx_callback()
585 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
598 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
599 struct dma_chan *chan = dmatx->chan; in pl011_dma_tx_refill()
600 struct dma_device *dma_dev = chan->device; in pl011_dma_tx_refill()
602 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
612 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
613 uap->dmatx.queued = false; in pl011_dma_tx_refill()
621 count -= 1; in pl011_dma_tx_refill()
627 if (xmit->tail < xmit->head) in pl011_dma_tx_refill()
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); in pl011_dma_tx_refill()
630 size_t first = UART_XMIT_SIZE - xmit->tail; in pl011_dma_tx_refill()
635 second = count - first; in pl011_dma_tx_refill()
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); in pl011_dma_tx_refill()
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second); in pl011_dma_tx_refill()
642 dmatx->sg.length = count; in pl011_dma_tx_refill()
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { in pl011_dma_tx_refill()
645 uap->dmatx.queued = false; in pl011_dma_tx_refill()
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
647 return -EBUSY; in pl011_dma_tx_refill()
650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, in pl011_dma_tx_refill()
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); in pl011_dma_tx_refill()
654 uap->dmatx.queued = false; in pl011_dma_tx_refill()
659 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
660 return -EBUSY; in pl011_dma_tx_refill()
664 desc->callback = pl011_dma_tx_callback; in pl011_dma_tx_refill()
665 desc->callback_param = uap; in pl011_dma_tx_refill()
671 dma_dev->device_issue_pending(chan); in pl011_dma_tx_refill()
673 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
674 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
675 uap->dmatx.queued = true; in pl011_dma_tx_refill()
681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in pl011_dma_tx_refill()
682 uap->port.icount.tx += count; in pl011_dma_tx_refill()
685 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
691 * We received a transmit interrupt without a pending X-char but with
700 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
705 * TX interrupt, it will be because we've just sent an X-char. in pl011_dma_tx_irq()
708 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
709 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
710 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
711 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
712 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
721 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
722 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
734 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
735 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
736 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
752 if (!uap->using_tx_dma) in pl011_dma_tx_start()
755 if (!uap->port.x_char) { in pl011_dma_tx_start()
756 /* no X-char, try to push chars out in DMA mode */ in pl011_dma_tx_start()
759 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
761 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
762 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
765 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
766 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
767 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
773 * We have an X-char to send. Disable DMA to prevent it loading in pl011_dma_tx_start()
776 dmacr = uap->dmacr; in pl011_dma_tx_start()
777 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
778 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
784 * loaded the character, we should just re-enable DMA. in pl011_dma_tx_start()
789 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
790 uap->port.icount.tx++; in pl011_dma_tx_start()
791 uap->port.x_char = 0; in pl011_dma_tx_start()
793 /* Success - restore the DMA state */ in pl011_dma_tx_start()
794 uap->dmacr = dmacr; in pl011_dma_tx_start()
805 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
806 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
811 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
814 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
816 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
817 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, in pl011_dma_flush_buffer()
819 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
820 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
821 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
829 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
830 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
835 return -EIO; in pl011_dma_rx_trigger_dma()
838 sgbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
839 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_trigger_dma()
840 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, in pl011_dma_rx_trigger_dma()
849 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
851 return -EBUSY; in pl011_dma_rx_trigger_dma()
855 desc->callback = pl011_dma_rx_callback; in pl011_dma_rx_trigger_dma()
856 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
857 dmarx->cookie = dmaengine_submit(desc); in pl011_dma_rx_trigger_dma()
860 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
861 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
862 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
864 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
865 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
873 * with the port spinlock uap->port.lock held.
879 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
881 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_chars()
885 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
888 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
890 dmataken = sgbuf->sg.length - dmarx->last_residue; in pl011_dma_rx_chars()
893 pending -= dmataken; in pl011_dma_rx_chars()
904 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_chars()
907 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
909 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
914 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
915 dmarx->last_residue = sgbuf->sg.length; in pl011_dma_rx_chars()
940 spin_unlock(&uap->port.lock); in pl011_dma_rx_chars()
941 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
945 spin_lock(&uap->port.lock); in pl011_dma_rx_chars()
950 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
951 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_irq()
952 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? in pl011_dma_rx_irq()
953 &dmarx->sgbuf_b : &dmarx->sgbuf_a; in pl011_dma_rx_irq()
964 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
965 dmastat = rxchan->device->device_tx_status(rxchan, in pl011_dma_rx_irq()
966 dmarx->cookie, &state); in pl011_dma_rx_irq()
968 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
970 /* Disable RX DMA - incoming data will wait in the FIFO */ in pl011_dma_rx_irq()
971 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
972 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
973 uap->dmarx.running = false; in pl011_dma_rx_irq()
975 pending = sgbuf->sg.length - state.residue; in pl011_dma_rx_irq()
977 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_irq()
984 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
986 /* Switch buffer & re-trigger DMA job */ in pl011_dma_rx_irq()
987 dmarx->use_buf_b = !dmarx->use_buf_b; in pl011_dma_rx_irq()
989 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_irq()
991 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
992 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
999 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
1000 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_callback()
1001 bool lastbuf = dmarx->use_buf_b; in pl011_dma_rx_callback()
1002 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? in pl011_dma_rx_callback()
1003 &dmarx->sgbuf_b : &dmarx->sgbuf_a; in pl011_dma_rx_callback()
1015 spin_lock_irq(&uap->port.lock); in pl011_dma_rx_callback()
1020 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_callback()
1021 pending = sgbuf->sg.length - state.residue; in pl011_dma_rx_callback()
1023 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_callback()
1026 uap->dmarx.running = false; in pl011_dma_rx_callback()
1027 dmarx->use_buf_b = !lastbuf; in pl011_dma_rx_callback()
1031 spin_unlock_irq(&uap->port.lock); in pl011_dma_rx_callback()
1037 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_callback()
1039 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1040 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1051 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1055 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1056 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1067 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1068 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1069 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1077 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; in pl011_dma_rx_poll()
1078 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_poll()
1079 if (likely(state.residue < dmarx->last_residue)) { in pl011_dma_rx_poll()
1080 dmataken = sgbuf->sg.length - dmarx->last_residue; in pl011_dma_rx_poll()
1081 size = dmarx->last_residue - state.residue; in pl011_dma_rx_poll()
1082 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_poll()
1085 dmarx->last_residue = state.residue; in pl011_dma_rx_poll()
1086 dmarx->last_jiffies = jiffies; in pl011_dma_rx_poll()
1094 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) in pl011_dma_rx_poll()
1095 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1097 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_rx_poll()
1099 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1100 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1101 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_rx_poll()
1103 uap->dmarx.running = false; in pl011_dma_rx_poll()
1105 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1107 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1108 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1116 if (!uap->dma_probed) in pl011_dma_startup()
1119 if (!uap->dmatx.chan) in pl011_dma_startup()
1122 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1123 if (!uap->dmatx.buf) { in pl011_dma_startup()
1124 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); in pl011_dma_startup()
1125 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1129 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); in pl011_dma_startup()
1132 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1133 uap->using_tx_dma = true; in pl011_dma_startup()
1135 if (!uap->dmarx.chan) in pl011_dma_startup()
1139 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, in pl011_dma_startup()
1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1147 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, in pl011_dma_startup()
1150 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1152 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, in pl011_dma_startup()
1157 uap->using_rx_dma = true; in pl011_dma_startup()
1161 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1162 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1165 * ST Micro variants has some specific dma burst threshold in pl011_dma_startup()
1169 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1173 if (uap->using_rx_dma) { in pl011_dma_startup()
1175 dev_dbg(uap->port.dev, "could not trigger initial " in pl011_dma_startup()
1177 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1178 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1179 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1181 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1182 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1183 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1190 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1194 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1197 spin_lock_irq(&uap->port.lock); in pl011_dma_shutdown()
1198 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1199 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1200 spin_unlock_irq(&uap->port.lock); in pl011_dma_shutdown()
1202 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1204 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1205 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1206 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, in pl011_dma_shutdown()
1208 uap->dmatx.queued = false; in pl011_dma_shutdown()
1211 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1212 uap->using_tx_dma = false; in pl011_dma_shutdown()
1215 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1216 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1218 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1220 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1221 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1222 uap->using_rx_dma = false; in pl011_dma_shutdown()
1228 return uap->using_rx_dma; in pl011_dma_rx_available()
1233 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1274 return -EIO; in pl011_dma_rx_trigger_dma()
1295 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1296 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1306 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1307 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1325 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| in pl011_stop_rx()
1327 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1336 spin_lock_irqsave(&port->lock, flags); in pl011_throttle_rx()
1338 spin_unlock_irqrestore(&port->lock, flags); in pl011_throttle_rx()
1346 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; in pl011_enable_ms()
1347 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1351 __releases(&uap->port.lock) in pl011_rx_chars()
1352 __acquires(&uap->port.lock) in pl011_rx_chars()
1356 spin_unlock(&uap->port.lock); in pl011_rx_chars()
1357 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1364 dev_dbg(uap->port.dev, "could not trigger RX DMA job " in pl011_rx_chars()
1366 uap->im |= UART011_RXIM; in pl011_rx_chars()
1367 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1371 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1372 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1373 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1374 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1376 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1381 spin_lock(&uap->port.lock); in pl011_rx_chars()
1392 uap->port.icount.tx++; in pl011_tx_char()
1400 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1401 int count = uap->fifosize >> 1; in pl011_tx_chars()
1403 if (uap->port.x_char) { in pl011_tx_chars()
1404 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1406 uap->port.x_char = 0; in pl011_tx_chars()
1407 --count; in pl011_tx_chars()
1409 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1410 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1419 if (likely(from_irq) && count-- == 0) in pl011_tx_chars()
1422 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) in pl011_tx_chars()
1425 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in pl011_tx_chars()
1429 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1432 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1444 delta = status ^ uap->old_status; in pl011_modem_status()
1445 uap->old_status = status; in pl011_modem_status()
1451 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1453 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1454 uap->port.icount.dsr++; in pl011_modem_status()
1456 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1457 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1458 status & uap->vendor->fr_cts); in pl011_modem_status()
1460 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1465 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1487 spin_lock_irqsave(&uap->port.lock, flags); in pl011_int()
1488 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1509 if (pass_counter-- == 0) in pl011_int()
1512 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1517 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_int()
1528 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1530 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1546 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); in pl011_get_mctrl()
1547 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); in pl011_get_mctrl()
1548 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); in pl011_get_mctrl()
1573 if (port->status & UPSTAT_AUTORTS) { in pl011_set_mctrl()
1574 /* We need to disable auto-RTS if we want to turn RTS off */ in pl011_set_mctrl()
1589 spin_lock_irqsave(&uap->port.lock, flags); in pl011_break_ctl()
1591 if (break_state == -1) in pl011_break_ctl()
1596 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_break_ctl()
1664 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1669 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1673 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1684 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1687 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1690 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1691 if (plat->init) in pl011_hwinit()
1692 plat->init(); in pl011_hwinit()
1720 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1722 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1735 spin_lock_irqsave(&uap->port.lock, flags); in pl011_enable_interrupts()
1746 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1753 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1755 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1756 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1757 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_enable_interrupts()
1765 spin_lock_irqsave(&uap->port.lock, flags); in pl011_unthrottle_rx()
1767 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1769 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1771 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1773 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_unthrottle_rx()
1791 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1793 spin_lock_irq(&uap->port.lock); in pl011_startup()
1796 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); in pl011_startup()
1800 spin_unlock_irq(&uap->port.lock); in pl011_startup()
1805 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1815 clk_disable_unprepare(uap->clk); in pl011_startup()
1834 uap->old_status = 0; in sbsa_uart_startup()
1860 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1861 spin_lock_irq(&uap->port.lock); in pl011_disable_uart()
1863 uap->old_cr = cr; in pl011_disable_uart()
1867 spin_unlock_irq(&uap->port.lock); in pl011_disable_uart()
1879 spin_lock_irq(&uap->port.lock); in pl011_disable_interrupts()
1882 uap->im = 0; in pl011_disable_interrupts()
1883 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
1886 spin_unlock_irq(&uap->port.lock); in pl011_disable_interrupts()
1898 free_irq(uap->port.irq, uap); in pl011_shutdown()
1905 clk_disable_unprepare(uap->clk); in pl011_shutdown()
1907 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1909 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1912 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1913 if (plat->exit) in pl011_shutdown()
1914 plat->exit(); in pl011_shutdown()
1917 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1918 uap->port.ops->flush_buffer(port); in pl011_shutdown()
1928 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
1930 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
1931 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
1937 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
1938 if (termios->c_iflag & INPCK) in pl011_setup_status_masks()
1939 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
1940 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in pl011_setup_status_masks()
1941 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
1946 port->ignore_status_mask = 0; in pl011_setup_status_masks()
1947 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
1948 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
1949 if (termios->c_iflag & IGNBRK) { in pl011_setup_status_masks()
1950 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
1955 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
1956 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
1962 if ((termios->c_cflag & CREAD) == 0) in pl011_setup_status_masks()
1963 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
1976 if (uap->vendor->oversampling) in pl011_set_termios()
1985 port->uartclk / clkdiv); in pl011_set_termios()
1990 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
1991 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
1994 if (baud > port->uartclk/16) in pl011_set_termios()
1995 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
1997 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
1999 switch (termios->c_cflag & CSIZE) { in pl011_set_termios()
2013 if (termios->c_cflag & CSTOPB) in pl011_set_termios()
2015 if (termios->c_cflag & PARENB) { in pl011_set_termios()
2017 if (!(termios->c_cflag & PARODD)) in pl011_set_termios()
2019 if (termios->c_cflag & CMSPAR) in pl011_set_termios()
2022 if (uap->fifosize > 1) in pl011_set_termios()
2025 spin_lock_irqsave(&port->lock, flags); in pl011_set_termios()
2028 * Update the per-port timeout. in pl011_set_termios()
2030 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
2034 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
2041 if (termios->c_cflag & CRTSCTS) { in pl011_set_termios()
2046 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in pl011_set_termios()
2049 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_set_termios()
2052 if (uap->vendor->oversampling) { in pl011_set_termios()
2053 if (baud > port->uartclk / 16) in pl011_set_termios()
2060 * Workaround for the ST Micro oversampling variants to in pl011_set_termios()
2065 if (uap->vendor->oversampling) { in pl011_set_termios()
2067 quot -= 1; in pl011_set_termios()
2069 quot -= 2; in pl011_set_termios()
2076 * ----------v----------v----------v----------v----- in pl011_set_termios()
2079 * ----------^----------^----------^----------^----- in pl011_set_termios()
2084 spin_unlock_irqrestore(&port->lock, flags); in pl011_set_termios()
2095 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2098 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in sbsa_uart_set_termios()
2099 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in sbsa_uart_set_termios()
2100 termios->c_cflag |= CS8 | CLOCAL; in sbsa_uart_set_termios()
2102 spin_lock_irqsave(&port->lock, flags); in sbsa_uart_set_termios()
2103 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2105 spin_unlock_irqrestore(&port->lock, flags); in sbsa_uart_set_termios()
2112 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2121 port->type = PORT_AMBA; in pl011_config_port()
2130 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) in pl011_verify_port()
2131 ret = -EINVAL; in pl011_verify_port()
2132 if (ser->irq < 0 || ser->irq >= nr_irqs) in pl011_verify_port()
2133 ret = -EINVAL; in pl011_verify_port()
2134 if (ser->baud_base < 9600) in pl011_verify_port()
2135 ret = -EINVAL; in pl011_verify_port()
2136 if (port->mapbase != (unsigned long) ser->iomem_base) in pl011_verify_port()
2137 ret = -EINVAL; in pl011_verify_port()
2212 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write()
2217 clk_enable(uap->clk); in pl011_console_write()
2220 if (uap->port.sysrq) in pl011_console_write()
2223 locked = spin_trylock(&uap->port.lock); in pl011_console_write()
2225 spin_lock(&uap->port.lock); in pl011_console_write()
2230 if (!uap->vendor->always_enabled) { in pl011_console_write()
2237 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2244 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2245 & uap->vendor->fr_busy) in pl011_console_write()
2247 if (!uap->vendor->always_enabled) in pl011_console_write()
2251 spin_unlock(&uap->port.lock); in pl011_console_write()
2254 clk_disable(uap->clk); in pl011_console_write()
2281 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2283 if (uap->vendor->oversampling) { in pl011_console_get_options()
2305 if (co->index >= UART_NR) in pl011_console_setup()
2306 co->index = 0; in pl011_console_setup()
2307 uap = amba_ports[co->index]; in pl011_console_setup()
2309 return -ENODEV; in pl011_console_setup()
2312 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2314 ret = clk_prepare(uap->clk); in pl011_console_setup()
2318 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2321 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2322 if (plat->init) in pl011_console_setup()
2323 plat->init(); in pl011_console_setup()
2326 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2328 if (uap->vendor->fixed_options) { in pl011_console_setup()
2329 baud = uap->fixed_baud; in pl011_console_setup()
2338 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2342 * pl011_console_match - non-standard console matching
2357 * Returns 0 if console matches; otherwise non-zero to use default matching
2373 return -ENODEV; in pl011_console_match()
2376 return -ENODEV; in pl011_console_match()
2379 return -ENODEV; in pl011_console_match()
2388 port = &amba_ports[i]->port; in pl011_console_match()
2390 if (port->mapbase != addr) in pl011_console_match()
2393 co->index = i; in pl011_console_match()
2394 port->cons = co; in pl011_console_match()
2398 return -ENODEV; in pl011_console_match()
2409 .index = -1,
2417 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in qdf2400_e44_putc()
2419 writel(c, port->membase + UART01x_DR); in qdf2400_e44_putc()
2420 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) in qdf2400_e44_putc()
2426 struct earlycon_device *dev = con->data; in qdf2400_e44_early_write()
2428 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); in qdf2400_e44_early_write()
2433 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2435 if (port->iotype == UPIO_MEM32) in pl011_putc()
2436 writel(c, port->membase + UART01x_DR); in pl011_putc()
2438 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2439 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2445 struct earlycon_device *dev = con->data; in pl011_early_write()
2447 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2453 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) in pl011_getc()
2456 if (port->iotype == UPIO_MEM32) in pl011_getc()
2457 return readl(port->membase + UART01x_DR); in pl011_getc()
2459 return readb(port->membase + UART01x_DR); in pl011_getc()
2464 struct earlycon_device *dev = con->data; in pl011_early_read()
2468 ch = pl011_getc(&dev->port); in pl011_early_read()
2482 * On non-ACPI systems, earlycon is enabled by specifying
2496 if (!device->port.membase) in pl011_early_console_setup()
2497 return -ENODEV; in pl011_early_console_setup()
2499 device->con->write = pl011_early_write; in pl011_early_console_setup()
2500 device->con->read = pl011_early_read; in pl011_early_console_setup()
2505 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2514 * case, the SPCR code will detect the need for the E44 work-around,
2521 if (!device->port.membase) in qdf2400_e44_early_console_setup()
2522 return -ENODEV; in qdf2400_e44_early_console_setup()
2524 device->con->write = qdf2400_e44_early_write; in qdf2400_e44_early_console_setup()
2553 np = dev->of_node; in pl011_probe_dt_alias()
2570 …dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeratio… in pl011_probe_dt_alias()
2600 return -EBUSY; in pl011_find_free_port()
2614 uap->old_cr = 0; in pl011_setup_port()
2615 uap->port.dev = dev; in pl011_setup_port()
2616 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2617 uap->port.membase = base; in pl011_setup_port()
2618 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2619 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2620 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2621 uap->port.line = index; in pl011_setup_port()
2639 dev_err(uap->port.dev, in pl011_register_port()
2640 "Failed to register AMBA-PL011 driver\n"); in pl011_register_port()
2648 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2658 struct vendor_data *vendor = id->data; in pl011_probe()
2665 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2668 return -ENOMEM; in pl011_probe()
2670 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2671 if (IS_ERR(uap->clk)) in pl011_probe()
2672 return PTR_ERR(uap->clk); in pl011_probe()
2674 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2675 uap->vendor = vendor; in pl011_probe()
2676 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2677 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2678 uap->port.irq = dev->irq[0]; in pl011_probe()
2679 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2681 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2683 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2696 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2706 return -EINVAL; in pl011_suspend()
2708 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2716 return -EINVAL; in pl011_resume()
2718 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2735 if (pdev->dev.of_node) { in sbsa_uart_probe()
2736 struct device_node *np = pdev->dev.of_node; in sbsa_uart_probe()
2738 ret = of_property_read_u32(np, "current-speed", &baudrate); in sbsa_uart_probe()
2749 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2752 return -ENOMEM; in sbsa_uart_probe()
2757 uap->port.irq = ret; in sbsa_uart_probe()
2761 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); in sbsa_uart_probe()
2762 uap->vendor = &vendor_qdt_qdf2400_e44; in sbsa_uart_probe()
2765 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2767 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2768 uap->fifosize = 32; in sbsa_uart_probe()
2769 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2770 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2771 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2773 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2777 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2790 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2796 { .compatible = "arm,sbsa-uart", },
2812 .name = "sbsa-uart",
2843 .name = "uart-pl011",