35 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)  in hda_dsp_ctrl_link_reset()  argument
45 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,  in hda_dsp_ctrl_link_reset()
51 		gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);  in hda_dsp_ctrl_link_reset()
58 	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",  in hda_dsp_ctrl_link_reset()
63 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)  in hda_dsp_ctrl_get_caps()  argument
65 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_get_caps()
74 	ret = hda_dsp_ctrl_link_reset(sdev, true);  in hda_dsp_ctrl_get_caps()
77 	ret = hda_dsp_ctrl_link_reset(sdev, false);  in hda_dsp_ctrl_get_caps()
81 	offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);  in hda_dsp_ctrl_get_caps()
84 		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",  in hda_dsp_ctrl_get_caps()
87 		cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);  in hda_dsp_ctrl_get_caps()
98 			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
101 			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;  in hda_dsp_ctrl_get_caps()
104 			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
107 			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;  in hda_dsp_ctrl_get_caps()
110 			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
113 			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;  in hda_dsp_ctrl_get_caps()
116 			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
121 			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
126 			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",  in hda_dsp_ctrl_get_caps()
137 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_ppcap_enable()  argument
141 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,  in hda_dsp_ctrl_ppcap_enable()
145 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_ppcap_int_enable()  argument
149 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,  in hda_dsp_ctrl_ppcap_int_enable()
153 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_misc_clock_gating()  argument
157 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);  in hda_dsp_ctrl_misc_clock_gating()
165 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_clock_power_gating()  argument
171 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);  in hda_dsp_ctrl_clock_power_gating()
175 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,  in hda_dsp_ctrl_clock_power_gating()
180 	snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);  in hda_dsp_ctrl_clock_power_gating()
185 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)  in hda_dsp_ctrl_init_chip()  argument
187 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_init_chip()
200 	hda_dsp_ctrl_misc_clock_gating(sdev, false);  in hda_dsp_ctrl_init_chip()
204 		ret = hda_dsp_ctrl_link_reset(sdev, true);  in hda_dsp_ctrl_init_chip()
206 			dev_err(sdev->dev, "error: failed to reset HDA controller\n");  in hda_dsp_ctrl_init_chip()
213 		ret = hda_dsp_ctrl_link_reset(sdev, false);  in hda_dsp_ctrl_init_chip()
215 			dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");  in hda_dsp_ctrl_init_chip()
249 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_init_chip()
255 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,  in hda_dsp_ctrl_init_chip()
264 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,  in hda_dsp_ctrl_init_chip()
273 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_init_chip()
279 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,  in hda_dsp_ctrl_init_chip()
281 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,  in hda_dsp_ctrl_init_chip()
294 	hda_dsp_ctrl_misc_clock_gating(sdev, true);  in hda_dsp_ctrl_init_chip()
302 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)  in hda_dsp_ctrl_stop_chip()  argument
304 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_stop_chip()
314 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
322 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_stop_chip()
326 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_stop_chip()
333 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
339 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,  in hda_dsp_ctrl_stop_chip()
348 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,  in hda_dsp_ctrl_stop_chip()
357 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
359 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()