591          dispatch_width, stage_abbrev, msg);  in vfail()
624    if (dispatch_width > n) {  in limit_dispatch_width()
1118    int reg_width = dispatch_width / 8;  in vgrf()
1363       for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {  in emit_sampleid_setup()
1364          const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);  in emit_sampleid_setup()
3421    if (dispatch_width >= 16)  in remove_duplicate_mrf_writes()
3938          fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);  in lower_mul_dword_inst()
4383       assert(bld.dispatch_width() <= 16);  in brw_sample_mask_reg()
4386       assert(v->devinfo->ver >= 6 && bld.dispatch_width() <= 16);  in brw_sample_mask_reg()
4432           bld.dispatch_width() == inst->exec_size);  in brw_emit_predicate_on_sample_mask()
4475    unsigned width = bld.dispatch_width();  in emit_is_helper_invocation()
5127    return !(is_periodic(inst->src[i], lbld.dispatch_width()) ||  in needs_src_copy()
5129              lbld.dispatch_width() <= inst->exec_size)) ||  in needs_src_copy()
5152       const fs_builder cbld = lbld.group(MIN2(lbld.dispatch_width(),  in emit_unzip()
5161    } else if (is_periodic(inst->src[i], lbld.dispatch_width())) {  in emit_unzip()
5195    if (lbld.dispatch_width() > inst->exec_size)  in needs_dst_copy()
5232    assert(lbld_before.dispatch_width() == lbld_after.dispatch_width());  in emit_zip()
5250             lbld_before.group(MIN2(lbld_before.dispatch_width(),  in emit_zip()
5259          lbld_after.group(MIN2(lbld_after.dispatch_width(),  in emit_zip()
5863    if (inst->exec_size != dispatch_width)  in dump_instruction()
5874    const unsigned payload_width = MIN2(16, dispatch_width);  in setup_fs_payload_gfx6()
5875    assert(dispatch_width % payload_width == 0);  in setup_fs_payload_gfx6()
5881    for (unsigned j = 0; j < dispatch_width / payload_width; j++) {  in setup_fs_payload_gfx6()
5886    for (unsigned j = 0; j < dispatch_width / payload_width; j++) {  in setup_fs_payload_gfx6()
6054                   stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \  in optimize()
6068                stage_abbrev, dispatch_width, nir->info.name);  in optimize()
6259          inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),  in fixup_3src_null_dest()
6375    const brw_predicate pred = dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H :  in fixup_nomask_control_flow()
6376                               dispatch_width > 8 ? BRW_PREDICATE_ALIGN1_ANY16H :  in fixup_nomask_control_flow()
6442                                        .exec_all().group(dispatch_width, 0);  in fixup_nomask_control_flow()
6450                                       flag_mask(flag, dispatch_width / 8);  in fixup_nomask_control_flow()
6889       assert(dispatch_width == 16);  in run_fs()
6905          const unsigned lower_width = MIN2(dispatch_width, 16);  in run_fs()
6906          for (unsigned i = 0; i < dispatch_width / lower_width; i++) {  in run_fs()
7035    payload.num_regs = dispatch_width == 32 ? 4 : 3;  in run_task()
7082    payload.num_regs = dispatch_width == 32 ? 4 : 3;  in run_mesh()
7760 brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width)  in brw_nir_lower_simd()  argument
7763                                  (void *)(uintptr_t)dispatch_width);  in brw_nir_lower_simd()
7800       const unsigned dispatch_width = 8u << simd;  in brw_compile_cs()  local
7804                         dispatch_width, true /* is_scalar */);  in brw_compile_cs()
7806       NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width);  in brw_compile_cs()
7816                                &prog_data->base, shader, dispatch_width,  in brw_compile_cs()
7839                                 dispatch_width, v[simd]->fail_msg);  in brw_compile_cs()