Searched defs:CONTROL (Results 1 – 18 of 18) sorted by relevance
14 __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ member
14 __RW uint32_t CONTROL; /* 0x0: Tamper n control */ member
30 #define CONTROL 4 macro
185 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
178 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ argument
69 uint32_t CONTROL; member
33 __IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register member
172 uint32_t CONTROL; member193 uint8_t CONTROL; member
818 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
382 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) |… argument
44 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member60 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
50 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member64 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
653 __IO uint32_t CONTROL; member694 __IO uint32_t CONTROL; member
823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register member
900 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register member
928 __IO uint32_t CONTROL; /* Address Offset: 0x0000 */ member