| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/ |
| D | reg_patch.h | 24 __IO uint32_t CTRL[PATCH_ENTRY_NUM]; member
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| /device/soc/goodix/gr551x/sdk_liteos/gr551x_sdk/components/sdk/ |
| D | gr55xx_fpb.h | 71 volatile uint32_t CTRL; /**< Offset: 0x000 (R/W) Data */ member
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| /device/soc/winnermicro/wm800/board/include/driver/ |
| D | wm_i2c.h | 40 __IO uint32_t CTRL; member
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| D | wm_lcd.h | 42 __IO uint32_t CTRL; member
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| D | wm_i2s.h | 31 __IO uint32_t CTRL; member
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| /device/board/openvalley/niobeu4/liteos_m/arch/ |
| D | los_arch_timer.h | 58 UINT32 CTRL; member
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/ |
| D | ttydefaults.h | 9 #define CTRL(x) ((x)&037) macro
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| /device/soc/hpmicro/sdk/hpm_sdk/soc/ip/ |
| D | hpm_wdg_regs.h | 14 __RW uint32_t CTRL; /* 0x10: Control Register */ member
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| D | hpm_dao_regs.h | 13 __RW uint32_t CTRL; /* 0x0: Control Register */ member
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| D | hpm_rng_regs.h | 14 __RW uint32_t CTRL; /* 0x4: Control Register */ member
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| D | hpm_pdma_regs.h | 13 __RW uint32_t CTRL; /* 0x0: Control Register */ member
26 __RW uint32_t CTRL; /* 0x30: Layer Control Register */ member
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| D | hpm_dma_regs.h | 23 __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ member
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| D | hpm_vad_regs.h | 13 __RW uint32_t CTRL; /* 0x0: Control Register */ member
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| D | hpm_i2c_regs.h | 19 __RW uint32_t CTRL; /* 0x24: Control Register */ member
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| D | hpm_pdm_regs.h | 13 __RW uint32_t CTRL; /* 0x0: Control Register */ member
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/ |
| D | reg_dma.h | 43 __IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register member
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/inc/ |
| D | core_cm0plus.h | 474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_sc000.h | 490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_armv8mbl.h | 562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_cm23.h | 562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1010 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
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| D | core_sc300.h | 693 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm3.h | 708 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1158 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| D | core_cm0.h | 450 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
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| D | core_cm4.h | 770 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
910 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1220 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
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| /device/soc/st/stm32f407zg/uniproton/board/common/STM32F4xx_StdPeriph_Driver/inc/ |
| D | stm32f4xx_dma.h | 536 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ argument
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