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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6ull-colibri.dtsi17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
42 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
47 states = <1800000 0x1 3300000 0x0>;
59 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
78 pinctrl-0 = <&pinctrl_enet2>;
86 #size-cells = <0>;
98 pinctrl-0 = <&pinctrl_gpmi_nand>;
108 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
Dimx6ul-ccimx6ulsbcexpress.dts23 pinctrl-0 = <&pinctrl_adc1>;
29 pinctrl-0 = <&pinctrl_flexcan1>;
37 pinctrl-0 = <&pinctrl_ecspi3_master>;
43 pinctrl-0 = <&pinctrl_enet1>;
50 #size-cells = <0>;
52 ethphy0: ethernet-phy@0 {
55 reg = <0>;
62 pinctrl-0 = <&pinctrl_i2c2>;
68 pinctrl-0 = <&pinctrl_pwm1>;
74 pinctrl-0 = <&pinctrl_uart4>;
[all …]
Dimx6ul-pico-pi.dts18 pinctrl-0 = <&pinctrl_gpio_leds>;
40 #clock-cells = <0>;
48 pinctrl-0 = <&pinctrl_i2c2>;
52 reg = <0x0a>;
63 pinctrl-0 = <&pinctrl_i2c3>;
68 reg = <0x38>;
79 pinctrl-0 = <&pinctrl_hog>;
83 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0
84 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0
85 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0
[all …]
Dimx6ul-pico-hobbit.dts18 pinctrl-0 = <&pinctrl_gpio_leds>;
40 #clock-cells = <0>;
48 pinctrl-0 = <&pinctrl_i2c2>;
52 reg = <0x0a>;
65 reg = <0x38>;
75 reg = <0x50>;
82 pinctrl-0 = <&pinctrl_hog>;
86 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0
87 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0
88 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0
[all …]
Dimx6sx-softing-vining-2000.dts22 reg = <0x80000000 0x40000000>;
29 pinctrl-0 = <&pinctrl_usb_otg1>;
49 pwms = <&pwm6 0 50000>;
55 pwms = <&pwm2 0 50000>;
61 pwms = <&pwm1 0 50000>;
95 pinctrl-0 = <&pinctrl_ecspi4>;
102 pinctrl-0 = <&pinctrl_enet1>;
112 #size-cells = <0>;
114 ethphy0: ethernet0-phy@0 {
115 reg = <0>;
[all …]
Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]
Dimx6ul-phytec-segin.dtsi35 pinctrl-0 = <&princtrl_flexcan1_en>;
84 pinctrl-0 = <&pinctrl_adc1>;
96 pinctrl-0 = <&pinctrl_flexcan1>;
108 pinctrl-0 = <&pinctrl_ecspi3>;
115 pinctrl-0 = <&pinctrl_enet2>;
124 #sound-dai-cells = <0>;
125 reg = <0x18>;
135 reg = <0x44>;
139 pinctrl-0 = <&pinctrl_stmpe>;
146 st,ref-sel = <0>;
[all …]
Dimx6sx-udoo-neo.dtsi20 gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
45 pinctrl-0 = <&pinctrl_otg1_reg>;
56 pinctrl-0 = <&pinctrl_otg2_reg>;
77 pinctrl-0 = <&pinctrl_enet1>;
85 pinctrl-0 = <&pinctrl_i2c1>;
91 reg = <0x08>;
181 pinctrl-0 = <&pinctrl_i2c2>;
188 pinctrl-0 = <&pinctrl_i2c4>;
196 <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>;
201 <MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0xa0b1>,
[all …]
Dimx6sx-sdb.dtsi21 reg = <0x80000000 0x40000000>;
26 pwms = <&pwm3 0 5000000>;
27 brightness-levels = <0 4 8 16 32 64 128 255>;
34 pinctrl-0 = <&pinctrl_gpio_keys>;
54 pinctrl-0 = <&pinctrl_vcc_sd3>;
65 pinctrl-0 = <&pinctrl_usb_otg1>;
76 pinctrl-0 = <&pinctrl_usb_otg2>;
94 gpio = <&gpio3 27 0>;
101 pinctrl-0 = <&pinctrl_peri_3v3>;
113 pinctrl-0 = <&pinctrl_enet_3v3>;
[all …]
Dimx6ul-pico.dtsi16 reg = <0x80000000 0>;
25 pwms = <&pwm3 0 5000000>;
26 brightness-levels = <0 4 8 16 32 64 128 255>;
57 pinctrl-0 = <&pinctrl_usb_otg1>;
61 gpio = <&gpio1 6 0>;
69 pinctrl-0 = <&pinctrl_brcm_reg>;
90 pinctrl-0 = <&pinctrl_flexcan1>;
96 pinctrl-0 = <&pinctrl_flexcan2>;
107 pinctrl-0 = <&pinctrl_enet2>;
116 #size-cells = <0>;
[all …]
Dimx6qdl-rex.dtsi19 #size-cells = <0>;
21 reg_3p3v: regulator@0 {
23 reg = <0>;
56 pinctrl-0 = <&pinctrl_led>;
83 pinctrl-0 = <&pinctrl_audmux>;
90 pinctrl-0 = <&pinctrl_ecspi2>;
97 pinctrl-0 = <&pinctrl_ecspi3>;
103 pinctrl-0 = <&pinctrl_enet>;
117 pinctrl-0 = <&pinctrl_i2c1>;
122 reg = <0x0a>;
[all …]
Dimx23-pinfunc.h19 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
20 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
21 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
22 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
23 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
24 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
25 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
26 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
27 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
28 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
Dimx28-pinfunc.h19 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
20 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
21 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
22 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
23 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
24 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
25 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
26 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
27 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
28 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
Dimx6sx-sabreauto.dts15 reg = <0x80000000 0x80000000>;
21 pinctrl-0 = <&pinctrl_led>;
33 pinctrl-0 = <&pinctrl_vcc_sd3>;
118 assigned-clock-rates = <0>, <0>, <24576000>;
123 pinctrl-0 = <&pinctrl_esai>;
127 assigned-clock-rates = <0>, <24576000>;
133 pinctrl-0 = <&pinctrl_enet1>;
141 #size-cells = <0>;
143 ethphy0: ethernet-phy@0 {
145 reg = <0>;
[all …]
Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
Dkeystone-k2g-evm.dts17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
66 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
67 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
73 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
74 K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
75 K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
76 K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
77 K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
78 K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/kernel/linux/linux-5.10/sound/pci/oxygen/
Doxygen.c11 * SPI 0 -> 1st AK4396 (front)
17 * GPIO 0 -> DFS0 of AK5385
25 * GPIO 6 -> S/PDIF from optical (0) or coaxial (1) input
36 * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
90 { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
91 { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF },
92 { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
93 { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
94 { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
95 { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dqcom,sdm845-venus-v2.yaml119 reg = <0x0aa00000 0xff000>;
135 iommus = <&apps_smmu 0x10a0 0x8>,
136 <&apps_smmu 0x10b0 0x0>;
Dqcom,sdm845-venus.yaml132 reg = <0x0aa00000 0xff000>;
139 iommus = <&apps_smmu 0x10a0 0x8>,
140 <&apps_smmu 0x10b0 0x0>;
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Dpci.h15 #define RTK_PCI_CTRL 0x300
18 #define REG_DBI_WDATA_V1 0x03E8
19 #define REG_DBI_RDATA_V1 0x03EC
20 #define REG_DBI_FLAG_V1 0x03F0
26 #define REG_MDIO_V1 0x03F4
27 #define REG_PCIE_MIX_CFG 0x03F8
28 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
31 #define RTW_PCI_MDIO_PG_OFFS_G1 0
35 #define RTK_PCIE_LINK_CFG 0x0719
38 #define RTK_PCIE_CLKDLY_CTRL 0x0725
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/lima/
Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dgpucc-msm8998.c36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
73 .offset = 0x0,
88 { P_XO, 0 },
[all …]
/kernel/linux/linux-5.10/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h26 #define CN6XXX_XPANSION_BAR 0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
[all …]

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