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12

/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
Dphy_lcn.c66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mn-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
Dfsl,imx8mm-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
77 <0x240 0x4A8 0x000 0x0 0x0 0x140>;
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_lcn.c40 #define NOISE_IF_OFF 0
45 #define PAPD2LUT 0
46 #define PAPD_CORR_NORM 0
47 #define PAPD_BLANKING_THRESHOLD 0
48 #define PAPD_STOP_AFTER_LAST_UPDATE 0
70 (0 + 8)
72 (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
75 (0 + 8)
77 (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
85 (read_phy_reg((pi), 0x451) & \
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/kernel/linux/linux-5.10/drivers/ntb/hw/amd/
Dntb_hw_amd.h56 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
57 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
97 AMD_CNTL_OFFSET = 0x200,
106 AMD_STA_OFFSET = 0x204,
107 AMD_PGSLV_OFFSET = 0x208,
108 AMD_SPAD_MUX_OFFSET = 0x20C,
109 AMD_SPAD_OFFSET = 0x210,
110 AMD_RSMU_HCID = 0x250,
111 AMD_RSMU_SIID = 0x254,
112 AMD_PSION_OFFSET = 0x300,
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra-audio.c17 #define AUDIO_SYNC_CLK_I2S0 0x4a0
18 #define AUDIO_SYNC_CLK_I2S1 0x4a4
19 #define AUDIO_SYNC_CLK_I2S2 0x4a8
20 #define AUDIO_SYNC_CLK_I2S3 0x4ac
21 #define AUDIO_SYNC_CLK_I2S4 0x4b0
22 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
23 #define AUDIO_SYNC_CLK_DMIC1 0x560
24 #define AUDIO_SYNC_CLK_DMIC2 0x564
25 #define AUDIO_SYNC_CLK_DMIC3 0x6b8
27 #define AUDIO_SYNC_DOUBLER 0x49c
[all …]
/kernel/linux/linux-5.10/drivers/staging/mt7621-pci-phy/
Dpci-mt7621-phy.c19 #define RG_PE1_PIPE_REG 0x02c
23 #define RG_P0_TO_P1_WIDTH 0x100
24 #define RG_PE1_H_LCDDS_REG 0x49c
25 #define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
26 #define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
28 #define RG_PE1_FRC_H_XTAL_REG 0x400
31 #define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
33 #define RG_PE1_FRC_PHY_REG 0x000
37 #define RG_PE1_H_PLL_REG 0x490
39 #define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dahci_tegra.c27 #define SATA_CONFIGURATION_0 0x180
28 #define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
31 #define SCFG_OFFSET 0x1000
33 #define T_SATA0_CFG_1 0x04
34 #define T_SATA0_CFG_1_IO_SPACE BIT(0)
39 #define T_SATA0_CFG_9 0x24
40 #define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
42 #define SATA_FPCI_BAR5 0x94
43 #define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
44 #define SATA_FPCI_BAR5_START (0x0040020 << 4)
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra186.c45 for (i = 0; i < mc->soc->num_clients; i++) { in tegra186_mc_program_sid()
73 .override = 0x000,
74 .security = 0x004,
80 .override = 0x070,
81 .security = 0x074,
87 .override = 0x0a8,
88 .security = 0x0ac,
94 .override = 0x0b0,
95 .security = 0x0b4,
101 .override = 0x0e0,
[all …]
Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
[all …]
Dtegra124-emc.c25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
29 #define EMC_INTSTATUS 0x0
32 #define EMC_CFG 0xc
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
40 #define EMC_REFCTRL 0x20
41 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
44 #define EMC_TIMING_CONTROL 0x28
45 #define EMC_RC 0x2c
[all …]
/kernel/linux/linux-5.10/sound/soc/sh/rcar/
Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
164 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
189 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
193 regf.lsb = 0; in _rsnd_gen_regmap_init()
206 return 0; in _rsnd_gen_regmap_init()
215 RSND_GEN_S_REG(SSI_MODE0, 0x800), in rsnd_gen2_probe()
216 RSND_GEN_S_REG(SSI_MODE1, 0x804), in rsnd_gen2_probe()
217 RSND_GEN_S_REG(SSI_MODE2, 0x808), in rsnd_gen2_probe()
[all …]
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dclk-hi6220.c26 { HI6220_REF32K, "ref32k", NULL, 0, 32764, },
27 { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, },
28 { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, },
29 { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, },
30 { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, },
31 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, },
32 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,},
33 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,},
34 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,},
35 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dpm-imx6.c29 #define CCR 0x0
30 #define BM_CCR_WB_COUNT (0x7 << 16)
31 #define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
32 #define BM_CCR_RBC_EN (0x1 << 27)
34 #define CLPCR 0x54
35 #define BP_CLPCR_LPM 0
36 #define BM_CLPCR_LPM (0x3 << 0)
37 #define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
38 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
39 #define BM_CLPCR_SBYOS (0x1 << 6)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
Dtvmodesnv17.c54 0x2a, 0x9, 0x8a, 0xcb, 0x0, 0x0, 0xb, 0x18,
55 0x7e, 0x40, 0x8a, 0x35, 0x27, 0x0, 0x34, 0x3,
56 0x3e, 0x3, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x9c,
57 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x3,
58 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5,
59 0x0, 0x1a, 0xff, 0x3, 0x18, 0xf, 0x78, 0x0,
60 0x0, 0xb4, 0x0, 0x15, 0x49, 0x10, 0x0, 0x9b,
61 0xbd, 0x15, 0x5, 0x15, 0x3e, 0x3, 0x0, 0x0
66 0x21, 0xe6, 0xef, 0xe3, 0x0, 0x0, 0xb, 0x18,
67 0x7e, 0x44, 0x76, 0x32, 0x25, 0x0, 0x3c, 0x0,
[all …]

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