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/kernel/linux/linux-5.10/drivers/soc/ux500/
Dux500-soc-id.c25 * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard"
26 * @partnumber: hithereto 0x8500 for DB8500
43 return 0; in ux500_read_asicid()
57 if (rev == 0x01) in ux500_print_soc_info()
59 else if (rev >= 0xA0) in ux500_print_soc_info()
60 pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); in ux500_print_soc_info()
69 return (asicid >> 8) & 0xffff; in partnumber()
74 * DB8500ed 0x410fc090 0x9001FFF4 0x00850001
75 * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0
76 * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dsocionext,uniphier-ave4.yaml93 reg = <0x65000000 0x8500>;
94 interrupts = <0 66 4>;
101 socionext,syscon-phy-mode = <&soc_glue 0>;
105 #size-cells = <0>;
/kernel/linux/linux-5.10/drivers/media/usb/gspca/
Dspca561.c37 #define Rev012A 0
64 .priv = 0},
87 .priv = 0},
112 #define SPCA561_INDEX_I2C_BASE 0x8800
113 #define SPCA561_SNAPBIT 0x20
114 #define SPCA561_SNAPCTRL 0x40
117 {0x0000, 0x8114}, /* Software GPIO output data */
118 {0x0001, 0x8114}, /* Software GPIO output data */
119 {0x0000, 0x8112}, /* Some kind of reset */
123 {0x0003, 0x8701}, /* PCLK clock delay adjustment */
[all …]
Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprcm43xx.h18 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
19 #define AM43XX_PRM_MPU_INST 0x0300
20 #define AM43XX_PRM_GFX_INST 0x0400
21 #define AM43XX_PRM_RTC_INST 0x0500
22 #define AM43XX_PRM_TAMPER_INST 0x0600
23 #define AM43XX_PRM_CEFUSE_INST 0x0700
24 #define AM43XX_PRM_PER_INST 0x0800
25 #define AM43XX_PRM_WKUP_INST 0x2000
26 #define AM43XX_PRM_DEVICE_INST 0x4000
29 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
/kernel/linux/linux-5.10/include/video/
Dtrident.h4 #define TRIDENTFB_DEBUG 0
20 #define CYBER9320 0x9320
21 #define CYBER9388 0x9388
22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
23 #define CYBER9385 0x9385 /* ditto */
24 #define CYBER9397 0x9397
25 #define CYBER9397DVD 0x939A
26 #define CYBER9520 0x9520
27 #define CYBER9525DVD 0x9525
28 #define TGUI9440 0x9440
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dstv6111.c46 { 2572, 0 },
82 { 1548, 0 },
118 { 4870, 0x3000 },
119 { 4850, 0x3C00 },
120 { 4800, 0x4500 },
121 { 4750, 0x4800 },
122 { 4700, 0x4B00 },
123 { 4650, 0x4D00 },
124 { 4600, 0x4F00 },
125 { 4550, 0x5100 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Dvlv_suspend.c114 /* GAM 0x4000-0x4770 */ in vlv_save_gunit_s0ix_state()
121 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) in vlv_save_gunit_s0ix_state()
134 /* MBC 0x9024-0x91D0, 0x8500 */ in vlv_save_gunit_s0ix_state()
139 /* GCP 0x9400-0x9424, 0x8100-0x810C */ in vlv_save_gunit_s0ix_state()
147 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ in vlv_save_gunit_s0ix_state()
159 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ in vlv_save_gunit_s0ix_state()
165 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) in vlv_save_gunit_s0ix_state()
168 /* GT SA CZ domain, 0x100000-0x138124 */ in vlv_save_gunit_s0ix_state()
175 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ in vlv_save_gunit_s0ix_state()
183 * DFT, 0x9800-0x9EC0 in vlv_save_gunit_s0ix_state()
[all …]
Dintel_uncore.c51 mmio_debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
80 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
101 fw_clear(d, 0xffff); in fw_domain_reset()
129 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
150 ACK_CLEAR = 0,
159 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
191 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
197 return ack_detected ? 0 : -ETIMEDOUT; in fw_domain_wait_ack_with_fallback()
324 * w/a for a sporadic read returning 0 by waiting for the GT in __gen6_gt_wait_for_thread_c0()
328 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), in __gen6_gt_wait_for_thread_c0()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
Dpq2fads.dts26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x60>;
52 ranges = <0x0 0x0 0xff800000 0x800000
53 0x1 0x0 0xf4500000 0x8000
54 0x8 0x0 0xf8200000 0x8000>;
[all …]
Dmpc8272ads.dts25 #size-cells = <0>;
27 PowerPC,8272@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x40>;
52 ranges = <0x0 0x0 0xff800000 0x00800000
53 0x1 0x0 0xf4500000 0x8000
[all …]
Dmgcoge.dts23 #size-cells = <0>;
25 PowerPC,8247@0 {
27 reg = <0>;
32 timebase-frequency = <0>; /* Filled in by U-Boot */
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 bus-frequency = <0>; /* Filled in by U-Boot */
44 reg = <0xf0010100 0x40>;
46 ranges = <0 0 0xfe000000 0x00400000
47 1 0 0x30000000 0x00010000
48 2 0 0x40000000 0x00010000
[all …]
/kernel/linux/linux-5.10/arch/powerpc/sysdev/
Dfsl_pci.c55 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) in quirk_fsl_pcie_early()
68 u32 val = 0; in fsl_pcie_check_link()
72 __indirect_read_config(hose, hose->first_busno, 0, in fsl_pcie_check_link()
75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); in fsl_pcie_check_link()
87 return 0; in fsl_pcie_check_link()
138 dev->bus_dma_limit = 0; in fsl_pci_dma_set_mask()
150 u32 flags = 0x80044000; /* enable & mem R/W */ in setup_one_atmu()
153 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", in setup_one_atmu()
157 flags |= 0x10000000; /* enable relaxed ordering */ in setup_one_atmu()
159 for (i = 0; size > 0; i++) { in setup_one_atmu()
[all …]
/kernel/linux/linux-5.10/drivers/net/usb/
Dsr9800.h16 #define SR_CMD_SET_SW_MII 0x06
18 #define SR_CMD_READ_MII_REG 0x07
20 #define SR_CMD_WRITE_MII_REG 0x08
22 #define SR_CMD_SET_HW_MII 0x0a
24 #define SR_CMD_READ_EEPROM 0x0b
26 #define SR_CMD_WRITE_EEPROM 0x0c
28 #define SR_CMD_WRITE_ENABLE 0x0d
30 #define SR_CMD_WRITE_DISABLE 0x0e
32 #define SR_CMD_READ_RX_CTL 0x0f
33 #define SR_RX_CTL_PRO (1 << 0)
[all …]
/kernel/linux/linux-5.10/lib/
Dcrc-ccitt.c13 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
17 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
18 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
19 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
20 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
21 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
22 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
23 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
24 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
25 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmeson.dtsi22 reg = <0xc1100000 0x200000>;
25 ranges = <0x0 0xc1100000 0x200000>;
31 reg = <0x4000 0x400>;
36 reg = <0x7c00 0x200>;
41 reg = <0x8100 0x8>;
46 reg = <0x84c0 0x18>;
53 reg = <0x84dc 0x18>;
60 reg = <0x8500 0x20>;
63 #size-cells = <0>;
69 reg = <0x8550 0x10>;
[all …]
Dam43xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x0040>;
17 #clock-cells = <0>;
21 reg = <0x0040>;
25 #clock-cells = <0>;
29 reg = <0x0040>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
79 #size-cells = <0>;
[all …]
Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi20 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0 0x000>;
52 reg = <0 0x001>;
62 reg = <0 0x002>;
72 reg = <0 0x003>;
126 #clock-cells = <0>;
181 reg = <0x0 0x81000000 0x0 0x01000000>;
186 soc@0 {
190 ranges = <0 0 0 0xffffffff>;
[all …]
Duniphier-ld11.dtsi19 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0 0x000>;
44 reg = <0 0x001>;
93 #clock-cells = <0>;
117 reg = <0x0 0x81000000 0x0 0x01000000>;
122 soc@0 {
126 ranges = <0 0 0 0xffffffff>;
131 reg = <0x54006000 0x100>;
133 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/
Dtc358743_regs.h19 #define CHIPID 0x0000
20 #define MASK_CHIPID 0xff00
21 #define MASK_REVID 0x00ff
23 #define SYSCTL 0x0002
24 #define MASK_IRRST 0x0800
25 #define MASK_CECRST 0x0400
26 #define MASK_CTXRST 0x0200
27 #define MASK_HDMIRST 0x0100
28 #define MASK_SLEEP 0x0001
30 #define CONFCTL 0x0004
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]

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