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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml16 Opcode of the instruction
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
26 …C++ base that represent this opcode. In far future if we managed to generate also instruction clas…
30 Properties of the instruction, such as: arithmetic, binop, throw, etc
33 Modes which the instruction can be used in
36 # Templates aim to reduce boilerplate in instruction description.
122 description: Phi instruction
128 description: Pseudo instruction that inserted by Register Allocator.
155 description: Pseudo instruction, inserted in the beginning of try-block.
163 …Pseudo instruction, which is inserted in the Catch handler basic block, and defines virtual regist…
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/arkcompiler/runtime_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
29 …inst_check->SetInput(0, FindOrCreate32BitConstant(instruction->GetImm<<%= inst.get_format %>, 0>()…
37 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
45 … auto inst = graph_->CreateInstAdd(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddress()));
46 inst->SetInput(0, GetDefinition(instruction->GetVReg<<%=inst.get_format%>, 0>()));
48 … inst->SetInput(1, FindOrCreate32BitConstant(instruction->GetImm<<%=inst.get_format%>, 0>()));
50 inst->SetInput(1, FindOrCreateConstant(instruction->GetImm<<%=inst.get_format%>, 0>()));
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/arkcompiler/ets_frontend/testTs/instype/
Drecordthis-expected.txt2 (instruction order, type): (-2, 111), (-1, 106),
4 (instruction order, type): (-2, 111), (-1, 102),
6 (instruction order, type): (-2, 111), (-1, 103),
8 (instruction order, type): (-2, 111), (-1, 104),
10 (instruction order, type): (-2, 111), (-1, 105),
12 (instruction order, type): (-2, 111), (-1, 107), (16, 4),
14 (instruction order, type): (-2, 101), (-1, 108),
16 (instruction order, type): (-2, 111), (-1, 109),
18 (instruction order, type): (-2, 111), (-1, 110),
20 (instruction order, type): (-1, 112), (9, 1),
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Drecordimport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
12 (instruction order, type): (5, 101), (8, 105), (19, 107), (22, 102), (25, 103), (31, 104), (37, 106…
Drecordexport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
/arkcompiler/runtime_core/docs/
Dir_format.md7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
65 ## Instruction set
76 …le to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those …
81 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
87 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
178 **Inst** is a base class with main information about an instruction.
179 * Opcode(name) of the instruction
180 * pc(address) instruction in bytecode/file
181 * Type of instruction(bool, uint8, uint32, float, double e.t.c)
189 Class **FixedInputsInst** inherits from **Inst** for instruction with a fixed number of inputs(oper…
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Drationale-for-bytecode.md40 Just as real CPUs can expose different instruction set architectures, there is no universal way of
72 operates with smaller instructions. Indeed, each instruction `push_arg1`, `push_arg1`, and `add`
77 just a single register-based instruction. Since the interpreter has an extra work to do to read
78 each bytecode instruction, execute it and move to the next one, running more instruction results in
87 **Panda uses register-based instruction set architecture**.
112 some "stack-based'ness" into an otherwise register-based instruction set in attempt to make the
149 the instruction as follows:
172 instruction lacks a wide-range form, we can prepare operands for it with moves that have all
175 With such approach, we can carefully introduce various "overloads" for instruction when it could
185 `adda ...` instruction, what are types of its operands?
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/arkcompiler/runtime_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
58 6. If instruction is a terminator, goto 1, else goto 4.
60 `Virtual register map` is a map, where key is virtual register, value is an IR instruction that cur…
66 …or all constants that are used in instructions with different types, split constant instruction and
99 # Next instruction starts new basic block
125 Example of the case for the `ADD` bytecode instruction in autogenerated `BuildInstruction` function.
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Dvn_doc.md5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
Ddeoptimize_elimination_doc.md17 If `SaveStateDeoptimize` didn't have users, this instruction is replaced by `NOP`.
22 * Other constant -> `DeoptimizeIf` is replaced by `Deoptimize` instruction.
29 …rithm try to replaced by `NOP` all `DeoptimizeIf` instruction which is dominated by current instru…
/arkcompiler/runtime_core/tests/cts-generator/cts-template/
Djnez.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
44 description: Check 'jnez.obj' instruction with invalid offset.
68 description: Check 'jnez.obj' instruction with uninitialized accumulator.
84 description: Check 'jnez.obj' instruction with invalid branch target.
132 … description: Check 'jnez.obj' instruction with prohibited branch target in PandaAssembly context.
209 … description: Check 'jnez.obj' instruction with prohibited branch target in PandaAssembly context.
281 description: Check 'jnez.obj' instruction with invalid accumulator value
389 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
391 instruction address.
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Djeqz.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
44 description: Check 'jeqz.obj' instruction with invalid offset.
68 description: Check 'jeqz.obj' instruction with uninitialized accumulator.
84 description: Check 'jeqz.obj' instruction with invalid branch target.
132 … description: Check 'jeqz.obj' instruction with prohibited branch target in PandaAssembly context.
209 … description: Check 'jeqz.obj' instruction with prohibited branch target in PandaAssembly context.
281 description: Check 'jeqz.obj' instruction with invalid accumulator value
389 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
391 instruction address.
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Djne.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
48 description: Check 'jne.obj' instruction with invalid 'v' register.
78 description: Check 'jne.obj' instruction with invalid 'a' register.
112 description: Check 'jne.obj' instruction with valid 'v' register.
143 description: Check 'jne.obj' instruction with valid 'a' register.
198 description: Check 'jne.obj' instruction with uninitialized registers.
225 description: Check 'jne.obj' instruction with invalid branch target.
273 … description: Check 'jne.obj' instruction with prohibited branch target in PandaAssembly context.
352 … description: Check 'jne.obj' instruction with prohibited branch target in PandaAssembly context.
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Djeq.obj.yaml24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
48 description: Check 'jeq.obj' instruction with invalid 'v' register.
78 description: Check 'jeq.obj' instruction with invalid 'a' register.
112 description: Check 'jeq.obj' instruction with valid 'v' register.
142 description: Check 'jeq.obj' instruction with valid 'a' register.
197 description: Check 'jeq.obj' instruction with uninitialized registers.
224 description: Check 'jeq.obj' instruction with invalid branch target.
272 … description: Check 'jeq.obj' instruction with prohibited branch target in PandaAssembly context.
350 … description: Check 'jeq.obj' instruction with prohibited branch target in PandaAssembly context.
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Djeq.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jeq' instruction with invalid 'v' register.
62 description: Check 'jeq' instruction with invalid 'a' register.
96 description: Check 'jeq' instruction with valid 'v' register.
126 description: Check 'jeq' instruction with valid 'a' register.
180 description: Check 'jeq' instruction with uninitialized registers.
207 description: Check 'jeq' instruction with invalid branch target.
258 description: Check 'jeq' instruction with prohibited branch target.
331 description: Check 'jeq' instruction with invalid accumulator value
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Djgt.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jgt' instruction with invalid 'v' register.
62 description: Check 'jgt' instruction with invalid 'a' register.
96 description: Check 'jgt' instruction with valid 'v' register.
126 description: Check 'jgt' instruction with valid 'a' register.
176 description: Check 'jgt' instruction with uninitialized registers.
203 description: Check 'jgt' instruction with invalid branch target.
254 description: Check 'jgt' instruction with prohibited branch target.
327 description: Check 'jgt' instruction with invalid accumulator value
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Djle.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jle' instruction with invalid 'v' register.
62 description: Check 'jle' instruction with invalid 'a' register.
96 description: Check 'jle' instruction with valid 'v' register.
126 description: Check 'jle' instruction with valid 'a' register.
176 description: Check 'jle' instruction with uninitialized registers.
203 description: Check 'jle' instruction with invalid branch target.
254 description: Check 'jle' instruction with prohibited branch target.
327 description: Check 'jle' instruction with invalid accumulator value
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Djlt.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jlt' instruction with invalid 'v' register.
62 description: Check 'jlt' instruction with invalid 'a' register.
96 description: Check 'jlt' instruction with valid 'v' register.
126 description: Check 'jlt' instruction with valid 'a' register.
176 description: Check 'jlt' instruction with uninitialized registers.
203 description: Check 'jlt' instruction with invalid branch target.
254 description: Check 'jlt' instruction with prohibited branch target.
327 description: Check 'jlt' instruction with invalid accumulator value
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Djge.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jge' instruction with invalid 'v' register.
62 description: Check 'jge' instruction with invalid 'a' register.
96 description: Check 'jge' instruction with valid 'v' register.
126 description: Check 'jge' instruction with valid 'a' register.
176 description: Check 'jge' instruction with uninitialized registers.
203 description: Check 'jge' instruction with invalid branch target.
254 description: Check 'jge' instruction with prohibited branch target.
327 description: Check 'jge' instruction with invalid accumulator value
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Djne.yaml19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
21 instruction address.
35 description: Check 'jne' instruction with invalid 'v' register.
62 description: Check 'jne' instruction with invalid 'a' register.
96 description: Check 'jne' instruction with valid 'v' register.
126 description: Check 'jne' instruction with valid 'a' register.
176 description: Check 'jne' instruction with uninitialized registers.
203 description: Check 'jne' instruction with invalid branch target.
254 description: Check 'jne' instruction with prohibited branch target.
327 description: Check 'jne' instruction with invalid accumulator value
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/arkcompiler/runtime_core/bytecode_optimizer/
Dbytecode_optimizer_isapi.rb16 Instruction.class_eval do
48 @instruction_hash = Hash.new { |_, key| raise "No instruction with '#{key}' mnemonic" }
100 Leaf = Struct.new(:instruction, :args) do
104 if instruction.acc_read?
105 res << do_lda(instruction)
108 res << "enc->result_.emplace_back(pandasm::Create_#{instruction.asm_token}(\n"
111 if instruction.acc_write?
112 res << do_sta(instruction)
119 reg = instruction.operands.select(&:reg?).first
180 # Type/cc cases for instruction selection
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/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
Dassembler_aarch64_constants.h219 /* Aarch64 Instruction MOVZ Field Defines
222 Aarch64 Instruction MOVN Field Defines
225 Aarch64 Instruction MOVK Field Defines
233 /* Aarch64 Instruction AddImm Field Defines
236 Aarch64 Instruction AddShift Field Defines
239 Aarch64 Instruction AddExtend Field Defines
253 Aarch64 Instruction OrrImm Field Defines
256 Aarch64 Instruction ORRShift Field Defines
268 Aarch64 Instruction CMP Instruction is aliase of Subs
269 Aarch64 Instruction CSEL Field Defines
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/arkcompiler/runtime_core/tests/checked/
DREADME.md4 For example, check some event was raised or some IR instruction is appeared after specific optimiza…
32 * **INST** (inst: pattern) search specified instruction in the ir dump file specified by commands `…
33 * **INST_NOT** (inst: pattern) equal to `NOT INST`, i.e. check that instruction is not exist
34 * **INST_NEXT_NOT** (event: pattern) ensure instruction is not occurred after current position
40 …st: pattern) select a specified instruction in disasm file, next "ASM*" checks will be applied onl…
/arkcompiler/runtime_core/isa/
DChangeLog.md5 + ISAPI: removed acc_none, acc_read, acc_write properties in favor of Instruction::acc_none?,
6 Instruction::acc_read?, Instruction::acc_write? properties
/arkcompiler/runtime_core/tests/cts-generator/generator/
Dtest_case.rb22 … def initialize(command, current_case, instruction, definitions, predefined, template, skip_header) argument
23 super instruction, command, definitions, predefined, skip_header
25 LOG.debug "TestCase created with '#{command}' '#{current_case}' '#{instruction}'"
39 @instruction = instruction
127 LOG.error "Instruction: #{@instruction}"

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