| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/v4l2_dev/app/v4l2_interface/ |
| D | isp-v4l2-ctrl.c | 30 static int isp_v4l2_ctrl_check_valid( struct v4l2_ctrl *ctrl ) in isp_v4l2_ctrl_check_valid() argument
32 if ( ctrl->is_int == 1 ) { in isp_v4l2_ctrl_check_valid()
33 if ( ctrl->val < ctrl->minimum || ctrl->val > ctrl->maximum ) in isp_v4l2_ctrl_check_valid()
40 static int isp_v4l2_ctrl_s_ctrl_standard( struct v4l2_ctrl *ctrl ) in isp_v4l2_ctrl_s_ctrl_standard() argument
43 struct v4l2_ctrl_handler *hdl = ctrl->handler; in isp_v4l2_ctrl_s_ctrl_standard()
49 ctrl->id, ctrl->val, ctrl->is_int, ctrl->minimum, ctrl->maximum ); in isp_v4l2_ctrl_s_ctrl_standard()
51 if ( isp_v4l2_ctrl_check_valid( ctrl ) < 0 ) { in isp_v4l2_ctrl_s_ctrl_standard()
55 switch ( ctrl->id ) { in isp_v4l2_ctrl_s_ctrl_standard()
57 ret = fw_intf_set_brightness( ctx_id, ctrl->val ); in isp_v4l2_ctrl_s_ctrl_standard()
60 ret = fw_intf_set_contrast( ctx_id, ctrl->val ); in isp_v4l2_ctrl_s_ctrl_standard()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/subdev/sensor/src/platform/ |
| D | system_spi.c | 145 uint32_t ctrl; in system_spi_rw48() local
155 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
156 ctrl |= SPI_CR_MASTER_MODE_MASK; in system_spi_rw48()
158 ctrl |= SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
160 ctrl &= ~SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
162 ctrl |= ( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
164 ctrl &= ~( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
165 SPI_WRITE32( FPGA_SPI_SPICR, ctrl ); in system_spi_rw48()
187 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
188 ctrl |= SPI_CR_ENABLE_MASK; in system_spi_rw48()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/subdev/lens/src/platform/ |
| D | system_spi.c | 145 uint32_t ctrl; in system_spi_rw48() local
155 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
156 ctrl |= SPI_CR_MASTER_MODE_MASK; in system_spi_rw48()
158 ctrl |= SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
160 ctrl &= ~SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
162 ctrl |= ( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
164 ctrl &= ~( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
165 SPI_WRITE32( FPGA_SPI_SPICR, ctrl ); in system_spi_rw48()
187 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
188 ctrl |= SPI_CR_ENABLE_MASK; in system_spi_rw48()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/regs/ |
| D | hdmi_reg_video_path.c | 133 video_path_ctrl ctrl; in hdmi_reg_video_blank_en_set() local
136 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_blank_en_set()
137 ctrl.bits.reg_video_blank_en = reg_video_blank_en; in hdmi_reg_video_blank_en_set()
138 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_video_blank_en_set()
146 video_path_ctrl ctrl; in hdmi_reg_video_blank_en_get() local
149 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_blank_en_get()
150 return ctrl.bits.reg_video_blank_en; in hdmi_reg_video_blank_en_get()
156 video_path_ctrl ctrl; in hdmi_reg_video_lp_disable_set() local
159 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_video_lp_disable_set()
160 ctrl.bits.reg_video_lp_disable = reg_video_lp_disable; in hdmi_reg_video_lp_disable_set()
[all …]
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| D | hdmi_reg_aon.c | 79 ddc_mst_ctrl ctrl; in hdmi_reg_dcc_man_en_set() local
82 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_dcc_man_en_set()
83 ctrl.bits.dcc_man_en = dcc_man_en; in hdmi_reg_dcc_man_en_set()
84 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_dcc_man_en_set()
92 ddc_man_ctrl ctrl; in hdmi_reg_ddc_sda_oen_set() local
95 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_ddc_sda_oen_set()
96 ctrl.bits.ddc_sda_oen = ddc_sda_oen; in hdmi_reg_ddc_sda_oen_set()
97 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_ddc_sda_oen_set()
105 ddc_man_ctrl ctrl; in hdmi_reg_ddc_scl_oen_set() local
108 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_ddc_scl_oen_set()
[all …]
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| D | hdmi_reg_audio_path.c | 40 tx_audio_ctrl ctrl; in hdmi_reg_aud_spdif_en_set() local
43 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_spdif_en_set()
44 ctrl.bits.aud_spdif_en = aud_spdif_en; in hdmi_reg_aud_spdif_en_set()
45 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_spdif_en_set()
53 tx_audio_ctrl ctrl; in hdmi_reg_aud_i2s_en_set() local
56 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_i2s_en_set()
57 ctrl.bits.aud_i2s_en = aud_i2s_en; in hdmi_reg_aud_i2s_en_set()
58 hdmi_tx_reg_write(reg_addr, ctrl.u32); in hdmi_reg_aud_i2s_en_set()
66 tx_audio_ctrl ctrl; in hdmi_reg_aud_layout_set() local
69 ctrl.u32 = hdmi_tx_reg_read(reg_addr); in hdmi_reg_aud_layout_set()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/v4l2_dev/src/platform/ |
| D | system_spi.c | 144 uint32_t ctrl; in system_spi_rw48() local
154 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
155 ctrl |= SPI_CR_MASTER_MODE_MASK; in system_spi_rw48()
157 ctrl |= SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
159 ctrl &= ~SPI_CR_LSB_FIRST_MASK; in system_spi_rw48()
161 ctrl |= ( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
163 ctrl &= ~( SPI_CR_CLK_POLARITY_MASK | SPI_CR_CLK_PHASE_MASK ); in system_spi_rw48()
164 SPI_WRITE32( FPGA_SPI_SPICR, ctrl ); in system_spi_rw48()
186 ctrl = SPI_READ32( FPGA_SPI_SPICR ); in system_spi_rw48()
187 ctrl |= SPI_CR_ENABLE_MASK; in system_spi_rw48()
[all …]
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/bk7235/hal/ |
| D | vault_hal_debug.c | 31 SOC_LOGI(" ctrl addr=0x%x value=0x%x\r\n", &hw->ctrl, hw->ctrl.v); in vault_struct_dump()
32 SOC_LOGI(" abort_req: %x\r\n", hw->ctrl.abort_reg); in vault_struct_dump()
33 SOC_LOGI(" big_end: %x\r\n", hw->ctrl.big_end); in vault_struct_dump()
34 SOC_LOGI(" clk_man_reset_n: %x\r\n", hw->ctrl.clk_man_reset_n); in vault_struct_dump()
35 SOC_LOGI(" cm_reset_n: %x\r\n", hw->ctrl.cm_reset_n); in vault_struct_dump()
36 SOC_LOGI(" ctr_reset_n: %x\r\n", hw->ctrl.ctr_reset_n); in vault_struct_dump()
37 SOC_LOGI(" slv_reset_n: %x\r\n", hw->ctrl.slv_reset_n); in vault_struct_dump()
38 SOC_LOGI(" soft_reset: %x\r\n", hw->ctrl.soft_reset); in vault_struct_dump()
39 SOC_LOGI(" pos_disable: %x\r\n", hw->ctrl.pos_disable); in vault_struct_dump()
40 SOC_LOGI(" power_mode_to_vault: %x\r\n", hw->ctrl.power_mode_to_vault); in vault_struct_dump()
[all …]
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| D | spi_hal_debug.c | 31 SOC_LOGI(" ctrl=0x%x value=0x%x\n", &hw->ctrl, hw->ctrl.v); in spi_struct_dump()
32 SOC_LOGI(" tx_fifo_int_level: %x\n", hw->ctrl.tx_fifo_int_level); in spi_struct_dump()
33 SOC_LOGI(" rx_fifo_int_level: %x\n", hw->ctrl.rx_fifo_int_level); in spi_struct_dump()
34 SOC_LOGI(" tx_udf_int_en: %x\n", hw->ctrl.tx_udf_int_en); in spi_struct_dump()
35 SOC_LOGI(" rx_ovf_int_en: %x\n", hw->ctrl.rx_ovf_int_en); in spi_struct_dump()
36 SOC_LOGI(" tx_fifo_int_en: %x\n", hw->ctrl.tx_fifo_int_en); in spi_struct_dump()
37 SOC_LOGI(" rx_fifo_int_en: %x\n", hw->ctrl.rx_fifo_int_en); in spi_struct_dump()
38 SOC_LOGI(" clk_rate: %x\n", hw->ctrl.clk_rate); in spi_struct_dump()
39 SOC_LOGI(" slave_release_int_en: %x\n", hw->ctrl.slave_release_int_en); in spi_struct_dump()
40 SOC_LOGI(" wire3_en: %x\n", hw->ctrl.wire3_en); in spi_struct_dump()
[all …]
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| D | aon_rtc_ll.h | 30 hw->ctrl.en = 1; in aon_rtc_ll_enable()
35 hw->ctrl.en = 0; in aon_rtc_ll_disable()
40 return hw->ctrl.en; in aon_rtc_ll_is_enable()
45 hw->ctrl.cnt_stop = 1; in aon_rtc_ll_stop_counter()
50 hw->ctrl.cnt_stop = 0; in aon_rtc_ll_start_counter()
55 return hw->ctrl.cnt_stop; in aon_rtc_ll_is_counter_stop()
60 hw->ctrl.cnt_reset = 1; in aon_rtc_ll_reset_counter()
65 hw->ctrl.cnt_reset = 0; in aon_rtc_ll_clear_reset_counter()
70 return hw->ctrl.cnt_reset; in aon_rtc_ll_is_counter_reset()
75 hw->ctrl.ctrl_v = 0; in aon_rtc_ll_clear_ctrl()
[all …]
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| D | pwm_hal_debug.c | 30 SOC_LOGI(" ctrl=%x value=%x\n", &hw->group[group].ctrl, hw->group[group].ctrl.v); in pwm_struct_dump()
32 SOC_LOGI(" chan0_mode: %x\n", hw->group[group].ctrl.chan0_mode); in pwm_struct_dump()
33 SOC_LOGI(" chan0_en: %x\n", hw->group[group].ctrl.chan0_en); in pwm_struct_dump()
34 SOC_LOGI(" chan0_int_en: %x\n", hw->group[group].ctrl.chan0_int_en); in pwm_struct_dump()
35 SOC_LOGI(" chan0_timer_stop: %x\n", hw->group[group].ctrl.chan0_timer_stop); in pwm_struct_dump()
36 SOC_LOGI(" chan0_init_level: %x\n", hw->group[group].ctrl.chan0_init_level); in pwm_struct_dump()
37 SOC_LOGI(" chan0_cfg_update: %x\n", hw->group[group].ctrl.chan0_cfg_update); in pwm_struct_dump()
39 SOC_LOGI(" chan1_mode: %x\n", hw->group[group].ctrl.chan1_mode); in pwm_struct_dump()
40 SOC_LOGI(" chan1_en: %x\n", hw->group[group].ctrl.chan1_en); in pwm_struct_dump()
41 SOC_LOGI(" chan1_int_en: %x\n", hw->group[group].ctrl.chan1_int_en); in pwm_struct_dump()
[all …]
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| D | spi_ll.h | 40 hw->ctrl.tx_fifo_int_level = 0; in spi_ll_init()
41 hw->ctrl.rx_fifo_int_level = 2; in spi_ll_init()
46 hw->ctrl.enable = 1; in spi_ll_enable()
51 hw->ctrl.enable = 0; in spi_ll_disable()
56 hw->ctrl.tx_fifo_int_level = level; in spi_ll_set_tx_fifo_int_level()
61 hw->ctrl.rx_fifo_int_level = level; in spi_ll_set_rx_fifo_int_level()
66 switch (hw->ctrl.tx_fifo_int_level) { in spi_ll_get_tx_fifo_int_level()
81 switch (hw->ctrl.rx_fifo_int_level) { in spi_ll_get_rx_fifo_int_level()
96 hw->ctrl.tx_udf_int_en = 1; in spi_ll_enable_tx_underflow_int()
101 hw->ctrl.tx_udf_int_en = 0; in spi_ll_disable_tx_underflow_int()
[all …]
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| D | adc_ll.h | 28 hw->ctrl.v = 0; in adc_ll_init()
33 hw->ctrl.v = 0; in adc_ll_deinit()
40 hw->ctrl.adc_mode = 0; in adc_ll_set_sleep_mode()
45 hw->ctrl.adc_mode = 1; in adc_ll_set_single_step_mode()
50 hw->ctrl.adc_mode = 2; in adc_ll_set_software_control_mode()
55 hw->ctrl.adc_mode = 3; in adc_ll_set_continuous_mode()
60 return (hw->ctrl.adc_mode & 0x03); in adc_ll_get_adc_mode()
65 hw->ctrl.adc_en = 1; in adc_ll_enable()
70 hw->ctrl.adc_en = 0; in adc_ll_disable()
75 hw->ctrl.adc_channel = (id & 0xFF); in adc_ll_sel_channel()
[all …]
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| D | adc_hal_debug.c | 26 SOC_LOGI(" ctrl=0x%x , v =0x%x\n", &hw->ctrl, hw->ctrl.v); in adc_struct_dump()
27 SOC_LOGI(" adc_mode=%x\n", hw->ctrl.adc_mode); in adc_struct_dump()
28 SOC_LOGI(" adc_enable: %x\n", hw->ctrl.adc_en); in adc_struct_dump()
29 SOC_LOGI(" adc_channel=%x\n", hw->ctrl.adc_channel); in adc_struct_dump()
30 SOC_LOGI(" adc_setting=%x\n", hw->ctrl.adc_setting); in adc_struct_dump()
31 SOC_LOGI(" adc_int_clear=%x\n", hw->ctrl.adc_int_clear); in adc_struct_dump()
32 SOC_LOGI(" adc_div=0x%x\n", hw->ctrl.adc_div); in adc_struct_dump()
33 SOC_LOGI(" adc_32m_mode_enable=%x\n", hw->ctrl.adc_32m_mode); in adc_struct_dump()
34 SOC_LOGI(" adc_sample_rate=0x%x\n", hw->ctrl.adc_samp_rate); in adc_struct_dump()
35 SOC_LOGI(" adc_filter=%x\n", hw->ctrl.adc_filter); in adc_struct_dump()
[all …]
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| D | timer_ll.h | 48 hw->group[group].ctrl.timer0_en = 0; in timer_ll_init()
49 hw->group[group].ctrl.timer0_int_en = 0; in timer_ll_init()
51 hw->group[group].ctrl.timer1_en = 0; in timer_ll_init()
52 hw->group[group].ctrl.timer1_int_en = 0; in timer_ll_init()
54 hw->group[group].ctrl.timer2_en = 0; in timer_ll_init()
55 hw->group[group].ctrl.timer2_int_en = 0; in timer_ll_init()
65 hw->group[group].ctrl.timer0_en = value; in timer_ll_set_enable()
67 hw->group[group].ctrl.timer1_en = value; in timer_ll_set_enable()
69 hw->group[group].ctrl.timer2_en = value; in timer_ll_set_enable()
88 status |= hw->group[group].ctrl.timer0_en << (bit_pos++); in timer_ll_get_enable_status()
[all …]
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| D | efuse_ll.h | 31 hw->ctrl.addr = 0; in efuse_ll_reset_config_to_default()
32 hw->ctrl.wr_data = 0; in efuse_ll_reset_config_to_default()
45 hw->ctrl.en = 1; in efuse_ll_enable()
50 hw->ctrl.en = 0; in efuse_ll_disable()
60 hw->ctrl.dir = 0x1; in efuse_ll_set_direction_write()
65 hw->ctrl.dir = 0x0; in efuse_ll_set_direction_read()
70 hw->ctrl.addr = addr & EFUSE_F_ADDR_M; in efuse_ll_set_addr()
75 hw->ctrl.v &= (~(EFUSE_F_WR_DATA_M << EFUSE_F_WR_DATA_S)); in efuse_ll_set_wr_data()
76 hw->ctrl.v |= ((data & EFUSE_F_WR_DATA_M) << EFUSE_F_WR_DATA_S); in efuse_ll_set_wr_data()
91 hw->ctrl.vdd25_en = 1; in efuse_ll_enable_vdd25()
[all …]
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| D | pwm_ll.h | 49 hw->group[group].ctrl.v = 0; in pwm_ll_init()
55 hw->group[group].ctrl.chan0_en = value; in pwm_ll_set_enable()
57 hw->group[group].ctrl.chan1_en = value; in pwm_ll_set_enable()
73 return (hw->group[PWM_LL_GROUP(chan)].ctrl.chan0_en == 1); in pwm_ll_is_chan_started()
75 return (hw->group[PWM_LL_GROUP(chan)].ctrl.chan1_en == 1); in pwm_ll_is_chan_started()
81 hw->group[group].ctrl.chan0_int_en = value; in pwm_ll_set_interrupt()
83 hw->group[group].ctrl.chan1_int_en = value; in pwm_ll_set_interrupt()
102 status |= hw->group[group].ctrl.chan0_int_st << (group << 1); in pwm_ll_get_interrupt_status()
103 status |= hw->group[group].ctrl.chan1_int_st << ((group << 1) + 1); in pwm_ll_get_interrupt_status()
111 hw->group[0].ctrl.chan0_int_st = status & BIT(0); in pwm_ll_clear_interrupt_status()
[all …]
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| D | dma_hal_debug.c | 29 SOC_LOGI(" ctrl addr=0x%x value=0x%x\n", &hw->config_group[id].ctrl, hw->config_group[id].ctrl.v); in dma_struct_dump()
30 SOC_LOGI(" dma_en: %x\n", hw->config_group[id].ctrl.enable); in dma_struct_dump()
31 SOC_LOGI(" finish_int_en: %x\n", hw->config_group[id].ctrl.finish_int_en); in dma_struct_dump()
32 SOC_LOGI(" half_finish_int_en: %x\n", hw->config_group[id].ctrl.half_finish_int_en); in dma_struct_dump()
33 SOC_LOGI(" dma_work_mode: %x\n", hw->config_group[id].ctrl.mode); in dma_struct_dump()
34 SOC_LOGI(" src_data_width: %x\n", hw->config_group[id].ctrl.src_data_width); in dma_struct_dump()
35 SOC_LOGI(" dest_data_width: %x\n", hw->config_group[id].ctrl.dest_data_width); in dma_struct_dump()
36 SOC_LOGI(" src_addr_increment_en: %x\n", hw->config_group[id].ctrl.src_addr_inc_en); in dma_struct_dump()
37 SOC_LOGI(" dest_addr_increment_en: %x\n", hw->config_group[id].ctrl.dest_addr_inc_en); in dma_struct_dump()
38 SOC_LOGI(" src_addr_loop_en: %x\n", hw->config_group[id].ctrl.src_addr_loop_en); in dma_struct_dump()
[all …]
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| /device/board/unionman/unionpi_tiger/hardware/camera/driver_adapter/src/ |
| D | v4l2_control.cpp | 51 struct v4l2_control ctrl; in V4L2SetCtrls() local
54 ctrl.id = cList[i].id; in V4L2SetCtrls()
55 ctrl.value = cList[i].value; in V4L2SetCtrls()
56 ret = ioctl(fd, VIDIOC_S_CTRL, &ctrl); in V4L2SetCtrls()
101 struct v4l2_control ctrl; in V4L2GetCtrls() local
103 ctrl.id = cList[i].id; in V4L2GetCtrls()
104 ret = ioctl(fd, VIDIOC_G_CTRL, &ctrl); in V4L2GetCtrls()
109 iter->value = ctrl.value; in V4L2GetCtrls()
129 struct v4l2_control ctrl; in V4L2GetCtrl() local
131 ctrl.id = id; in V4L2GetCtrl()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/ |
| D | drv_hdmi_event.c | 74 if (tmp_pool->ctrl.pool_id == pool_id) { in event_mach_id()
150 if (tmp_pool->ctrl.pool_id == cur_gid) { in drv_hdmi_event_pool_malloc()
158 if (!tmp_pool->ctrl.pool_id) { in drv_hdmi_event_pool_malloc()
169 (hi_void)memset_s(&tmp_pool->ctrl, sizeof(tmp_pool->ctrl), 0, sizeof(hdmi_event_run_ctrl)); in drv_hdmi_event_pool_malloc()
171 tmp_pool->ctrl.pool_id = cur_gid; in drv_hdmi_event_pool_malloc()
173 *pool_id = tmp_pool->ctrl.pool_id; in drv_hdmi_event_pool_malloc()
175 tmp_pool->ctrl.wakeup_flag = HI_FALSE; in drv_hdmi_event_pool_malloc()
177 tmp_pool->ctrl.event_pool[i] = HDMI_EVENT_BUTT; in drv_hdmi_event_pool_malloc()
199 if (tmp_pool->ctrl.pool_id == pool_id) { in drv_hdmi_event_pool_free()
201 tmp_pool->ctrl.wakeup_flag = HI_TRUE; in drv_hdmi_event_pool_free()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/drivers/core/ |
| D | drv_trng_v200.c | 32 hisec_com_trng_ctrl ctrl; in drv_trng_randnum() local
40 ctrl.u32 = trng_read(HISEC_COM_TRNG_CTRL); in drv_trng_randnum()
41 if (ctrl.u32 != last) { in drv_trng_randnum()
44 ctrl.bits.mix_enable = 0x00; in drv_trng_randnum()
45 ctrl.bits.drop_enable = 0x00; in drv_trng_randnum()
46 ctrl.bits.pre_process_enable = 0x00; in drv_trng_randnum()
47 ctrl.bits.post_process_enable = 0x00; in drv_trng_randnum()
48 ctrl.bits.post_process_depth = 0x00; in drv_trng_randnum()
49 ctrl.bits.drbg_enable = 0x01; in drv_trng_randnum()
50 ctrl.bits.osc_sel = TRNG_OSC_SEL; in drv_trng_randnum()
[all …]
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| D | drv_trng_v100.c | 36 rng_ctrl ctrl; in drv_trng_randnum() local
44 if (ctrl.u32 != last) { in drv_trng_randnum()
47 ctrl.u32 = trng_read(RNG_CTRL); in drv_trng_randnum()
48 ctrl.bits.filter_enable = 0x00; in drv_trng_randnum()
49 ctrl.bits.mix_en = 0x00; in drv_trng_randnum()
50 ctrl.bits.drop_enable = 0x00; in drv_trng_randnum()
51 ctrl.bits.post_process_enable = 0x01; in drv_trng_randnum()
52 ctrl.bits.post_process_depth = TRNG_POST_PROCESS_DEPTH; in drv_trng_randnum()
53 ctrl.bits.osc_sel = TRNG_OSC_SEL; in drv_trng_randnum()
54 trng_write(RNG_CTRL, ctrl.u32); in drv_trng_randnum()
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/sys_ctrl/ |
| D | sys_usb_driver.c | 19 uint32_t sys_drv_usb_analog_phy_en(bool ctrl, void *arg) in sys_drv_usb_analog_phy_en() argument
23 sys_hal_usb_analog_phy_en(ctrl); in sys_drv_usb_analog_phy_en()
29 uint32_t sys_drv_usb_analog_speed_en(bool ctrl, void *arg) in sys_drv_usb_analog_speed_en() argument
37 sys_hal_usb_analog_speed_en(ctrl); in sys_drv_usb_analog_speed_en()
48 uint32_t sys_drv_usb_analog_ckmcu_en(bool ctrl, void *arg) in sys_drv_usb_analog_ckmcu_en() argument
57 sys_hal_usb_analog_ckmcu_en(ctrl); in sys_drv_usb_analog_ckmcu_en()
83 void sys_drv_usb_charge_stop(bool ctrl) in sys_drv_usb_charge_stop() argument
87 sys_hal_usb_enable_charge(ctrl); in sys_drv_usb_charge_stop()
92 void sys_drv_usb_charge_ctrl(bool ctrl, void *arg) in sys_drv_usb_charge_ctrl() argument
96 if(ctrl) in sys_drv_usb_charge_ctrl()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/v4l2_dev/src/driver/lens/ |
| D | lens_init.c | 61 int32_t lens_init( void **ctx, lens_control_t *ctrl ) in lens_init() argument
67 lens_v4l2_subdev_init( ctx, ctrl, lens_bus ); in lens_init()
74 lens_dongwoon_init( ctx, ctrl, lens_bus ); in lens_init()
81 lens_dw9800_init( ctx, ctrl, lens_bus ); in lens_init()
88 lens_AD5821_init( ctx, ctrl, lens_bus ); in lens_init()
95 lens_rohm_init( ctx, ctrl, lens_bus ); in lens_init()
102 lens_LC898201_init( ctx, ctrl, lens_bus ); in lens_init()
109 lens_fp5510a_init( ctx, ctrl, lens_bus ); in lens_init()
116 lens_BU64748_init( ctx, ctrl, lens_bus ); in lens_init()
123 lens_an41908a_init( ctx, ctrl, lens_bus ); in lens_init()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/subdev/lens/src/driver/lens/ |
| D | lens_init.c | 61 int32_t lens_init( void **ctx, lens_control_t *ctrl ) in lens_init() argument
67 lens_v4l2_subdev_init( ctx, ctrl, lens_bus ); in lens_init()
74 lens_dongwoon_init( ctx, ctrl, lens_bus ); in lens_init()
81 lens_dw9800_init( ctx, ctrl, lens_bus ); in lens_init()
88 lens_AD5821_init( ctx, ctrl, lens_bus ); in lens_init()
95 lens_rohm_init( ctx, ctrl, lens_bus ); in lens_init()
102 lens_LC898201_init( ctx, ctrl, lens_bus ); in lens_init()
109 lens_fp5510a_init( ctx, ctrl, lens_bus ); in lens_init()
116 lens_BU64748_init( ctx, ctrl, lens_bus ); in lens_init()
123 lens_an41908a_init( ctx, ctrl, lens_bus ); in lens_init()
[all …]
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