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Searched refs:setup (Results 1 – 25 of 98) sorted by relevance

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/device/soc/rockchip/rk3568/hardware/codec/src/
Dhdi_mpp_config.c114 void SetDefaultFps(RKHdiEncodeSetup *setup) in SetDefaultFps() argument
116 setup->fps.fpsInFlex = 0; in SetDefaultFps()
117 setup->fps.fpsInNum = FPS_SETUP_DEFAULT; in SetDefaultFps()
118 setup->fps.fpsOutNum = FPS_SETUP_DEFAULT; in SetDefaultFps()
119 setup->fps.fpsInDen = 1; in SetDefaultFps()
120 setup->fps.fpsOutDen = 1; in SetDefaultFps()
121 setup->fps.fpsOutFlex = 0; in SetDefaultFps()
124 void SetDefaultDropMode(RKHdiEncodeSetup *setup) in SetDefaultDropMode() argument
126 setup->drop.dropMode = MPP_ENC_RC_DROP_FRM_DISABLED; in SetDefaultDropMode()
127 setup->drop.dropThd = DFAULT_ENC_DROP_THD; /* 20% of max bps */ in SetDefaultDropMode()
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Dhdi_mpp.c36 component->setup.fmt = PIXEL_FMT_BUTT; in InitComponentSetup()
38 SetDefaultFps(&component->setup); in InitComponentSetup()
39 SetDefaultDropMode(&component->setup); in InitComponentSetup()
40 component->setup.rc.rcMode = MPP_ENC_RC_MODE_VBR; in InitComponentSetup()
41 SetDefaultGopMode(&component->setup); in InitComponentSetup()
610 component->setup.width = width; in HandleDecodeFrameInfoChange()
611 component->setup.height = height; in HandleDecodeFrameInfoChange()
690 dst.wstride = component->setup.stride.horStride; in PutDecodeFrameToOutput()
691 dst.hstride = component->setup.stride.verStride; in PutDecodeFrameToOutput()
692 dst.format = ConvertHdiFormat2RgaFormat(component->setup.fmt); in PutDecodeFrameToOutput()
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/device/soc/rockchip/rk3588/hardware/codec/src/
Dhdi_mpp_config.c114 void SetDefaultFps(RKHdiEncodeSetup *setup) in SetDefaultFps() argument
116 setup->fps.fpsInFlex = 0; in SetDefaultFps()
117 setup->fps.fpsInNum = FPS_SETUP_DEFAULT; in SetDefaultFps()
118 setup->fps.fpsOutNum = FPS_SETUP_DEFAULT; in SetDefaultFps()
119 setup->fps.fpsInDen = 1; in SetDefaultFps()
120 setup->fps.fpsOutDen = 1; in SetDefaultFps()
121 setup->fps.fpsOutFlex = 0; in SetDefaultFps()
124 void SetDefaultDropMode(RKHdiEncodeSetup *setup) in SetDefaultDropMode() argument
126 setup->drop.dropMode = MPP_ENC_RC_DROP_FRM_DISABLED; in SetDefaultDropMode()
127 setup->drop.dropThd = DFAULT_ENC_DROP_THD; /* 20% of max bps */ in SetDefaultDropMode()
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Dhdi_mpp.c36 component->setup.fmt = PIXEL_FMT_BUTT; in InitComponentSetup()
38 SetDefaultFps(&component->setup); in InitComponentSetup()
39 SetDefaultDropMode(&component->setup); in InitComponentSetup()
40 component->setup.rc.rcMode = MPP_ENC_RC_MODE_VBR; in InitComponentSetup()
41 SetDefaultGopMode(&component->setup); in InitComponentSetup()
610 component->setup.width = width; in HandleDecodeFrameInfoChange()
611 component->setup.height = height; in HandleDecodeFrameInfoChange()
690 dst.wstride = component->setup.stride.horStride; in PutDecodeFrameToOutput()
691 dst.hstride = component->setup.stride.verStride; in PutDecodeFrameToOutput()
692 dst.format = ConvertHdiFormat2RgaFormat(component->setup.fmt); in PutDecodeFrameToOutput()
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
Dmali_kbase_vinstr.c405 struct kbase_ioctl_hwcnt_reader_setup *setup, in kbasep_vinstr_client_create() argument
413 WARN_ON(!setup); in kbasep_vinstr_client_create()
414 WARN_ON(setup->buffer_count == 0); in kbasep_vinstr_client_create()
415 WARN_ON(!is_power_of_2(setup->buffer_count)); in kbasep_vinstr_client_create()
428 phys_em.fe_bm = setup->fe_bm; in kbasep_vinstr_client_create()
429 phys_em.shader_bm = setup->shader_bm; in kbasep_vinstr_client_create()
430 phys_em.tiler_bm = setup->tiler_bm; in kbasep_vinstr_client_create()
431 phys_em.mmu_l2_bm = setup->mmu_l2_bm; in kbasep_vinstr_client_create()
448 vctx->metadata_user, setup->buffer_count, &vcli->dump_bufs); in kbasep_vinstr_client_create()
454 setup->buffer_count, sizeof(*vcli->dump_bufs_meta), GFP_KERNEL); in kbasep_vinstr_client_create()
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Dmali_kbase_kinstr_prfcnt.c1664 union kbase_ioctl_kinstr_prfcnt_setup *setup, in kbasep_kinstr_prfcnt_parse_setup() argument
1669 unsigned int item_count = setup->in.request_item_count; in kbasep_kinstr_prfcnt_parse_setup()
1676 if (!setup->in.requests_ptr || (item_count < 2) || in kbasep_kinstr_prfcnt_parse_setup()
1677 (setup->in.request_item_size == 0) || in kbasep_kinstr_prfcnt_parse_setup()
1687 if (copy_from_user(req_arr, u64_to_user_ptr(setup->in.requests_ptr), in kbasep_kinstr_prfcnt_parse_setup()
1803 union kbase_ioctl_kinstr_prfcnt_setup *setup, in kbasep_kinstr_prfcnt_client_create() argument
1811 WARN_ON(!setup); in kbasep_kinstr_prfcnt_client_create()
1819 err = kbasep_kinstr_prfcnt_parse_setup(kinstr_ctx, setup, &cli->config); in kbasep_kinstr_prfcnt_client_create()
2080 union kbase_ioctl_kinstr_prfcnt_setup *setup) in kbase_kinstr_prfcnt_setup() argument
2085 if (!kinstr_ctx || !setup) in kbase_kinstr_prfcnt_setup()
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
Dmali_kbase_vinstr.h48 …t_reader_setup(struct kbase_vinstr_context *vinstr_ctx, struct kbase_uk_hwcnt_reader_setup *setup);
59 struct kbase_uk_hwcnt_setup *setup);
73 … struct kbase_uk_hwcnt_reader_setup *setup,
Dmali_kbase_vinstr.c191 struct kbase_uk_hwcnt_setup setup; in enable_hwcnt() local
194 setup.dump_buffer = vinstr_ctx->gpu_va; in enable_hwcnt()
195 setup.jm_bm = vinstr_ctx->bitmap[JM_HWCNT_BM]; in enable_hwcnt()
196 setup.tiler_bm = vinstr_ctx->bitmap[TILER_HWCNT_BM]; in enable_hwcnt()
197 setup.shader_bm = vinstr_ctx->bitmap[SHADER_HWCNT_BM]; in enable_hwcnt()
198 setup.mmu_l2_bm = vinstr_ctx->bitmap[MMU_L2_HWCNT_BM]; in enable_hwcnt()
207 err = kbase_instr_hwcnt_enable_internal(kbdev, kctx, &setup); in enable_hwcnt()
1741 …nt_reader_setup(struct kbase_vinstr_context *vinstr_ctx, struct kbase_uk_hwcnt_reader_setup *setup) in kbase_vinstr_hwcnt_reader_setup() argument
1747 KBASE_DEBUG_ASSERT(setup); in kbase_vinstr_hwcnt_reader_setup()
1748 KBASE_DEBUG_ASSERT(setup->buffer_count); in kbase_vinstr_hwcnt_reader_setup()
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Dmali_kbase_mmu_mode_aarch64.c67 static void mmu_get_as_setup(struct kbase_context *kctx, struct kbase_mmu_setup *const setup) in mmu_get_as_setup() argument
72 …setup->memattr = (AS_MEMATTR_IMPL_DEF_CACHE_POLICY << (AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY * 8)… in mmu_get_as_setup()
78 setup->transtab = (u64)kctx->pgd & AS_TRANSTAB_BASE_MASK; in mmu_get_as_setup()
79 setup->transcfg = AS_TRANSCFG_ADRMODE_AARCH64_4K; in mmu_get_as_setup()
Dmali_kbase_mmu_mode_lpae.c67 static void mmu_get_as_setup(struct kbase_context *kctx, struct kbase_mmu_setup *const setup) in mmu_get_as_setup() argument
71 …setup->memattr = (AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY << (AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY… in mmu_get_as_setup()
78 … setup->transtab = ((u64)kctx->pgd & ((0xFFFFFFFFULL << 32) | AS_TRANSTAB_LPAE_ADDR_SPACE_MASK)) | in mmu_get_as_setup()
81 setup->transcfg = 0; in mmu_get_as_setup()
Dmali_kbase_gator_api.c152 struct kbase_uk_hwcnt_reader_setup setup; in kbase_gator_hwcnt_init() local
263 setup.jm_bm = in_out_info->bitmask[0]; in kbase_gator_hwcnt_init()
264 setup.tiler_bm = in_out_info->bitmask[1]; in kbase_gator_hwcnt_init()
265 setup.shader_bm = in_out_info->bitmask[0x2]; in kbase_gator_hwcnt_init()
266 setup.mmu_l2_bm = in_out_info->bitmask[0x3]; in kbase_gator_hwcnt_init()
267 …hand->vinstr_cli = kbase_vinstr_hwcnt_kernel_setup(hand->kbdev->vinstr_ctx, &setup, hand->vinstr_b… in kbase_gator_hwcnt_init()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
Dmali_kbase_vinstr.h54 struct kbase_uk_hwcnt_reader_setup *setup);
67 struct kbase_uk_hwcnt_setup *setup);
82 struct kbase_uk_hwcnt_reader_setup *setup,
Dmali_kbase_vinstr.c216 struct kbase_uk_hwcnt_setup setup; in enable_hwcnt() local
219 setup.dump_buffer = vinstr_ctx->gpu_va; in enable_hwcnt()
220 setup.jm_bm = vinstr_ctx->bitmap[JM_HWCNT_BM]; in enable_hwcnt()
221 setup.tiler_bm = vinstr_ctx->bitmap[TILER_HWCNT_BM]; in enable_hwcnt()
222 setup.shader_bm = vinstr_ctx->bitmap[SHADER_HWCNT_BM]; in enable_hwcnt()
223 setup.mmu_l2_bm = vinstr_ctx->bitmap[MMU_L2_HWCNT_BM]; in enable_hwcnt()
232 err = kbase_instr_hwcnt_enable_internal(kbdev, kctx, &setup); in enable_hwcnt()
1847 struct kbase_uk_hwcnt_reader_setup *setup) in kbase_vinstr_hwcnt_reader_setup() argument
1853 KBASE_DEBUG_ASSERT(setup); in kbase_vinstr_hwcnt_reader_setup()
1854 KBASE_DEBUG_ASSERT(setup->buffer_count); in kbase_vinstr_hwcnt_reader_setup()
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Dmali_kbase_mmu_mode_aarch64.c72 struct kbase_mmu_setup * const setup) in mmu_get_as_setup() argument
77 setup->memattr = in mmu_get_as_setup()
89 setup->transtab = (u64)kctx->pgd & AS_TRANSTAB_BASE_MASK; in mmu_get_as_setup()
90 setup->transcfg = AS_TRANSCFG_ADRMODE_AARCH64_4K; in mmu_get_as_setup()
Dmali_kbase_mmu_mode_lpae.c72 struct kbase_mmu_setup * const setup) in mmu_get_as_setup() argument
76 setup->memattr = in mmu_get_as_setup()
89 setup->transtab = ((u64)kctx->pgd & in mmu_get_as_setup()
94 setup->transcfg = 0; in mmu_get_as_setup()
Dmali_kbase_gator_api.c152 struct kbase_uk_hwcnt_reader_setup setup; in kbase_gator_hwcnt_init() local
256 setup.jm_bm = in_out_info->bitmask[0]; in kbase_gator_hwcnt_init()
257 setup.tiler_bm = in_out_info->bitmask[1]; in kbase_gator_hwcnt_init()
258 setup.shader_bm = in_out_info->bitmask[2]; in kbase_gator_hwcnt_init()
259 setup.mmu_l2_bm = in_out_info->bitmask[3]; in kbase_gator_hwcnt_init()
261 &setup, hand->vinstr_buffer); in kbase_gator_hwcnt_init()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
Dmali_kbase_instr_backend.c58 struct kbase_uk_hwcnt_setup *setup) in kbase_instr_hwcnt_enable_internal() argument
70 if ((setup->dump_buffer == 0ULL) || (setup->dump_buffer & (0x800 - 1))) { in kbase_instr_hwcnt_enable_internal()
99 kbdev->hwcnt.addr = setup->dump_buffer; in kbase_instr_hwcnt_enable_internal()
133 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), setup->dump_buffer & 0xFFFFFFFF, kctx); in kbase_instr_hwcnt_enable_internal()
134 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), setup->dump_buffer >> 0x20, kctx); in kbase_instr_hwcnt_enable_internal()
135 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), setup->jm_bm, kctx); in kbase_instr_hwcnt_enable_internal()
136 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN), setup->shader_bm, kctx); in kbase_instr_hwcnt_enable_internal()
137 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN), setup->mmu_l2_bm, kctx); in kbase_instr_hwcnt_enable_internal()
143 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), setup->tiler_bm, kctx); in kbase_instr_hwcnt_enable_internal()
151 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), setup->tiler_bm, kctx); in kbase_instr_hwcnt_enable_internal()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
Dmali_kbase_instr_backend.c66 struct kbase_uk_hwcnt_setup *setup) in kbase_instr_hwcnt_enable_internal() argument
79 if ((setup->dump_buffer == 0ULL) || (setup->dump_buffer & (2048 - 1))) in kbase_instr_hwcnt_enable_internal()
108 kbdev->hwcnt.addr = setup->dump_buffer; in kbase_instr_hwcnt_enable_internal()
148 setup->dump_buffer & 0xFFFFFFFF, kctx); in kbase_instr_hwcnt_enable_internal()
150 setup->dump_buffer >> 32, kctx); in kbase_instr_hwcnt_enable_internal()
152 setup->jm_bm, kctx); in kbase_instr_hwcnt_enable_internal()
154 setup->shader_bm, kctx); in kbase_instr_hwcnt_enable_internal()
156 setup->mmu_l2_bm, kctx); in kbase_instr_hwcnt_enable_internal()
164 setup->tiler_bm, kctx); in kbase_instr_hwcnt_enable_internal()
173 setup->tiler_bm, kctx); in kbase_instr_hwcnt_enable_internal()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
Dmali_kbase_vinstr.c379 …nstr_client_create(struct kbase_vinstr_context *vctx, struct kbase_ioctl_hwcnt_reader_setup *setup, in kbasep_vinstr_client_create() argument
387 WARN_ON(!setup); in kbasep_vinstr_client_create()
388 WARN_ON(setup->buffer_count == 0); in kbasep_vinstr_client_create()
402 phys_em.fe_bm = setup->fe_bm; in kbasep_vinstr_client_create()
403 phys_em.shader_bm = setup->shader_bm; in kbasep_vinstr_client_create()
404 phys_em.tiler_bm = setup->tiler_bm; in kbasep_vinstr_client_create()
405 phys_em.mmu_l2_bm = setup->mmu_l2_bm; in kbasep_vinstr_client_create()
416 …errcode = kbase_hwcnt_dump_buffer_array_alloc(vctx->metadata, setup->buffer_count, &vcli->dump_buf… in kbasep_vinstr_client_create()
422 …vcli->dump_bufs_meta = kmalloc_array(setup->buffer_count, sizeof(*vcli->dump_bufs_meta), GFP_KERNE… in kbasep_vinstr_client_create()
567 …hwcnt_reader_setup(struct kbase_vinstr_context *vctx, struct kbase_ioctl_hwcnt_reader_setup *setup) in kbase_vinstr_hwcnt_reader_setup() argument
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/
Dmali_kbase_mmu_mode_lpae.c68 static void mmu_get_as_setup(struct kbase_mmu_table *mmut, struct kbase_mmu_setup *const setup) in mmu_get_as_setup() argument
73 …setup->memattr = (AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY << (AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY… in mmu_get_as_setup()
80 … setup->transtab = ((u64)mmut->pgd & ((0xFFFFFFFFULL << 32) | AS_TRANSTAB_LPAE_ADDR_SPACE_MASK)) | in mmu_get_as_setup()
83 setup->transcfg = 0; in mmu_get_as_setup()
/device/board/talkweb/niobe407/liteos_m/drivers/exit/src/
Dhal_exti.c56 if (g_pinsGroup[index].setup) { in LL_Gpio_Exti_Handler()
89 g_pinsGroup[g_exitSetupCounts].setup = SET; in LL_SETUP_EXTI()
91 g_pinsGroup[g_exitSetupCounts].setup= RESET; in LL_SETUP_EXTI()
/device/soc/rockchip/rk3588/hardware/codec/include/
Dhdi_mpp_config.h34 void SetDefaultFps(RKHdiEncodeSetup *setup);
35 void SetDefaultDropMode(RKHdiEncodeSetup *setup);
36 void SetDefaultGopMode(RKHdiEncodeSetup *setup);
/device/soc/rockchip/rk3568/hardware/codec/include/
Dhdi_mpp_config.h34 void SetDefaultFps(RKHdiEncodeSetup *setup);
35 void SetDefaultDropMode(RKHdiEncodeSetup *setup);
36 void SetDefaultGopMode(RKHdiEncodeSetup *setup);
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/arbitration/
DKconfig27 virtualization setup for Mali
36 virtualization setup for Mali
45 virtualization setup for Mali
/device/soc/beken/bk7235/liteos_m/bk_sdk_armino/include/components/
Daud_intf.h46 bk_err_t bk_aud_intf_drv_init(aud_intf_drv_setup_t *setup);
428 bk_err_t bk_aud_intf_voc_init(aud_intf_voc_setup_t setup);

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