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Searched refs:R2 (Results 1 – 25 of 130) sorted by relevance

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/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
Dlos_exc.S85 LDR R2, =OS_NVIC_HFSR
86 LDR R2, [R2]
90 TST R2, #0x80000000
96 TST R2, #0x00000002
102 LDR R2, =OS_NVIC_FSR
103 LDR R2, [R2]
105 TST R2, #0x8000 // BFARVALID
108 TST R2, #0x80 // MMARVALID
141 CLZ R2, R2
143 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
Dlos_exc.S85 LDR R2, =OS_NVIC_HFSR
86 LDR R2, [R2]
90 TST R2, #0x80000000
96 TST R2, #0x00000002
102 LDR R2, =OS_NVIC_FSR
103 LDR R2, [R2]
105 TST R2, #0x8000 // BFARVALID
108 TST R2, #0x80 // MMARVALID
141 CLZ R2, R2
143 ADD R3, R3, R2
[all …]
Dlos_dispatch.S70 MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
159 LDR R2, =g_secureContext
160 LDR R1, [R2]
167 MOV R12, R2 /* R2 = PRIMASK. */
183 MRS R2, PSPLIM
185 …STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of …
192 …LDMIA R1!, {R0, R2-R3} /* Restore secureContext, PSPLIM and LR from the current…
193 MSR PSPLIM, R2
195 LDR R2, =g_secureContext
196 …STR R0, [R2] /* Set the secureContext of the new task to g_secureCont…
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
Dlos_exc.S73 LDR R2, =OS_NVIC_HFSR
74 LDR R2, [R2]
78 TST R2, #0x80000000
84 TST R2, #0x00000002
90 LDR R2, =OS_NVIC_FSR
91 LDR R2, [R2]
93 TST R2, #0x8000 ; BFARVALID
96 TST R2, #0x80 ; MMARVALID
114 CLZ R2, R2
116 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
Dlos_exc.S74 LDR R2, =OS_NVIC_HFSR
75 LDR R2, [R2]
79 TST R2, #0x80000000
85 TST R2, #0x00000002
91 LDR R2, =OS_NVIC_FSR
92 LDR R2, [R2]
94 TST R2, #0x8000 ; BFARVALID
97 TST R2, #0x80 ; MMARVALID
115 CLZ R2, R2
117 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
Dlos_exc.S73 LDR R2, =OS_NVIC_HFSR
74 LDR R2, [R2]
78 TST R2, #0x80000000
84 TST R2, #0x00000002
90 LDR R2, =OS_NVIC_FSR
91 LDR R2, [R2]
93 TST R2, #0x8000 ; BFARVALID
96 TST R2, #0x80 ; MMARVALID
114 CLZ R2, R2
116 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
Dlos_exc.S74 LDR R2, =OS_NVIC_HFSR
75 LDR R2, [R2]
79 TST R2, #0x80000000
85 TST R2, #0x00000002
91 LDR R2, =OS_NVIC_FSR
92 LDR R2, [R2]
94 TST R2, #0x8000 ; BFARVALID
97 TST R2, #0x80 ; MMARVALID
115 CLZ R2, R2
117 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
Dlos_exc.S74 LDR R2, =OS_NVIC_HFSR
75 LDR R2, [R2]
79 TST R2, #0x80000000
85 TST R2, #0x00000002
91 LDR R2, =OS_NVIC_FSR
92 LDR R2, [R2]
94 TST R2, #0x8000 ; BFARVALID
97 TST R2, #0x80 ; MMARVALID
115 CLZ R2, R2
117 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
Dlos_exc.S86 LDR R2, =OS_NVIC_HFSR
87 LDR R2, [R2]
91 TST R2, #0x80000000
97 TST R2, #0x00000002
103 LDR R2, =OS_NVIC_FSR
104 LDR R2, [R2]
106 TST R2, #0x8000 // BFARVALID
109 TST R2, #0x80 // MMARVALID
142 CLZ R2, R2
144 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
Dlos_exc.S83 LDR R2, =OS_NVIC_HFSR
84 LDR R2, [R2]
88 TST R2, #0x80000000
94 TST R2, #0x00000002
100 LDR R2, =OS_NVIC_FSR
101 LDR R2, [R2]
103 TST R2, #0x8000 // BFARVALID
106 TST R2, #0x80 // MMARVALID
139 CLZ R2, R2
141 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
Dlos_exc.S86 LDR R2, =OS_NVIC_HFSR
87 LDR R2, [R2]
91 TST R2, #0x80000000
97 TST R2, #0x00000002
103 LDR R2, =OS_NVIC_FSR
104 LDR R2, [R2]
106 TST R2, #0x8000 // BFARVALID
109 TST R2, #0x80 // MMARVALID
142 CLZ R2, R2
144 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
Dlos_exc.S86 LDR R2, =OS_NVIC_HFSR
87 LDR R2, [R2]
91 TST R2, #0x80000000
97 TST R2, #0x00000002
103 LDR R2, =OS_NVIC_FSR
104 LDR R2, [R2]
106 TST R2, #0x8000 // BFARVALID
109 TST R2, #0x80 // MMARVALID
142 CLZ R2, R2
144 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/secure/
Dlos_secure_context_asm.S48 MOV R2, #0xFFFF
49 LSL R2, R2, #16
50 BIC R1, R1, R2
51 MOV R2, #0x05FA
52 LSL R2, R2, #16
53 ORR R1, R1, R2
56 MOV R2, #0x4000
57 ORR R1, R1, R2
71 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
72 MSR PSPLIM, R2 /* Restore PSPLIM. */
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/secure/
Dlos_secure_context_asm.S48 MOV R2, #0xFFFF
49 LSL R2, R2, #16
50 BIC R1, R1, R2
51 MOV R2, #0x05FA
52 LSL R2, R2, #16
53 ORR R1, R1, R2
56 MOV R2, #0x4000
57 ORR R1, R1, R2
71 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
72 MSR PSPLIM, R2 /* Restore PSPLIM. */
/kernel/liteos_m/arch/arm/cortex-m4/iar/
Dlos_exc.S74 LDR R2, =OS_NVIC_HFSR
75 LDR R2, [R2]
79 TST R2, #0x80000000
85 TST R2, #0x00000002
91 LDR R2, =OS_NVIC_FSR
92 LDR R2, [R2]
94 TST R2, #0x8000 ; BFARVALID
97 TST R2, #0x80 ; MMARVALID
115 CLZ R2, R2
117 ADD R3, R3, R2
[all …]
/kernel/liteos_m/arch/arm/cortex-m3/keil/
Dlos_exc.S74 LDR R2, =OS_NVIC_HFSR
75 LDR R2, [R2]
79 TST R2, #0x80000000
85 TST R2, #0x00000002
91 LDR R2, =OS_NVIC_FSR
92 LDR R2, [R2]
94 TST R2, #0x8000 ; BFARVALID
97 TST R2, #0x80 ; MMARVALID
115 CLZ R2, R2
117 ADD R3, R3, R2
[all …]
/kernel/uniproton/src/arch/cpu/armv7-m/cortex-m4/
Dprt_hw_exc.S107 LDR R2, =OS_NVIC_HFSR
108 LDR R2, [R2]
113 TST R2, #0x80000000
120 TST R2, #0x00000002 @ bit1 indicates the fault of VECTBL
126 LDR R2, =OS_NVIC_FSR
127 LDR R2, [R2]
129 TST R2, #0x8000 @ BFARVALID
132 TST R2, #0x80 @ MMARVALID
151 AND R2, R3
152 …CLZ R2, R2 @ NO_BMU_FAULT,when hard fault happen, no BMU fault(CFSR(R2) = 0, CLZ R2, R…
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/secure/
Dlos_secure_context_asm.S50 MOV R2, #0xFFFF
51 LSL R2, R2, #16
52 BIC R1, R1, R2
53 MOV R2, #0x05FA
54 LSL R2, R2, #16
55 ORR R1, R1, R2
58 MOV R2, #0x4000
59 ORR R1, R1, R2
78 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
79 MSR PSPLIM, R2 /* Restore PSPLIM. */
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/secure/
Dlos_secure_context_asm.S50 MOV R2, #0xFFFF
51 LSL R2, R2, #16
52 BIC R1, R1, R2
53 MOV R2, #0x05FA
54 LSL R2, R2, #16
55 ORR R1, R1, R2
58 MOV R2, #0x4000
59 ORR R1, R1, R2
78 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
79 MSR PSPLIM, R2 /* Restore PSPLIM. */
/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S39 #define R2 %rcx macro
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
231 encrypt_round(R2,R3,R0,R1,5*8);
232 encrypt_round(R0,R1,R2,R3,6*8);
233 encrypt_round(R2,R3,R0,R1,7*8);
234 encrypt_round(R0,R1,R2,R3,8*8);
[all …]
Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/kernel/linux/linux-5.10/lib/
Dtest_bpf.c41 #define R2 BPF_REG_2 macro
1111 BPF_ALU64_IMM(BPF_MOV, R2, 3),
1112 BPF_ALU64_REG(BPF_SUB, R1, R2),
1127 BPF_ALU64_IMM(BPF_MOV, R2, 3),
1128 BPF_ALU64_REG(BPF_MUL, R1, R2),
1143 BPF_ALU32_IMM(BPF_MOV, R2, 3),
1144 BPF_ALU64_REG(BPF_MUL, R1, R2),
1160 BPF_ALU32_IMM(BPF_MOV, R2, 3),
1161 BPF_ALU32_REG(BPF_MUL, R1, R2),
1181 BPF_ALU64_IMM(BPF_MOV, R2, 2),
[all …]
/kernel/liteos_a/arch/arm/arm/src/
Dlos_hw_runstop.S49 PUSH {R2}
50 LDR R2, =g_saveAR
51 STR R0, [R2]
52 STR R1, [R2, #4]
53 POP {R2}
106 PUSH {R2}
107 LDR R2, =g_saveAR
108 STR R0, [R2]
109 STR R1, [R2, #4]
110 POP {R2}
Dlos_hw_exc.S107 MRS R2, SPSR
110 ORR R2, R2, #(CPSR_INT_DISABLE)
111 MSR CPSR_c, R2
165 ORR R2, R3, #0X80000000
166 STR R2, [R1]
181 MOV R2, #0
183 …STMFD SP!, {R2-R3} @ far and fsr fields, are 0 under this a…
263 MRC P15, 0, R2, C6, C0, 2
265 STMFD SP!, {R2-R3} @ Save far and fsr
305 MRC P15, 0, R2, C6, C0, 0
[all …]
/kernel/linux/linux-5.10/arch/arm/crypto/
Dpoly1305-armv4.pl495 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
535 vdup.32 $R2,r4
556 vmull.u32 $D2,$R2,${R0}[1]
563 vmlal.u32 $D3,$R2,${R1}[1]
568 vmlal.u32 $D3,$R1,${R2}[1]
569 vmlal.u32 $D2,$R0,${R2}[1]
570 vmlal.u32 $D4,$R2,${R2}[1]
572 vmlal.u32 $D0,$R2,${S3}[1]
580 vmlal.u32 $D1,$R2,${S4}[1]
609 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
[all …]

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