Searched refs:TOP (Results 1 – 17 of 17) sorted by relevance
12 DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)38 'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
251 u16 TOP; /* Value: take over point */ member1678 u16 TOP, /* 0: Dual AGC; Value: take over point */ in MXL5005_TunerConfig() argument1702 state->TOP = TOP; in MXL5005_TunerConfig()1827 if (state->TOP == 55) /* TOP == 5.5 */ in MXL_BlockInit()1830 if (state->TOP == 72) /* TOP == 7.2 */ in MXL_BlockInit()1833 if (state->TOP == 92) /* TOP == 9.2 */ in MXL_BlockInit()1836 if (state->TOP == 110) /* TOP == 11.0 */ in MXL_BlockInit()1839 if (state->TOP == 129) /* TOP == 12.9 */ in MXL_BlockInit()1842 if (state->TOP == 147) /* TOP == 14.7 */ in MXL_BlockInit()1845 if (state->TOP == 168) /* TOP == 16.8 */ in MXL_BlockInit()[all …]
80 modules are power gated, except the TOP modules
78 TCON TOP is responsible for configuring display pipeline for
118 label = "TOP-LEFT";123 label = "TOP-RIGHT";
67 * flash. TODO: once the flash part TOP/BOTTOM detection
88 * flash. TODO: once the flash part TOP/BOTTOM detection
107 * flash. TODO: once the flash part TOP/BOTTOM detection
72 #define ETH_RSS_HASH_TOP __ETH_RSS_HASH(TOP)
637 #define COND_SEL(CODE, TOP, FOP) \ in bpf_jit_compile() argument639 t_op = TOP; \ in bpf_jit_compile()
177 /* BOARD-SPECIFIC TOP LEVEL NODES */
116 /* BOARD-SPECIFIC TOP LEVEL NODES */
386 SET Y=0 AT TOP
2706 _(TOP , device->top , &device->top->subdev); in nvkm_device_subdev()
6242 + * We use a TOP reset signal because the APB reset signal6243 + * is handled by the TOP control registers.
40447 + BOTTOM/TOP bit is setted to BOTTOM, it means the lock area starts
331359 + BOTTOM/TOP bit is setted to BOTTOM, it means the lock area starts