| /kernel/linux/linux-5.10/crypto/ |
| D | simd.c | 237 struct simd_skcipher_alg *simd; in simd_register_skciphers_compat() local
249 simd = simd_skcipher_create_compat(algname, drvname, basename); in simd_register_skciphers_compat()
250 err = PTR_ERR(simd); in simd_register_skciphers_compat()
251 if (IS_ERR(simd)) in simd_register_skciphers_compat()
253 simd_algs[i] = simd; in simd_register_skciphers_compat()
484 struct simd_aead_alg *simd; in simd_register_aeads_compat() local
496 simd = simd_aead_create_compat(algname, drvname, basename); in simd_register_aeads_compat()
497 err = PTR_ERR(simd); in simd_register_aeads_compat()
498 if (IS_ERR(simd)) in simd_register_aeads_compat()
500 simd_algs[i] = simd; in simd_register_aeads_compat()
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| D | Makefile | 204 crypto_simd-y := simd.o
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| /kernel/linux/linux-5.10/arch/arm/crypto/ |
| D | aes-neonbs-glue.c | 525 struct simd_skcipher_alg *simd; in aes_init() local
546 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
547 err = PTR_ERR(simd); in aes_init()
548 if (IS_ERR(simd)) in aes_init()
551 aes_simd_algs[i] = simd; in aes_init()
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| D | aes-ce-glue.c | 696 struct simd_skcipher_alg *simd; in aes_init() local
714 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
715 err = PTR_ERR(simd); in aes_init()
716 if (IS_ERR(simd)) in aes_init()
719 aes_simd_algs[i] = simd; in aes_init()
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| /kernel/linux/linux-5.10/arch/arm64/crypto/ |
| D | aes-neonbs-glue.c | 530 struct simd_skcipher_alg *simd; in aes_init() local
551 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
552 err = PTR_ERR(simd); in aes_init()
553 if (IS_ERR(simd)) in aes_init()
556 aes_simd_algs[i] = simd; in aes_init()
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| D | aes-glue.c | 1012 struct simd_skcipher_alg *simd; in aes_init() local
1034 simd = simd_skcipher_create_compat(algname, drvname, basename); in aes_init()
1035 err = PTR_ERR(simd); in aes_init()
1036 if (IS_ERR(simd)) in aes_init()
1039 aes_simd_algs[i] = simd; in aes_init()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2982 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2986 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2992 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2998 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
3007 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v6_0_read_wave_data() argument
3011 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
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| D | amdgpu_gfx.h | 206 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
208 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
211 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
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| D | gfx_v7_0.c | 4149 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4153 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4159 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4165 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4174 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4178 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4179 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4180 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4181 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4182 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
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| D | amdgpu_debugfs.c | 868 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
879 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
899 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
960 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
971 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
993 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
996 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
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| D | gfx_v8_0.c | 5228 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5232 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5238 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5244 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5253 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v8_0_read_wave_data() argument
5257 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5258 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5259 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5260 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5261 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
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| D | gfx_v9_0.c | 2013 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2017 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2023 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2029 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2038 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v9_0_read_wave_data() argument
2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
2043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
2044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
2045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
2046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
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| D | gfx_v10_0.c | 4164 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument
4169 WARN_ON(simd != 0); in gfx_v10_0_read_wave_data()
4190 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4194 WARN_ON(simd != 0); in gfx_v10_0_read_wave_sgprs()
4201 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | Kbuild | 53 mandatory-y += simd.h
|