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Searched refs:Opcode (Results 1 – 25 of 573) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt() argument
212 Opcode |= Rs << 21; in emitRsRt()
213 Opcode |= Rt << 16; in emitRsRt()
215 emitInst(Opcode); in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16() argument
224 Opcode |= Rs << 21; in emitRtRsImm16()
225 Opcode |= Rt << 16; in emitRtRsImm16()
226 Opcode |= Imm & 0xffff; in emitRtRsImm16()
228 emitInst(Opcode); in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel() argument
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DIceInstMIPS32.h297 void dumpOpcode(Ostream &Str, const char *Opcode, Type Ty) const { in dumpOpcode() argument
298 Str << Opcode << "." << Ty; in dumpOpcode()
305 static void emitUnaryopGPR(const char *Opcode, const InstMIPS32 *Inst,
307 static void emitUnaryopGPRFLoHi(const char *Opcode, const InstMIPS32 *Inst,
309 static void emitUnaryopGPRTLoHi(const char *Opcode, const InstMIPS32 *Inst,
311 static void emitTwoAddr(const char *Opcode, const InstMIPS32 *Inst,
313 static void emitThreeAddr(const char *Opcode, const InstMIPS32 *Inst,
315 static void emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst,
370 emitUnaryopGPR(Opcode, this, Func); in emit()
380 dumpOpcode(Str, Opcode, getDest()->getType()); in dump()
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DIceInstARM32.h483 static void emitThreeAddrFP(const char *Opcode, FPSign Sign,
486 static void emitFourAddrFP(const char *Opcode, FPSign Sign,
522 void dumpOpcodePred(Ostream &Str, const char *Opcode, Type Ty) const;
525 static void emitUnaryopGPR(const char *Opcode, const InstARM32Pred *Instr,
527 static void emitUnaryopFP(const char *Opcode, FPSign Sign,
529 static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Instr,
531 static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Instr,
533 static void emitFourAddr(const char *Opcode, const InstARM32Pred *Instr,
535 static void emitCmpLike(const char *Opcode, const InstARM32Pred *Instr,
564 emitUnaryopGPR(Opcode, this, Func, NeedsWidthSuffix); in emit()
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_opcodes.c37 .Opcode = RC_OPCODE_NOP,
41 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
45 .Opcode = RC_OPCODE_ADD,
52 .Opcode = RC_OPCODE_ARL,
58 .Opcode = RC_OPCODE_ARR,
64 .Opcode = RC_OPCODE_CEIL,
71 .Opcode = RC_OPCODE_CMP,
78 .Opcode = RC_OPCODE_CND,
85 .Opcode = RC_OPCODE_COS,
92 .Opcode = RC_OPCODE_DDX,
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Dradeon_program_tex.c67 inst_mov->U.I.Opcode = RC_OPCODE_MUL; in scale_texcoords()
89 inst_rcp->U.I.Opcode = RC_OPCODE_RCP; in projective_divide()
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
109 inst->U.I.Opcode = RC_OPCODE_TEX; in projective_divide()
132 if (inst->U.I.Opcode != RC_OPCODE_TEX && in radeonTransformTEX()
133 inst->U.I.Opcode != RC_OPCODE_TXB && in radeonTransformTEX()
134 inst->U.I.Opcode != RC_OPCODE_TXP && in radeonTransformTEX()
135 inst->U.I.Opcode != RC_OPCODE_TXD && in radeonTransformTEX()
136 inst->U.I.Opcode != RC_OPCODE_TXL && in radeonTransformTEX()
137 inst->U.I.Opcode != RC_OPCODE_KIL) in radeonTransformTEX()
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/third_party/spirv-tools/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int argument
101 type OpcodeMap map[string]*Opcode
975 OpNop = &Opcode {
978 Opcode: 0,
982 OpUndef = &Opcode {
985 Opcode: 1,
999 OpSourceContinued = &Opcode {
1002 Opcode: 2,
1011 OpSource = &Opcode {
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/third_party/skia/third_party/externals/spirv-tools/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int member
101 type OpcodeMap map[string]*Opcode
952 OpNop = &Opcode {
955 Opcode: 0,
959 OpUndef = &Opcode {
962 Opcode: 1,
976 OpSourceContinued = &Opcode {
979 Opcode: 2,
988 OpSource = &Opcode {
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/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/utils/vscode/src/schema/
Dschema.go21 type Opcode struct { struct
24 Opcode int member
101 type OpcodeMap map[string]*Opcode
952 OpNop = &Opcode {
955 Opcode: 0,
959 OpUndef = &Opcode {
962 Opcode: 1,
976 OpSourceContinued = &Opcode {
979 Opcode: 2,
988 OpSource = &Opcode {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDisassemblerTables.inc65 /* 16 */ MCD::OPC_Decode, 133, 3, 0, // Opcode: ATTN
67 /* 25 */ MCD::OPC_Decode, 168, 13, 1, // Opcode: TDI
69 /* 34 */ MCD::OPC_Decode, 189, 13, 2, // Opcode: TWI
75 /* 59 */ MCD::OPC_Decode, 204, 13, 3, // Opcode: VADDUBM
77 /* 68 */ MCD::OPC_Decode, 207, 13, 3, // Opcode: VADDUHM
79 /* 77 */ MCD::OPC_Decode, 210, 13, 3, // Opcode: VADDUWM
81 /* 86 */ MCD::OPC_Decode, 206, 13, 3, // Opcode: VADDUDM
83 /* 95 */ MCD::OPC_Decode, 209, 13, 3, // Opcode: VADDUQM
85 /* 104 */ MCD::OPC_Decode, 196, 13, 3, // Opcode: VADDCUQ
87 /* 113 */ MCD::OPC_Decode, 197, 13, 3, // Opcode: VADDCUW
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenDisassemblerTables.inc66 /* 22 */ MCD::OPC_Decode, 240, 36, 0, // Opcode: UDF
81 /* 84 */ MCD::OPC_Decode, 142, 2, 1, // Opcode: ADD_ZPmZ_B
84 /* 98 */ MCD::OPC_Decode, 144, 2, 1, // Opcode: ADD_ZPmZ_H
89 /* 120 */ MCD::OPC_Decode, 229, 34, 1, // Opcode: SUB_ZPmZ_B
92 /* 134 */ MCD::OPC_Decode, 231, 34, 1, // Opcode: SUB_ZPmZ_H
97 /* 156 */ MCD::OPC_Decode, 203, 34, 1, // Opcode: SUBR_ZPmZ_B
100 /* 170 */ MCD::OPC_Decode, 205, 34, 1, // Opcode: SUBR_ZPmZ_H
105 /* 192 */ MCD::OPC_Decode, 150, 26, 1, // Opcode: SMAX_ZPmZ_B
108 /* 206 */ MCD::OPC_Decode, 152, 26, 1, // Opcode: SMAX_ZPmZ_H
113 /* 228 */ MCD::OPC_Decode, 175, 37, 1, // Opcode: UMAX_ZPmZ_B
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h66 static BranchPredicate getBranchPredicate(unsigned Opcode);
95 unsigned Opcode) const;
99 unsigned Opcode) const;
102 MachineInstr &Inst, unsigned Opcode) const;
108 unsigned Opcode,
337 bool isSALU(uint16_t Opcode) const { in isSALU() argument
338 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
345 bool isVALU(uint16_t Opcode) const { in isVALU() argument
346 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
353 bool isVMEM(uint16_t Opcode) const { in isVMEM() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDisassemblerTables.inc65 /* 13 */ MCD::OPC_Decode, 180, 7, 0, // Opcode: Bimm16
68 /* 27 */ MCD::OPC_Decode, 178, 7, 1, // Opcode: BeqzRxImm16
71 /* 41 */ MCD::OPC_Decode, 182, 7, 1, // Opcode: BnezRxImm16
74 /* 55 */ MCD::OPC_Decode, 241, 5, 2, // Opcode: AddiuRxRxImm16
77 /* 69 */ MCD::OPC_Decode, 216, 20, 1, // Opcode: SltiRxImm16
80 /* 83 */ MCD::OPC_Decode, 218, 20, 1, // Opcode: SltiuRxImm16
85 /* 105 */ MCD::OPC_Decode, 185, 7, 0, // Opcode: Bteqz16
88 /* 119 */ MCD::OPC_Decode, 187, 7, 0, // Opcode: Btnez16
91 /* 133 */ MCD::OPC_Decode, 244, 5, 0, // Opcode: AddiuSpImm16
94 /* 147 */ MCD::OPC_Decode, 224, 16, 3, // Opcode: Move32R16
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDisassemblerTables.inc74 /* 52 */ MCD::OPC_Decode, 232, 4, 0, // Opcode: ANDrr
76 /* 61 */ MCD::OPC_Decode, 233, 4, 1, // Opcode: ANDrsi
80 /* 82 */ MCD::OPC_Decode, 158, 14, 0, // Opcode: SUBrr
82 /* 91 */ MCD::OPC_Decode, 159, 14, 1, // Opcode: SUBrsi
86 /* 112 */ MCD::OPC_Decode, 223, 4, 0, // Opcode: ADDrr
88 /* 121 */ MCD::OPC_Decode, 224, 4, 1, // Opcode: ADDrsi
92 /* 142 */ MCD::OPC_Decode, 152, 13, 0, // Opcode: SBCrr
94 /* 151 */ MCD::OPC_Decode, 153, 13, 1, // Opcode: SBCrsi
101 /* 181 */ MCD::OPC_Decode, 234, 4, 2, // Opcode: ANDrsr
104 /* 195 */ MCD::OPC_Decode, 160, 14, 2, // Opcode: SUBrsr
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp65 int SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
78 switch (Opcode) { in getIntImmCostInst()
351 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost() argument
373 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
375 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
402 if (Opcode == Instruction::Shl || Opcode == Instruction::LShr || in getArithmeticInstrCost()
403 Opcode == Instruction::AShr) { in getArithmeticInstrCost()
422 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
423 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) { in getArithmeticInstrCost()
432 getArithmeticInstrCost(Opcode, Ty->getScalarType()); in getArithmeticInstrCost()
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DSystemZInstrInfo.cpp178 unsigned Opcode = getOpcodeForOffset( in expandRXYPseudo() local
181 MI.setDesc(get(Opcode)); in expandRXYPseudo()
190 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; in expandLOCPseudo() local
191 MI.setDesc(get(Opcode)); in expandLOCPseudo()
252 unsigned Opcode; in emitGRX32Move() local
256 Opcode = SystemZ::RISBHH; in emitGRX32Move()
258 Opcode = SystemZ::RISBHL; in emitGRX32Move()
260 Opcode = SystemZ::RISBLH; in emitGRX32Move()
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
673 unsigned Opcode = MI.getOpcode(); in isPredicable() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp121 int PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
124 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty); in getIntImmCostInst()
135 switch (Opcode) { in getIntImmCostInst()
276 unsigned Opcode = 0; in mightUseCTR() local
311 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
312 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
313 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
314 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR()
315 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
316 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in mightUseCTR()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DInstruction.h148 static inline bool isUnaryOp(unsigned Opcode) {
149 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
151 static inline bool isBinaryOp(unsigned Opcode) {
152 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
155 static inline bool isIntDivRem(unsigned Opcode) {
156 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
160 static inline bool isShift(unsigned Opcode) {
161 return Opcode >= Shl && Opcode <= AShr;
175 static inline bool isBitwiseLogicOp(unsigned Opcode) {
176 return Opcode == And || Opcode == Or || Opcode == Xor;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFMISimplifyPatchable.cpp68 unsigned Opcode);
106 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
108 if (Opcode == BPF::LDB || Opcode == BPF::LDH || Opcode == BPF::LDW || in checkADDrr()
109 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || in checkADDrr()
110 Opcode == BPF::STW || Opcode == BPF::STD) in checkADDrr()
112 else if (Opcode == BPF::LDB32 || Opcode == BPF::LDH32 || in checkADDrr()
113 Opcode == BPF::LDW32 || Opcode == BPF::STB32 || in checkADDrr()
114 Opcode == BPF::STH32 || Opcode == BPF::STW32) in checkADDrr()
125 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr()
133 unsigned Opcode) { in checkShift() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp132 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
142 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument
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DX86TargetTransformInfo.h123 unsigned Opcode, Type *Ty,
131 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
133 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
135 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
136 int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
138 int getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
140 int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr,
154 int getArithmeticReductionCost(unsigned Opcode, Type *Ty,
160 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
165 int getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonTargetTransformInfo.cpp154 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost() argument
158 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getMemoryOpCost()
159 if (Opcode == Instruction::Store) in getMemoryOpCost()
160 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); in getMemoryOpCost()
198 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I); in getMemoryOpCost()
201 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, in getMaskedMemoryOpCost() argument
203 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace); in getMaskedMemoryOpCost()
211 unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy, in getGatherScatterOpCost() argument
213 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost()
217 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, in getInterleavedMemoryOpCost() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp174 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
180 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
217 unsigned Opcode = MI.getOpcode(); in getMemoryOpOffset() local
218 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
222 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
223 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
224 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
225 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
229 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
230 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerInfo.cpp85 OS << Opcode << ", Tys={"; in print()
91 OS << Opcode << ", MMOs={"; in print()
290 const unsigned Opcode = FirstOp + OpcodeIdx; in computeTables() local
326 setScalarAction(Opcode, TypeIdx, S(ScalarSpecifiedActions)); in computeTables()
336 Opcode, TypeIdx, PointerSpecifiedActions.first, in computeTables()
358 Opcode, TypeIdx, ElementSize, in computeTables()
369 Opcode, TypeIdx, VectorElementSizeChangeStrategy(ElementSizesSeen)); in computeTables()
404 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
405 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
406 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMUnwindOpAsm.h72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
73 Ops.push_back(Opcode & 0xff); in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
79 Ops.push_back(Opcode & 0xff); in EmitInt16()
83 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes() argument
84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in EmitBytes()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/DebugInfo/DWARF/
DDWARFDebugFrame.cpp40 uint8_t Opcode = Data.getRelocatedValue(1, Offset); in parse() local
42 uint8_t Primary = Opcode & DWARF_CFI_PRIMARY_OPCODE_MASK; in parse()
47 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK; in parse()
63 switch (Opcode) { in parse()
67 Opcode); in parse()
73 addInstruction(Opcode); in parse()
77 addInstruction(Opcode, Data.getRelocatedAddress(Offset)); in parse()
81 addInstruction(Opcode, Data.getRelocatedValue(1, Offset)); in parse()
85 addInstruction(Opcode, Data.getRelocatedValue(2, Offset)); in parse()
89 addInstruction(Opcode, Data.getRelocatedValue(4, Offset)); in parse()
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