| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 99 const TargetRegisterClass *getPointerRegClass(
126 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
129 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
139 const TargetRegisterClass *RC; in isSGPRReg()
148 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass()
153 bool hasVGPRs(const TargetRegisterClass *RC) const;
156 bool hasAGPRs(const TargetRegisterClass *RC) const;
159 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters()
164 const TargetRegisterClass *getEquivalentVGPRClass(
165 const TargetRegisterClass *SRC) const;
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| D | SIFixSGPRCopies.cpp | 167 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
174 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg) in getCopyRegClasses()
181 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg) in getCopyRegClasses()
188 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy()
189 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy()
195 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy()
196 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy()
261 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence()
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
297 const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC); in foldVGPRCopyIntoRegSequence()
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| D | SIRegisterInfo.cpp | 424 const TargetRegisterClass *SIRegisterInfo::getPointerRegClass( in getPointerRegClass()
637 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
775 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in spillSGPR()
880 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in restoreSGPR()
1233 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { in getPhysRegClass()
1236 static const TargetRegisterClass *const BaseClasses[] = { in getPhysRegClass()
1263 for (const TargetRegisterClass *BaseClass : BaseClasses) { in getPhysRegClass()
1273 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs()
1300 bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const { in hasAGPRs()
1325 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass( in getEquivalentVGPRClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 44 class TargetRegisterClass {
48 using sc_iterator = const TargetRegisterClass* const *;
118 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
130 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
230 using regclass_iterator = const TargetRegisterClass * const *;
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
277 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
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| D | RegisterClassInfo.h | 70 void compute(const TargetRegisterClass *RC) const;
73 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
106 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
122 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
130 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
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| D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
125 BitVector getRegsAvailable(const TargetRegisterClass *RC);
129 Register FindUnusedReg(const TargetRegisterClass *RC) const;
163 Register scavengeRegister(const TargetRegisterClass *RC,
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
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| D | LiveStacks.h | 28 class TargetRegisterClass; variable
43 std::map<int, const TargetRegisterClass *> S2RCMap;
62 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
80 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
82 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
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| D | FastISel.h | 57 class TargetRegisterClass; variable
393 const TargetRegisterClass *RC);
398 const TargetRegisterClass *RC, unsigned Op0,
404 const TargetRegisterClass *RC, unsigned Op0,
410 const TargetRegisterClass *RC, unsigned Op0,
417 const TargetRegisterClass *RC, unsigned Op0,
423 const TargetRegisterClass *RC, unsigned Op0,
429 const TargetRegisterClass *RC,
435 const TargetRegisterClass *RC, unsigned Op0,
442 const TargetRegisterClass *RC, uint64_t Imm);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 64 const TargetRegisterClass *
65 getMatchingSuperRegClass(const TargetRegisterClass *A,
66 const TargetRegisterClass *B,
69 const TargetRegisterClass *
70 getSubClassWithSubReg(const TargetRegisterClass *RC,
73 const TargetRegisterClass *
74 getLargestLegalSuperClass(const TargetRegisterClass *RC,
77 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
79 const TargetRegisterClass *SrcRC,
84 const TargetRegisterClass *
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| D | X86RegisterInfo.cpp | 86 const TargetRegisterClass *
87 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg()
98 const TargetRegisterClass *
99 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, in getMatchingSuperRegClass()
100 const TargetRegisterClass *B, in getMatchingSuperRegClass()
111 const TargetRegisterClass *
112 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
127 const TargetRegisterClass *Super = RC; in getLargestLegalSuperClass()
128 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
178 const TargetRegisterClass *
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 172 const TargetRegisterClass *
173 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
179 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
189 const TargetRegisterClass *
196 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
197 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
210 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
218 const TargetRegisterClass *RC) const { in getAllocatableSet()
222 const TargetRegisterClass *SubClass = getAllocatableClass(RC); in getAllocatableSet()
226 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
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| D | CriticalAntiDepBreaker.cpp | 76 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
94 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
124 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
131 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
192 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
202 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
211 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
212 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
217 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) in PrescanInstruction()
231 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) { in PrescanInstruction()
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| D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass()
68 static const TargetRegisterClass *
70 const TargetRegisterClass *OldRC, in constrainRegClass()
71 const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
74 const TargetRegisterClass *NewRC = in constrainRegClass()
84 const TargetRegisterClass *
86 const TargetRegisterClass *RC, in constrainRegClass()
105 else if (RegCB.is<const TargetRegisterClass *>() != in constrainRegAttrs()
106 ConstrainingRegCB.is<const TargetRegisterClass *>()) in constrainRegAttrs()
108 else if (RegCB.is<const TargetRegisterClass *>()) { in constrainRegAttrs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
59 const TargetRegisterClass *SrcRC,
61 const TargetRegisterClass *DstRC,
63 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 63 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
64 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
65 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
73 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
77 const TargetRegisterClass *RC) const;
81 const TargetRegisterClass *
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| D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
113 const TargetRegisterClass *RC);
116 const TargetRegisterClass *RC);
121 const TargetRegisterClass *RC);
124 const TargetRegisterClass *RC);
136 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 139 const TargetRegisterClass *
142 const TargetRegisterClass *
143 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
145 const TargetRegisterClass *
146 getLargestLegalSuperClass(const TargetRegisterClass *RC,
149 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
207 const TargetRegisterClass *SrcRC,
209 const TargetRegisterClass *DstRC,
211 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
59 const TargetRegisterClass *
60 getSubClassWithSubReg(const TargetRegisterClass *RC,
88 const TargetRegisterClass *
91 const TargetRegisterClass *
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
118 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.h | 49 const TargetRegisterClass *
58 const TargetRegisterClass *
59 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
88 const TargetRegisterClass *SrcRC,
90 const TargetRegisterClass *DstRC,
92 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 4319 …const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const overr…
4320 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4325 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4335 extern const TargetRegisterClass GR8RegClass;
4336 extern const TargetRegisterClass GRH8RegClass;
4337 extern const TargetRegisterClass GR8_NOREXRegClass;
4338 extern const TargetRegisterClass GR8_ABCD_HRegClass;
4339 extern const TargetRegisterClass GR8_ABCD_LRegClass;
4340 extern const TargetRegisterClass GRH16RegClass;
4341 extern const TargetRegisterClass GR16RegClass;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 3813 …const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const overr…
3814 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3819 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3829 extern const TargetRegisterClass MSA128F16RegClass;
3830 extern const TargetRegisterClass CCRRegClass;
3831 extern const TargetRegisterClass COP0RegClass;
3832 extern const TargetRegisterClass COP2RegClass;
3833 extern const TargetRegisterClass COP3RegClass;
3834 extern const TargetRegisterClass DSPRRegClass;
3835 extern const TargetRegisterClass FGR32RegClass;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
75 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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| D | MipsInstrInfo.h | 38 class TargetRegisterClass; variable
115 const TargetRegisterClass *RC, in storeRegToStackSlot()
123 const TargetRegisterClass *RC, in loadRegFromStackSlot()
131 const TargetRegisterClass *RC,
138 const TargetRegisterClass *RC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 3585 …const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const overr…
3586 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3591 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3601 extern const TargetRegisterClass HPRRegClass;
3602 extern const TargetRegisterClass FPWithVPRRegClass;
3603 extern const TargetRegisterClass SPRRegClass;
3604 extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass;
3605 extern const TargetRegisterClass GPRRegClass;
3606 extern const TargetRegisterClass GPRwithAPSRRegClass;
3607 extern const TargetRegisterClass GPRwithZRRegClass;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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