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Searched refs:dpp_ctrl (Results 1 – 18 of 18) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_print_ir.cpp575 if (dpp.dpp_ctrl <= 0xff) { in print_instr_format_specific()
576 fprintf(output, " quad_perm:[%d,%d,%d,%d]", dpp.dpp_ctrl & 0x3, (dpp.dpp_ctrl >> 2) & 0x3, in print_instr_format_specific()
577 (dpp.dpp_ctrl >> 4) & 0x3, (dpp.dpp_ctrl >> 6) & 0x3); in print_instr_format_specific()
578 } else if (dpp.dpp_ctrl >= 0x101 && dpp.dpp_ctrl <= 0x10f) { in print_instr_format_specific()
579 fprintf(output, " row_shl:%d", dpp.dpp_ctrl & 0xf); in print_instr_format_specific()
580 } else if (dpp.dpp_ctrl >= 0x111 && dpp.dpp_ctrl <= 0x11f) { in print_instr_format_specific()
581 fprintf(output, " row_shr:%d", dpp.dpp_ctrl & 0xf); in print_instr_format_specific()
582 } else if (dpp.dpp_ctrl >= 0x121 && dpp.dpp_ctrl <= 0x12f) { in print_instr_format_specific()
583 fprintf(output, " row_ror:%d", dpp.dpp_ctrl & 0xf); in print_instr_format_specific()
584 } else if (dpp.dpp_ctrl == dpp_wf_sl1) { in print_instr_format_specific()
[all …]
Daco_lower_to_hw_instr.cpp200 PhysReg vtmp_reg, ReduceOp op, unsigned dpp_ctrl, unsigned row_mask, in emit_int64_dpp_op() argument
215 bld.vop1_dpp(aco_opcode::v_mov_b32, vtmp_def[0], src0[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
220 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
223 Operand(vcc, bld.lm), dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
235 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
237 bld.vop2_dpp(aco_opcode::v_xor_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
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Daco_optimizer_postRA.cpp464 dpp->dpp_ctrl = mov->dpp16().dpp_ctrl; in try_combine_dpp()
Daco_opt_value_numbering.cpp181 return aDPP.pass_flags == bDPP.pass_flags && aDPP.dpp_ctrl == bDPP.dpp_ctrl && in operator ()()
Daco_instruction_selection.cpp241 uint16_t dpp_ctrl = 0xffff; in emit_masked_swizzle() local
247 dpp_ctrl = dpp_quad_perm(res[0], res[1], res[2], res[3]); in emit_masked_swizzle()
249 dpp_ctrl = dpp_row_rr(8); in emit_masked_swizzle()
251 dpp_ctrl = dpp_row_mirror; in emit_masked_swizzle()
253 dpp_ctrl = dpp_row_half_mirror; in emit_masked_swizzle()
264 if (dpp_ctrl != 0xffff) in emit_masked_swizzle()
265 return bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl); in emit_masked_swizzle()
8841 uint16_t dpp_ctrl = 0; in visit_intrinsic() local
8844 case nir_intrinsic_quad_swap_horizontal: dpp_ctrl = dpp_quad_perm(1, 0, 3, 2); break; in visit_intrinsic()
8845 case nir_intrinsic_quad_swap_vertical: dpp_ctrl = dpp_quad_perm(2, 3, 0, 1); break; in visit_intrinsic()
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Daco_ir.cpp380 dpp->dpp_ctrl = dpp_quad_perm(0, 1, 2, 3); in convert_to_DPP()
Daco_assembler.cpp692 encoding |= dpp.dpp_ctrl << 8; in emit_instruction()
Daco_optimizer.cpp2444 new_dpp->dpp_ctrl = cmp_dpp.dpp_ctrl; in combine_inverse_comparison()
4521 dpp->dpp_ctrl = info.instr->dpp16().dpp_ctrl; in select_instruction()
Daco_ir.h1445 uint16_t dpp_ctrl; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP1Instructions.td290 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
838 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
840 (V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl),
846 (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl, timm:$row_mask,
848 (V_MOV_B32_dpp $old, $src, (as_i32imm $dpp_ctrl),
DVOP2Instructions.td293 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
348 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
362 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
397 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
417 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
DSIInstrInfo.td1082 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1748 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1754 Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1759 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1768 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1773 Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1970 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
DGCNDPPCombine.cpp250 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
DVOPInstructions.td576 bits<9> dpp_ctrl;
583 let Inst{48-40} = dpp_ctrl;
DSIInstructions.td1876 (i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
1878 (V_MOV_B64_DPP_PSEUDO $src, $src, (as_i32imm $dpp_ctrl),
1884 (i64 (int_amdgcn_update_dpp i64:$old, i64:$src, timm:$dpp_ctrl, timm:$row_mask,
1886 (V_MOV_B64_DPP_PSEUDO $old, $src, (as_i32imm $dpp_ctrl),
DSIInstrInfo.cpp3698 const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl); in verifyInstruction()
/third_party/mesa3d/src/amd/llvm/
Dac_llvm_build.c3253 enum dpp_ctrl enum
3269 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm()
3276 static inline enum dpp_ctrl dpp_row_sr(unsigned amount) in dpp_row_sr()
3283 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in _ac_build_dpp() argument
3294 (LLVMValueRef[]){old, src, LLVMConstInt(ctx->i32, dpp_ctrl, 0), in _ac_build_dpp()
3303 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in ac_build_dpp() argument
3321 _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
3326 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td1525 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1532 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1535 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>