| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_opt_uniform_atomics.c | 43 parse_atomic_op(nir_intrinsic_op op, unsigned *offset_src, unsigned *data_src, in parse_atomic_op() argument
49 *offset_src = 1; \ in parse_atomic_op()
51 *offset2_src = *offset_src; \ in parse_atomic_op()
56 *offset_src = 0; \ in parse_atomic_op()
58 *offset2_src = *offset_src; \ in parse_atomic_op()
61 *offset_src = 0; \ in parse_atomic_op()
70 *offset_src = 1; \ in parse_atomic_op()
72 *offset2_src = *offset_src; \ in parse_atomic_op()
211 unsigned offset_src = 0; in optimize_atomic() local
214 nir_op op = parse_atomic_op(intrin->intrinsic, &offset_src, &data_src, &offset2_src); in optimize_atomic()
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| D | nir_gather_ssa_types.c | 209 nir_src *offset_src = nir_get_io_offset_src(intrin); in nir_gather_ssa_types() local
210 if (offset_src) { in nir_gather_ssa_types()
211 assert(offset_src->is_ssa); in nir_gather_ssa_types()
212 set_type(offset_src->ssa->index, nir_type_int, in nir_gather_ssa_types()
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| D | nir_lower_wrmasks.c | 78 offset_src(nir_intrinsic_op intrinsic) in offset_src() function
105 unsigned offset_idx = offset_src(intr->intrinsic); in split_wrmask()
209 assert(offset_src(intr->intrinsic) >= 0); in nir_lower_wrmasks_instr()
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| D | nir_lower_ssbo.c | 115 nir_src *offset_src = nir_get_io_offset_src(intr); in lower_ssbo_instr() local
116 nir_ssa_def *offset = nir_ssa_for_src(b, *offset_src, 1); in lower_ssbo_instr()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_mem_access_bit_sizes.c | 99 nir_src *offset_src = nir_get_io_offset_src(intrin); in lower_mem_load_bit_size() local
100 if (bit_size < 32 && !needs_scalar && nir_src_is_const(*offset_src)) { in lower_mem_load_bit_size()
104 const int load_offset = nir_src_as_uint(*offset_src) % 4; in lower_mem_load_bit_size()
182 nir_src *offset_src = nir_get_io_offset_src(intrin); in lower_mem_store_bit_size() local
183 const bool offset_is_const = nir_src_is_const(*offset_src); in lower_mem_store_bit_size()
185 offset_is_const ? nir_src_as_uint(*offset_src) : 0; in lower_mem_store_bit_size()
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| D | brw_mesh.cpp | 149 nir_src *offset_src = nir_get_io_offset_src(intrin); in brw_nir_adjust_task_payload_offsets_instr() local
151 if (nir_src_is_const(*offset_src)) in brw_nir_adjust_task_payload_offsets_instr()
152 assert(nir_src_as_uint(*offset_src) % 4 == 0); in brw_nir_adjust_task_payload_offsets_instr()
162 assert(offset_src->is_ssa); in brw_nir_adjust_task_payload_offsets_instr()
163 nir_ssa_def *offset = nir_ishr_imm(b, offset_src->ssa, 2); in brw_nir_adjust_task_payload_offsets_instr()
164 nir_instr_rewrite_src(&intrin->instr, offset_src, nir_src_for_ssa(offset)); in brw_nir_adjust_task_payload_offsets_instr()
640 nir_src *offset_src = &intrin->src[is_load ? 1 : 2]; in brw_nir_adjust_offset_for_arrayed_indices_instr() local
646 offset_src->ssa, in brw_nir_adjust_offset_for_arrayed_indices_instr()
648 nir_instr_rewrite_src(&intrin->instr, offset_src, nir_src_for_ssa(offset)); in brw_nir_adjust_offset_for_arrayed_indices_instr()
656 nir_src *offset_src = &intrin->src[is_load ? 1 : 2]; in brw_nir_adjust_offset_for_arrayed_indices_instr() local
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| D | brw_fs_nir.cpp | 2511 const nir_src &offset_src, in emit_gs_input_load() argument
2521 nir_src_is_const(offset_src) && nir_src_is_const(vertex_src) && in emit_gs_input_load()
2522 4 * (base_offset + nir_src_as_uint(offset_src)) < push_reg_count) { in emit_gs_input_load()
2523 int imm_offset = (base_offset + nir_src_as_uint(offset_src)) * 4 + in emit_gs_input_load()
2614 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load()
2616 if (nir_src_is_const(offset_src)) { in emit_gs_input_load()
2638 inst->offset = base_offset + nir_src_as_uint(offset_src); in emit_gs_input_load()
2672 nir_src *offset_src = nir_get_io_offset_src(instr); in get_indirect_offset() local
2674 if (nir_src_is_const(*offset_src)) { in get_indirect_offset()
2679 assert(nir_src_as_uint(*offset_src) == 0); in get_indirect_offset()
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| D | brw_vec4_nir.cpp | 268 nir_src *offset_src = nir_get_io_offset_src(instr); in get_indirect_offset() local
270 if (nir_src_is_const(*offset_src)) { in get_indirect_offset()
275 assert(nir_src_as_uint(*offset_src) == 0); in get_indirect_offset()
279 return get_nir_src(*offset_src, BRW_REGISTER_TYPE_UD, 1); in get_indirect_offset()
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| D | brw_fs.h | 328 unsigned base_offset, const nir_src &offset_src,
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_nir_lower_robust_buffer_access.c | 31 uint32_t offset_src, in rewrite_offset() argument
49 nir_umin(b, instr->src[offset_src].ssa, aligned_buffer_size); in rewrite_offset()
50 nir_instr_rewrite_src(&instr->instr, &instr->src[offset_src], in rewrite_offset()
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| D | v3d_nir_lower_load_store_bitsize.c | 50 offset_src(nir_intrinsic_op intrinsic) in offset_src() function
132 unsigned offset_idx = offset_src(intr->intrinsic); in lower_load_bitsize()
191 unsigned offset_idx = offset_src(intr->intrinsic); in lower_store_bitsize()
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| D | nir_to_vir.c | 448 int offset_src, in emit_tmu_general_address_write() argument
456 ntq_get_src(c, instr->src[offset_src], 0); in emit_tmu_general_address_write()
478 struct qreg data = ntq_get_src(c, instr->src[offset_src], 0); in emit_tmu_general_address_write()
539 int offset_src; in ntq_emit_tmu_general() local
541 offset_src = 0; in ntq_emit_tmu_general()
548 offset_src = 0 + has_index; in ntq_emit_tmu_general()
550 offset_src = 1 + has_index; in ntq_emit_tmu_general()
552 offset_src = 0 + has_index; in ntq_emit_tmu_general()
555 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]); in ntq_emit_tmu_general()
558 const_offset = nir_src_as_uint(instr->src[offset_src]); in ntq_emit_tmu_general()
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_nir_lower_64bit.cpp | 1342 int offset_src = -1; in r600_lower_64bit_intrinsic() local
1348 offset_src = 1; in r600_lower_64bit_intrinsic()
1352 offset_src = 0; in r600_lower_64bit_intrinsic()
1356 offset_src = 2; in r600_lower_64bit_intrinsic()
1361 if (offset_src != -1) { in r600_lower_64bit_intrinsic()
1364 nir_iadd_imm(b, second->src[offset_src].ssa, offset_amount); in r600_lower_64bit_intrinsic()
1365 nir_instr_rewrite_src(&second->instr, &second->src[offset_src], in r600_lower_64bit_intrinsic()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_lower_ngg.c | 2120 nir_ssa_def *offset_src, in ms_store_prim_indices() argument
2125 if (!offset_src) in ms_store_prim_indices()
2126 offset_src = nir_imm_int(b, 0); in ms_store_prim_indices()
2128 nir_store_shared(b, nir_u2u8(b, val), offset_src, .base = s->layout.lds.indices_addr); in ms_store_prim_indices()
2133 nir_ssa_def *offset_src, in ms_load_prim_indices() argument
2136 if (!offset_src) in ms_load_prim_indices()
2137 offset_src = nir_imm_int(b, 0); in ms_load_prim_indices()
2139 return nir_load_shared(b, 1, 8, offset_src, .base = s->layout.lds.indices_addr); in ms_load_prim_indices()
2185 nir_ssa_def *offset_src = nir_get_io_offset_src(intrin)->ssa; in lower_ms_store_output() local
2186 ms_store_prim_indices(b, store_val, offset_src, s); in lower_ms_store_output()
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| /third_party/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 3328 int offset_src = -1; in nir_to_tgsi_lower_64bit_intrinsic() local
3334 offset_src = 1; in nir_to_tgsi_lower_64bit_intrinsic()
3337 offset_src = 1; in nir_to_tgsi_lower_64bit_intrinsic()
3341 offset_src = 2; in nir_to_tgsi_lower_64bit_intrinsic()
3346 if (offset_src != -1) { in nir_to_tgsi_lower_64bit_intrinsic()
3349 nir_iadd_imm(b, second->src[offset_src].ssa, offset_amount); in nir_to_tgsi_lower_64bit_intrinsic()
3350 nir_instr_rewrite_src(&second->instr, &second->src[offset_src], in nir_to_tgsi_lower_64bit_intrinsic()
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| /third_party/mesa3d/src/asahi/compiler/ |
| D | agx_compile.c | 224 nir_src *offset_src = nir_get_io_offset_src(instr); in agx_emit_load_attr() local
225 assert(nir_src_is_const(*offset_src) && "no attribute indirects"); in agx_emit_load_attr()
227 nir_src_as_uint(*offset_src); in agx_emit_load_attr()
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| /third_party/python/Modules/clinic/ |
| D | posixmodule.c.h | 5659 PyObject *offset_src, PyObject *offset_dst);
5672 PyObject *offset_src = Py_None; in os_copy_file_range() local
5703 offset_src = args[3]; in os_copy_file_range()
5710 return_value = os_copy_file_range_impl(module, src, dst, count, offset_src, offset_dst); in os_copy_file_range()
5749 PyObject *offset_src, PyObject *offset_dst,
5763 PyObject *offset_src = Py_None; in os_splice() local
5795 offset_src = args[3]; in os_splice()
5810 return_value = os_splice_impl(module, src, dst, count, offset_src, offset_dst, flags); in os_splice()
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| /third_party/mesa3d/src/compiler/nir/tests/ |
| D | load_store_vectorizer_tests.cpp | 240 int offset_src = res ? 1 : 0; in create_indirect_load() local
242 if (nir_src_is_const(load->src[offset_src])) { in create_indirect_load()
243 nir_intrinsic_set_range_base(load, nir_src_as_uint(load->src[offset_src])); in create_indirect_load()
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| /third_party/python/Modules/ |
| D | posixmodule.c | 10409 PyObject *offset_src, PyObject *offset_dst) in os_copy_file_range_impl() argument
10427 if (offset_src != Py_None) { in os_copy_file_range_impl()
10428 if (!Py_off_t_converter(offset_src, &offset_src_val)) { in os_copy_file_range_impl()
10481 PyObject *offset_src, PyObject *offset_dst, in os_splice_impl() argument
10496 if (offset_src != Py_None) { in os_splice_impl()
10497 if (!Py_off_t_converter(offset_src, &offset_src_val)) { in os_splice_impl()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| D | zink_compiler.c | 540 nir_src offset_src = nir_src_for_ssa(offset); in bound_bo_access_instr() local
541 if (!nir_src_is_const(offset_src)) in bound_bo_access_instr()
544 unsigned offset_bytes = nir_src_as_const_value(offset_src)->u32; in bound_bo_access_instr()
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| /third_party/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_vgpu10.c | 8696 struct tgsi_full_src_register offset_src, sampler, ref; in emit_tg4() local
8775 offset_src = make_src_reg(inst->TexOffsets[0].File, in emit_tg4()
8777 offset_src = swizzle_src(&offset_src, inst->TexOffsets[0].SwizzleX, in emit_tg4()
8781 emit_src_register(emit, &offset_src); in emit_tg4()
12393 struct tgsi_full_src_register offset_src = make_src_temp_reg(offset_tmp); in emit_rawbuf_instruction() local
12440 scalar_src(&offset_src, TGSI_SWIZZLE_X); in emit_rawbuf_instruction()
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_nir_to_llvm.c | 4156 LLVMValueRef offset_src = ac_extract_components(&ctx->ac, src, start, count); in visit_intrinsic() local
4157 LLVMBuildStore(ctx->ac.builder, offset_src, offset_ptr); in visit_intrinsic()
4661 unsigned offset_src = 0; in visit_tex() local
4686 offset_src = i; in visit_tex()
4911 int num_offsets = instr->src[offset_src].src.ssa->num_components; in visit_tex()
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| /third_party/python/Doc/library/ |
| D | os.rst | 787 .. function:: copy_file_range(src, dst, count, offset_src=None, offset_dst=None)
790 *offset_src*, to file descriptor *dst*, starting from offset *offset_dst*.
791 If *offset_src* is None, then *src* is read from the current position;
1433 .. function:: splice(src, dst, count, offset_src=None, offset_dst=None)
1436 *offset_src*, to file descriptor *dst*, starting from offset *offset_dst*.
1437 At least one of the file descriptors must refer to a pipe. If *offset_src*
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| /third_party/mesa3d/src/microsoft/compiler/ |
| D | nir_to_dxil.c | 3097 const struct dxil_value *offset_src = get_src(ctx, &intr->src[1], 0, nir_type_uint); in emit_load_ubo() local
3099 if (!offset_src || !c4) in emit_load_ubo()
3102 offset = dxil_emit_binop(&ctx->mod, DXIL_BINOP_ASHR, offset_src, c4, 0); in emit_load_ubo()
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| /third_party/python/Lib/test/ |
| D | test_os.py | 373 offset_src=in_skip,
454 i = os.splice(in_fd, write_fd, bytes_to_copy, offset_src=in_skip)
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