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Searched refs:para (Results 1 – 25 of 310) sorted by relevance

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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/g2d/g2d_legacy/
Dg2d_bsp_sun8iw11.c660 __s32 mixer_fillrectangle(g2d_fillrect *para) in mixer_fillrectangle() argument
670 (para->dst_rect.w - 1) | ((para->dst_rect.h - 1) << 16)); in mixer_fillrectangle()
673 if (para->flag & G2D_FIL_PLANE_ALPHA) in mixer_fillrectangle()
674 reg_val |= (para->alpha << 24) | 0x4; in mixer_fillrectangle()
675 else if (para->flag & G2D_FIL_MULTI_ALPHA) in mixer_fillrectangle()
676 reg_val |= (para->alpha << 24) | 0x8; in mixer_fillrectangle()
679 mixer_set_fillcolor(para->color, 0); in mixer_fillrectangle()
680 if ((para->flag & G2D_FIL_PLANE_ALPHA) in mixer_fillrectangle()
681 || (para->flag & G2D_FIL_PIXEL_ALPHA) in mixer_fillrectangle()
682 || (para->flag & G2D_FIL_MULTI_ALPHA)) { in mixer_fillrectangle()
[all …]
Dg2d_driver.c36 __g2d_info_t para; variable
354 init_para.g2d_base = (unsigned long) para.io; in drv_g2d_init()
372 address = dma_alloc_coherent(para.dev, actual_bytes, in g2d_malloc()
419 dma_free_coherent(para.dev, actual_bytes, virt_addr, in g2d_free()
502 mutex_lock(&para.mutex); in g2d_open()
503 para.user_cnt++; in g2d_open()
504 if (para.user_cnt == 1) { in g2d_open()
505 g2d_clock_enable(&para); in g2d_open()
506 para.opened = true; in g2d_open()
512 mutex_unlock(&para.mutex); in g2d_open()
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Dg2d_bsp_v2.c444 __s32 ck_para_set(g2d_ck *para) in ck_para_set() argument
448 if (para->match_rule) in ck_para_set()
451 write_wvalue(BLD_KEY_MAX, para->max_color & 0x00ffffff); in ck_para_set()
452 write_wvalue(BLD_KEY_MIN, para->min_color & 0x00ffffff); in ck_para_set()
1396 __s32 mixer_fillrectangle(g2d_fillrect *para) in mixer_fillrectangle() argument
1404 if (para->flag == G2D_FIL_NONE) { in mixer_fillrectangle()
1407 dst->color = para->color; in mixer_fillrectangle()
1409 g2d_format_trans(para->dst_image.format, in mixer_fillrectangle()
1410 para->dst_image.pixel_seq); in mixer_fillrectangle()
1411 dst->laddr[0] = para->dst_image.addr[0]; in mixer_fillrectangle()
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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/
Dde_eink.c273 struct eink_init_param *para) in eink_decoder_start() argument
277 w = para->timing.width ? (para->timing.width - 1) & 0xfff : 0; in eink_decoder_start()
278 h = para->timing.height ? (para->timing.height - 1) & 0xfff : 0; in eink_decoder_start()
282 tmp = para->eink_mode ? (((para->timing.lbl + para->timing.lsl + in eink_decoder_start()
283 para->timing.lel) << 2) + in eink_decoder_start()
284 (para->timing.width >> 1)) : in eink_decoder_start()
285 (((para->timing.lbl + para->timing.lsl + in eink_decoder_start()
286 para->timing.lel) << 1) + in eink_decoder_start()
287 (para->timing.width >> 1)); in eink_decoder_start()
291 tmp = para->eink_mode ? ((para->timing.fbl + para->timing.fsl) * tmp + in eink_decoder_start()
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/device/soc/amlogic/a311d/soc/amlogic/ge2d/
Dge2d_main.c327 struct ge2d_para_s para; in ge2d_ioctl() local
590 ret = copy_from_user(&para, argp, sizeof(struct ge2d_para_s)); in ge2d_ioctl()
637 … ge2d_log_dbg("fill rect...,x=%d,y=%d,w=%d,h=%d,color=0x%x\n", para.src1_rect.x, para.src1_rect.y, in ge2d_ioctl()
638 para.src1_rect.w, para.src1_rect.h, para.color); in ge2d_ioctl()
640 …fillrect(context, para.src1_rect.x, para.src1_rect.y, para.src1_rect.w, para.src1_rect.h, para.col… in ge2d_ioctl()
644 …ge2d_log_dbg("x=%d,y=%d,w=%d,h=%d,color=0x%x\n", para.src1_rect.x, para.src1_rect.y, para.src1_rec… in ge2d_ioctl()
645 para.src1_rect.h, para.color); in ge2d_ioctl()
647 …fillrect_noblk(context, para.src1_rect.x, para.src1_rect.y, para.src1_rect.w, para.src1_rect.h, pa… in ge2d_ioctl()
652 … ge2d_log_dbg("x=%d,y=%d,w=%d,h=%d,dst.w=%d,dst.h=%d\n", para.src1_rect.x, para.src1_rect.y, in ge2d_ioctl()
653 para.src1_rect.w, para.src1_rect.h, para.dst_rect.w, para.dst_rect.h); in ge2d_ioctl()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/secure/
Dcrypto.c426 static hi_u32 crypto_encrypt_data(hi_flash_crypto_content *content, boot_crypto_ctx *para) in crypto_encrypt_data() argument
431 hi_u8 *fw_cyp_data = boot_malloc(para->crypto_total_size); in crypto_encrypt_data()
453 …ret = hi_cipher_aes_crypto((uintptr_t)(para->buf), (uintptr_t)fw_cyp_data, para->crypto_total_size… in crypto_encrypt_data()
458 …ret = g_flash_cmd_funcs.write(para->kernel_addr + para->crypto_start_addr, para->crypto_total_size, in crypto_encrypt_data()
658 hi_u32 encrypt_upg_data(boot_crypto_ctx *para) in encrypt_upg_data() argument
674 …hi_u32 cs = KERNEL_RAM_ADDR ^ CRYPTO_KERNEL_LENGTH ^ (uintptr_t)(para->buf) ^ CRYPTO_KERNEL_LENGTH; in encrypt_upg_data()
675 …ret = memcpy_s((hi_u8 *)KERNEL_RAM_ADDR, CRYPTO_KERNEL_LENGTH, para->buf, CRYPTO_KERNEL_LENGTH, cs… in encrypt_upg_data()
692 ret = crypto_encrypt_data(new_content, para); in encrypt_upg_data()
733 hi_u32 upg_check_encrypt(boot_crypto_ctx *para, hi_u8 *buf, hi_u32 buf_len) in upg_check_encrypt() argument
738 hi_u32 size = para->cryptoed_size + buf_len; in upg_check_encrypt()
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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v3x/
Dde_dns.c289 struct __dns_config_data *para, in de_dns_info2para() argument
294 en = ((para->level == 0) || (bypass == 1)) ? 0 : 1; in de_dns_info2para()
295 para->mod_en = en; /* return enable info */ in de_dns_info2para()
297 if (en == 0 || fmt == 1 || para->inw > 4096 || para->inw < 32) { in de_dns_info2para()
307 dns_para[sel][chno].autolvl = para->level; in de_dns_info2para()
308 dns_para[sel][chno].xst = para->croprect.x & 0x7; in de_dns_info2para()
309 dns_para[sel][chno].yst = para->croprect.y & 0x7; in de_dns_info2para()
310 dns_para[sel][chno].w = para->inw; in de_dns_info2para()
311 dns_para[sel][chno].h = para->inh; in de_dns_info2para()
321 struct __dns_para_t *para) in de_dns_para_apply() argument
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Dde_peak2d.c130 struct __peak2d_config_data *para, in de_peak2d_info2para() argument
141 if ((para->inw < para->outw) && (para->inh < para->outh) && in de_peak2d_info2para()
142 (para->level > 0) && in de_peak2d_info2para()
144 (para->inw <= linebuf) && in de_peak2d_info2para()
155 level = para->level > (PEAK2D_PARA_NUM - 1) ? in de_peak2d_info2para()
156 (PEAK2D_PARA_NUM - 1) : para->level; in de_peak2d_info2para()
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v33x/de330/
Dde_dns.c233 struct __dns_config_data *para, in de_dns_info2para() argument
241 en = ((para->level == 0) || (bypass != 0)) ? 0 : 1; in de_dns_info2para()
242 para->mod_en = en; /* return enable info */ in de_dns_info2para()
244 if (en == 0 || fmt == 1 || para->inw > 4096 || para->inw < 32) { in de_dns_info2para()
254 priv->dns_para.autolvl = para->level; in de_dns_info2para()
255 priv->dns_para.xst = para->croprect.x & 0x7; in de_dns_info2para()
256 priv->dns_para.yst = para->croprect.y & 0x7; in de_dns_info2para()
257 priv->dns_para.w = para->inw; in de_dns_info2para()
258 priv->dns_para.h = para->inh; in de_dns_info2para()
267 struct de_dns_para *para) in de_dns_para_apply() argument
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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-vipp/
Dvipp_reg.c386 void vipp_osd_para_cfg(unsigned int id, struct vipp_osd_para_config *para, in vipp_osd_para_cfg() argument
393 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.h_start = para->overlay_cfg[i].h_start; in vipp_osd_para_cfg()
394 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.h_end = para->overlay_cfg[i].h_end; in vipp_osd_para_cfg()
395 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.v_start = para->overlay_cfg[i].v_start; in vipp_osd_para_cfg()
396 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.v_end = para->overlay_cfg[i].v_end; in vipp_osd_para_cfg()
397 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.alpha = para->overlay_cfg[i].alpha; in vipp_osd_para_cfg()
401 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.h_start = para->cover_cfg[i].h_start; in vipp_osd_para_cfg()
402 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.h_end = para->cover_cfg[i].h_end; in vipp_osd_para_cfg()
403 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.v_start = para->cover_cfg[i].v_start; in vipp_osd_para_cfg()
404 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.v_end = para->cover_cfg[i].v_end; in vipp_osd_para_cfg()
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Dsunxi_scaler.c107 struct scaler_para *para) in __scaler_calc_ratios() argument
117 para->xratio = 256 * input->width / output->width; in __scaler_calc_ratios()
118 para->yratio = 256 * input->height / output->height; in __scaler_calc_ratios()
119 para->xratio = clamp_t(u32, para->xratio, MIN_RATIO, MAX_RATIO); in __scaler_calc_ratios()
120 para->yratio = clamp_t(u32, para->yratio, MIN_RATIO, MAX_RATIO); in __scaler_calc_ratios()
122 r_min = min(para->xratio, para->yratio); in __scaler_calc_ratios()
126 para->xratio = 256 * input->width / width; in __scaler_calc_ratios()
127 para->yratio = 256 * input->height / height; in __scaler_calc_ratios()
128 para->xratio = clamp_t(u32, para->xratio, MIN_RATIO, MAX_RATIO); in __scaler_calc_ratios()
129 para->yratio = clamp_t(u32, para->yratio, MIN_RATIO, MAX_RATIO); in __scaler_calc_ratios()
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/device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/subdev/sensor/src/platform/
Dsystem_am_adap.c56 struct am_adap_info para; variable
748 memset(&para, 0, sizeof(struct am_adap_info)); in am_adap_set_info()
749 memcpy(&para, info, sizeof(struct am_adap_info)); in am_adap_set_info()
758 para.mode = DDR_MODE; in am_adap_set_info()
760 dump_width = para.img.width; in am_adap_set_info()
761 dump_height = para.img.height; in am_adap_set_info()
773 switch (para.fmt) { in am_adap_get_depth()
814 int width = para.img.width; in am_adap_frontend_start()
836 int long_exp_offset = para.offset.long_offset; in am_adap_frontend_init()
837 int short_exp_offset = para.offset.short_offset; in am_adap_frontend_init()
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/device/soc/hpmicro/sdk/hpm_sdk/components/enet_phy/dp83867/
Dhpm_dp83867.c96 uint16_t para = 0; in dp83867_basic_mode_init() local
98 para |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ in dp83867_basic_mode_init()
108 … para |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); in dp83867_basic_mode_init()
149 uint16_t para = 0; in dp83867_set_rx_clk_delay() local
151 para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); in dp83867_set_rx_clk_delay()
152 dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | 1); in dp83867_set_rx_clk_delay()
157 uint16_t para = 0; in dp83867_enable_crc_check() local
159 para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG); in dp83867_enable_crc_check()
160 dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG, para | (1 << 7)); in dp83867_enable_crc_check()
165 uint16_t para = 0; in dp83867_enable_rmii_inf() local
[all …]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/system/upg/
Dkernel_crypto.c373 static hi_u32 crypto_decrypt_kernel(hi_flash_crypto_content *content, encrypt_ctx *para) in crypto_decrypt_kernel() argument
377 hi_u8 *fw_raw_data = para->raw_buf; in crypto_decrypt_kernel()
395 ret = hi_cipher_aes_crypto(para->kernel_start + para->encrypt_offset + SFC_BUFFER_BASE_ADDRESS, in crypto_decrypt_kernel()
396 (uintptr_t)fw_raw_data, para->encrypt_size, HI_FALSE); in crypto_decrypt_kernel()
407 hi_u32 crypto_decrypt(encrypt_ctx *para) in crypto_decrypt() argument
412 hi_u32 ret = crypto_content_id(para, &werk_content, &werk_content_bak); in crypto_decrypt()
444 ret = crypto_decrypt_kernel(key_content, para); in crypto_decrypt()
450 ret = crypto_decrypt_kernel(key_content, para); in crypto_decrypt()
462 static hi_u32 crypto_encrypt_data(hi_flash_crypto_content *new_content, encrypt_ctx *para) in crypto_encrypt_data() argument
467 hi_u8 *fw_cyp_data = hi_malloc(HI_MOD_ID_CRYPTO, para->encrypt_size); in crypto_encrypt_data()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/components/enet_phy/rtl8201/
Dhpm_rtl8201.c68 uint16_t para = 0; in rtl8201_basic_mode_init() local
70 para |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ in rtl8201_basic_mode_init()
79 … para |= RTL8201_BMCR_SPEED0_SET(config->speed) | RTL8201_BMCR_SPEED1_SET(config->speed >> 1); in rtl8201_basic_mode_init()
87 para = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR) & ~RTL8201_BMCR_SPEED0_MASK; in rtl8201_basic_mode_init()
88 enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, para); in rtl8201_basic_mode_init()
92 para = enet_read_phy(ptr, PHY_ADDR, 16); in rtl8201_basic_mode_init()
93 para |= 1 << 12; /* set txc as input mode */ in rtl8201_basic_mode_init()
94 enet_write_phy(ptr, PHY_ADDR, 16, para); in rtl8201_basic_mode_init()
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/
Ddisp_private.h144 extern s32 disp_init_lcd(struct disp_bsp_init_para *para);
146 extern s32 disp_init_hdmi(struct disp_bsp_init_para *para);
152 extern s32 disp_init_tv_para(struct disp_bsp_init_para *para);
157 extern s32 disp_init_vdpo(struct disp_bsp_init_para *para);
158 extern s32 disp_init_edp(struct disp_bsp_init_para *para);
162 extern s32 disp_init_mgr(struct disp_bsp_init_para *para);
164 extern s32 disp_init_enhance(struct disp_bsp_init_para *para);
166 extern s32 disp_init_smbl(struct disp_bsp_init_para *para);
168 extern s32 disp_init_capture(struct disp_bsp_init_para *para);
172 extern s32 disp_init_eink(struct disp_bsp_init_para *para);
[all …]
Dlcd_debug.h40 struct para { struct
47 int handle_request(struct para *lcd_debug_para); argument
49 int retrieve_prop(struct para *lcd_debug_para);
50 int create_prop(struct para *lcd_debug_para);
51 int update_prop(struct para *lcd_debug_para);
52 int delete_prop(struct para *lcd_debug_para);
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/g2d/g2d_rcq/
Dg2d.c41 __g2d_info_t para; variable
103 address = dma_alloc_coherent(para.dev, actual_bytes, in g2d_malloc()
147 dma_free_coherent(para.dev, actual_bytes, virt_addr, in g2d_free()
459 mutex_lock(&para.mutex); in g2d_open()
460 para.user_cnt++; in g2d_open()
461 if (para.user_cnt == 1) { in g2d_open()
462 g2d_clock_enable(&para); in g2d_open()
463 para.opened = true; in g2d_open()
467 mutex_unlock(&para.mutex); in g2d_open()
474 mutex_lock(&para.mutex); in g2d_release()
[all …]
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/lcd/
Dcpu_gg1p4062utsw.c161 void lcd_dbi_wr_dcs(__u32 sel, __u8 cmd, __u8 *para, __u32 para_num) in lcd_dbi_wr_dcs() argument
164 __u8 *data_p = para; in lcd_dbi_wr_dcs()
174 __u8 para[4]; in lcd_cpu_panel_fr() local
177 para[0] = (x >> 8) & 0xff; in lcd_cpu_panel_fr()
178 para[1] = (x >> 0) & 0xff; in lcd_cpu_panel_fr()
179 para[2] = ((x + w - 1) >> 8) & 0xff; in lcd_cpu_panel_fr()
180 para[3] = ((x + w - 1) >> 0) & 0xff; in lcd_cpu_panel_fr()
182 lcd_dbi_wr_dcs(sel, DSI_DCS_SET_COLUMN_ADDRESS, para, para_num); in lcd_cpu_panel_fr()
184 para[0] = (y >> 8) & 0xff; in lcd_cpu_panel_fr()
185 para[1] = (y >> 0) & 0xff; in lcd_cpu_panel_fr()
[all …]
Drt13qv005d.c235 static void lcd_dbi_wr_dcs(__u32 sel, __u8 cmd, __u8 *para, __u32 para_num) in lcd_dbi_wr_dcs() argument
238 __u8 *data_p = para; in lcd_dbi_wr_dcs()
248 __u8 para[4]; in lcd_cpu_panel_fr() local
250 para[0] = (x >> 8) & 0xff; in lcd_cpu_panel_fr()
251 para[1] = (x >> 0) & 0xff; in lcd_cpu_panel_fr()
252 para[2] = ((x + w - 1) >> 8) & 0xff; in lcd_cpu_panel_fr()
253 para[3] = ((x + w - 1) >> 0) & 0xff; in lcd_cpu_panel_fr()
255 lcd_dbi_wr_dcs(sel, DSI_DCS_SET_COLUMN_ADDRESS, para, para_num); in lcd_cpu_panel_fr()
257 para[0] = (y >> 8) & 0xff; in lcd_cpu_panel_fr()
258 para[1] = (y >> 0) & 0xff; in lcd_cpu_panel_fr()
[all …]
Dto20t20000.c169 static void lcd_dbi_wr_dcs(__u32 sel, __u8 cmd, __u8 *para, __u32 para_num) in lcd_dbi_wr_dcs() argument
172 __u8 *data_p = para; in lcd_dbi_wr_dcs()
182 __u8 para[4]; in lcd_cpu_panel_fr() local
184 para[0] = (x >> 8) & 0xff; in lcd_cpu_panel_fr()
185 para[1] = (x >> 0) & 0xff; in lcd_cpu_panel_fr()
186 para[2] = ((x + w - 1) >> 8) & 0xff; in lcd_cpu_panel_fr()
187 para[3] = ((x + w - 1) >> 0) & 0xff; in lcd_cpu_panel_fr()
189 lcd_dbi_wr_dcs(sel, DSI_DCS_SET_COLUMN_ADDRESS, para, para_num); in lcd_cpu_panel_fr()
191 para[0] = (y >> 8) & 0xff; in lcd_cpu_panel_fr()
192 para[1] = (y >> 0) & 0xff; in lcd_cpu_panel_fr()
[all …]
Dlt070me05000.c170 u8 para[9]; in LCD_panel_init() local
197 para[0] = 0x31; in LCD_panel_init()
198 para[1] = 0xf7; in LCD_panel_init()
199 para[2] = 0x80; in LCD_panel_init()
200 para[3] = 0x00; in LCD_panel_init()
201 para[4] = panel_info->lcd_vbp - 1; in LCD_panel_init()
202 para[5] = 0x00; in LCD_panel_init()
203 para[6] = 0x08; in LCD_panel_init()
204 para[7] = 0x00; in LCD_panel_init()
205 para[8] = 0x00; in LCD_panel_init()
[all …]
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/drm/sunxi_device/
Dsunxi_hdmi14.c599 struct video_para *para) in sunxi_hdmi_timing_convert_to_video_para() argument
601 para->vic = timing->vic; in sunxi_hdmi_timing_convert_to_video_para()
602 para->pixel_clk = timing->pixel_clk; in sunxi_hdmi_timing_convert_to_video_para()
603 para->clk_div = hdmi_clk_get_div(); in sunxi_hdmi_timing_convert_to_video_para()
604 para->pixel_repeat = timing->pixel_repeat; in sunxi_hdmi_timing_convert_to_video_para()
605 para->x_res = timing->x_res; in sunxi_hdmi_timing_convert_to_video_para()
606 para->y_res = timing->y_res; in sunxi_hdmi_timing_convert_to_video_para()
607 para->hor_total_time = timing->hor_total_time; in sunxi_hdmi_timing_convert_to_video_para()
608 para->hor_back_porch = timing->hor_back_porch; in sunxi_hdmi_timing_convert_to_video_para()
609 para->hor_front_porch = timing->hor_front_porch; in sunxi_hdmi_timing_convert_to_video_para()
[all …]
/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_sun8iw8/
Ddisp_al.c429 struct disp_vdevice_interface_para *para, in disp_al_vdevice_cfg() argument
436 al_priv.output_mode[screen_id] = (u32) para->intf; in disp_al_vdevice_cfg()
445 info.lcd_if = para->intf; in disp_al_vdevice_cfg()
448 info.lcd_hv_if = (enum disp_lcd_hv_if)para->sub_intf; in disp_al_vdevice_cfg()
456 info.lcd_hv_syuv_fdly = para->fdelay; in disp_al_vdevice_cfg()
457 info.lcd_hv_clk_phase = para->clk_phase; in disp_al_vdevice_cfg()
458 info.lcd_hv_sync_polarity = para->sync_polarity; in disp_al_vdevice_cfg()
460 info.lcd_hv_syuv_seq = para->sequence; in disp_al_vdevice_cfg()
462 info.lcd_hv_srgb_seq = para->sequence; in disp_al_vdevice_cfg()
572 int disp_init_al(struct disp_bsp_init_para *para) in disp_init_al() argument
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/device/soc/hpmicro/sdk/hpm_sdk/components/enet_phy/rtl8211/
Dhpm_rtl8211.c68 uint16_t para = 0; in rtl8211_basic_mode_init() local
70 para |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ in rtl8211_basic_mode_init()
79 … para |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); in rtl8211_basic_mode_init()
82 enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, para); in rtl8211_basic_mode_init()
119 uint16_t para = 0; in rtl8211_control_config() local
121 para = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR) | (1 << 10); in rtl8211_control_config()
123 enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR, para); in rtl8211_control_config()

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