1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * ++ Initialization and Configuration of ADC
10 * + Operation functions
11 * ++ Start, stop, get result of conversions of regular
12 * group, using 3 possible modes: polling, interruption or DMA.
13 * + Control functions
14 * ++ Channels configuration on regular group
15 * ++ Analog Watchdog configuration
16 * + State functions
17 * ++ ADC state machine management
18 * ++ Interrupts and flags management
19 * Other functions (extended functions) are available in file
20 * "stm32mp1xx_hal_adc_ex.c".
21 *
22
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 *
36
37 @verbatim
38 ==============================================================================
39 ##### ADC peripheral features #####
40 ==============================================================================
41 [..]
42 (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
43
44 (+) Interrupt generation at the end of regular conversion and in case of
45 analog watchdog or overrun events.
46
47 (+) Single and continuous conversion modes.
48
49 (+) Scan mode for conversion of several channels sequentially.
50
51 (+) Data alignment with in-built data coherency.
52
53 (+) Programmable sampling time (channel wise)
54
55 (+) External trigger (timer or EXTI) with configurable polarity
56
57 (+) DMA request generation for transfer of conversions data of regular group.
58
59 (+) Configurable delay between conversions in Dual interleaved mode.
60
61 (+) ADC channels selectable single/differential input.
62
63 (+) ADC offset shared on 4 offset instances.
64 (+) ADC calibration
65
66 (+) ADC conversion of regular group.
67
68 (+) ADC supply requirements: 1.62 V to 3.6 V.
69
70 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
71 Vdda or to an external voltage reference).
72
73
74 ##### How to use this driver #####
75 ==============================================================================
76 [..]
77
78 *** Configuration of top level parameters related to ADC ***
79 ============================================================
80 [..]
81
82 (#) Enable the ADC interface
83 (++) As prerequisite, ADC clock must be configured at RCC top level.
84
85 (++) Two clock settings are mandatory:
86 (+++) ADC clock (core clock, also possibly conversion clock).
87
88 (+++) ADC clock (conversions clock).
89 Two possible clock sources: synchronous clock derived from AHB clock
90 or asynchronous clock derived from system clock, the PLL4 or the PLL3.
91
92 (+++) Example:
93 Into HAL_ADC_MspInit() (recommended code location) or with
94 other device clock parameters configuration:
95 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
96
97 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
98 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
99 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
100 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
101 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
102
103 (++) ADC clock source and clock prescaler are configured at ADC level with
104 parameter "ClockPrescaler" using function HAL_ADC_Init().
105
106 (#) ADC pins configuration
107 (++) Enable the clock for the ADC GPIOs
108 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
109 (++) Configure these ADC pins in analog mode
110 using function HAL_GPIO_Init()
111
112 (#) Optionally, in case of usage of ADC with interruptions:
113 (++) Configure the NVIC for ADC
114 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
115 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
116 into the function of corresponding ADC interruption vector
117 ADCx_IRQHandler().
118
119 (#) Optionally, in case of usage of DMA:
120 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
121 using function HAL_DMA_Init().
122 (++) Configure the NVIC for DMA
123 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
124 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
125 into the function of corresponding DMA interruption vector
126 DMAx_Channelx_IRQHandler().
127
128 *** Configuration of ADC, group regular, channels parameters ***
129 ================================================================
130 [..]
131
132 (#) Configure the ADC parameters (resolution, data alignment, ...)
133 and regular group parameters (conversion trigger, sequencer, ...)
134 using function HAL_ADC_Init().
135
136 (#) Configure the channels for regular group parameters (channel number,
137 channel rank into sequencer, ..., into regular group)
138 using function HAL_ADC_ConfigChannel().
139
140 (#) Optionally, configure the analog watchdog parameters (channels
141 monitored, thresholds, ...)
142 using function HAL_ADC_AnalogWDGConfig().
143
144 *** Execution of ADC conversions ***
145 ====================================
146 [..]
147
148 (#) Optionally, perform an automatic ADC calibration to improve the
149 conversion accuracy
150 using function HAL_ADCEx_Calibration_Start().
151
152 (#) ADC driver can be used among three modes: polling, interruption,
153 transfer by DMA.
154
155 (++) ADC conversion by polling:
156 (+++) Activate the ADC peripheral and start conversions
157 using function HAL_ADC_Start()
158 (+++) Wait for ADC conversion completion
159 using function HAL_ADC_PollForConversion()
160 (+++) Retrieve conversion results
161 using function HAL_ADC_GetValue()
162 (+++) Stop conversion and disable the ADC peripheral
163 using function HAL_ADC_Stop()
164
165 (++) ADC conversion by interruption:
166 (+++) Activate the ADC peripheral and start conversions
167 using function HAL_ADC_Start_IT()
168 (+++) Wait for ADC conversion completion by call of function
169 HAL_ADC_ConvCpltCallback()
170 (this function must be implemented in user program)
171 (+++) Retrieve conversion results
172 using function HAL_ADC_GetValue()
173 (+++) Stop conversion and disable the ADC peripheral
174 using function HAL_ADC_Stop_IT()
175
176 (++) ADC conversion with transfer by DMA:
177 (+++) Activate the ADC peripheral and start conversions
178 using function HAL_ADC_Start_DMA()
179 (+++) Wait for ADC conversion completion by call of function
180 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
181 (these functions must be implemented in user program)
182 (+++) Conversion results are automatically transferred by DMA into
183 destination variable address.
184 (+++) Stop conversion and disable the ADC peripheral
185 using function HAL_ADC_Stop_DMA()
186
187 [..]
188
189 (@) Callback functions must be implemented in user program:
190 (+@) HAL_ADC_ErrorCallback()
191 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
192 (+@) HAL_ADC_ConvCpltCallback()
193 (+@) HAL_ADC_ConvHalfCpltCallback
194
195 *** Deinitialization of ADC ***
196 ============================================================
197 [..]
198
199 (#) Disable the ADC interface
200 (++) ADC clock can be hard reset and disabled at RCC top level.
201 (++) Hard reset of ADC peripherals
202 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
203 (++) ADC clock disable
204 using the equivalent macro/functions as configuration step.
205 (+++) Example:
206 Into HAL_ADC_MspDeInit() (recommended code location) or with
207 other device clock parameters configuration:
208 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
209 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
210 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
211
212 (#) ADC pins configuration
213 (++) Disable the clock for the ADC GPIOs
214 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
215
216 (#) Optionally, in case of usage of ADC with interruptions:
217 (++) Disable the NVIC for ADC
218 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
219
220 (#) Optionally, in case of usage of DMA:
221 (++) Deinitialize the DMA
222 using function HAL_DMA_Init().
223 (++) Disable the NVIC for DMA
224 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
225
226 [..]
227
228 *** Callback registration ***
229 =============================================
230 [..]
231
232 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
233 allows the user to configure dynamically the driver callbacks.
234 Use Functions @ref HAL_ADC_RegisterCallback()
235 to register an interrupt callback.
236 [..]
237
238 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
239 (+) ConvCpltCallback : ADC conversion complete callback
240 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
241 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
242 (+) ErrorCallback : ADC error callback
243 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
244 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
245 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
246 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
247 (+) EndOfSamplingCallback : ADC end of sampling callback
248 (+) MspInitCallback : ADC Msp Init callback
249 (+) MspDeInitCallback : ADC Msp DeInit callback
250 This function takes as parameters the HAL peripheral handle, the Callback ID
251 and a pointer to the user callback function.
252 [..]
253
254 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
255 weak function.
256 [..]
257
258 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
259 and the Callback ID.
260 This function allows to reset following callbacks:
261 (+) ConvCpltCallback : ADC conversion complete callback
262 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
263 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
264 (+) ErrorCallback : ADC error callback
265 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
266 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
267 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
268 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
269 (+) EndOfSamplingCallback : ADC end of sampling callback
270 (+) MspInitCallback : ADC Msp Init callback
271 (+) MspDeInitCallback : ADC Msp DeInit callback
272 [..]
273
274 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
275 all callbacks are set to the corresponding weak functions:
276 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
277 Exception done for MspInit and MspDeInit functions that are
278 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
279 these callbacks are null (not registered beforehand).
280 [..]
281
282 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
283 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
284 [..]
285
286 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
287 Exception done MspInit/MspDeInit functions that can be registered/unregistered
288 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
289 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
290 [..]
291
292 Then, the user first registers the MspInit/MspDeInit user callbacks
293 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
294 or @ref HAL_ADC_Init() function.
295 [..]
296
297 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
298 not defined, the callback registration feature is not available and all callbacks
299 are set to the corresponding weak functions.
300
301 @endverbatim
302
303 /* Includes ------------------------------------------------------------------*/
304 #include "stm32mp1xx_hal.h"
305
306 /** @addtogroup STM32MP1xx_HAL_Driver
307 * @{
308 */
309
310 /** @defgroup ADC ADC
311 * @brief ADC HAL module driver
312 * @{
313 */
314
315 #ifdef HAL_ADC_MODULE_ENABLED
316
317 /* Private typedef -----------------------------------------------------------*/
318 /* Private define ------------------------------------------------------------*/
319
320 /** @defgroup ADC_Private_Constants ADC Private Constants
321 * @{
322 */
323 #define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
324 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
325 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
326 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
327
328 #define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
329 ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
330 ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */
331
332 /* Timeout values for ADC operations (enable settling time, */
333 /* disable settling time, ...). */
334 /* Values defined to be higher than worst cases: low clock frequency, */
335 /* maximum prescalers. */
336 #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
337 #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
338
339 /* Timeout to wait for current conversion on going to be completed. */
340 /* Timeout fixed to worst case, for 1 channel. */
341 /* - maximum sampling time (830.5 adc_clk) */
342 /* - ADC resolution (Tsar 16 bits= 16.5 adc_clk) */
343 /* - ADC clock with prescaler 256 */
344 /* 823 * 256 = 210688 clock cycles max */
345 /* Unit: cycles of CPU clock. */
346 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
347
348 /**
349 * @}
350 */
351
352 /* Private macro -------------------------------------------------------------*/
353 /* Private variables ---------------------------------------------------------*/
354 /* Private function prototypes -----------------------------------------------*/
355 /* Exported functions --------------------------------------------------------*/
356
357 /** @defgroup ADC_Exported_Functions ADC Exported Functions
358 * @{
359 */
360
361 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
362 * @brief ADC Initialization and Configuration functions
363 *
364 @verbatim
365 ===============================================================================
366 ##### Initialization and de-initialization functions #####
367 ===============================================================================
368 [..] This section provides functions allowing to:
369 (+) Initialize and configure the ADC.
370 (+) De-initialize the ADC.
371 @endverbatim
372 * @{
373 */
374
375 /**
376 * @brief Initialize the ADC peripheral and regular group according to
377 * parameters specified in structure "ADC_InitTypeDef".
378 * @note As prerequisite, ADC clock must be configured at RCC top level
379 * (refer to description of RCC configuration for ADC
380 * in header of this file).
381 * @note Possibility to update parameters on the fly:
382 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
383 * coming from ADC state reset. Following calls to this function can
384 * be used to reconfigure some parameters of ADC_InitTypeDef
385 * structure on the fly, without modifying MSP configuration. If ADC
386 * MSP has to be modified again, HAL_ADC_DeInit() must be called
387 * before HAL_ADC_Init().
388 * The setting of these parameters is conditioned to ADC state.
389 * For parameters constraints, see comments of structure
390 * "ADC_InitTypeDef".
391 * @note This function configures the ADC within 2 scopes: scope of entire
392 * ADC and scope of regular group. For parameters details, see comments
393 * of structure "ADC_InitTypeDef".
394 * @note Parameters related to common ADC registers (ADC clock mode) are set
395 * only if all ADCs are disabled.
396 * If this is not the case, these common parameters setting are
397 * bypassed without error reporting: it can be the intended behaviour in
398 * case of update of a parameter of ADC_InitTypeDef on the fly,
399 * without disabling the other ADCs.
400 * @param hadc ADC handle
401 * @retval HAL status
402 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)403 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
404 {
405 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
406 uint32_t tmpCFGR;
407 uint32_t tmp_adc_reg_is_conversion_on_going;
408 __IO uint32_t wait_loop_index = 0UL;
409 uint32_t tmp_adc_is_conversion_on_going_regular;
410 uint32_t tmp_adc_is_conversion_on_going_injected;
411
412 /* Check ADC handle */
413 if (hadc == NULL)
414 {
415 return HAL_ERROR;
416 }
417
418 /* Check the parameters */
419 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
420 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
421 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
422 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
423 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
424 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
425 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
426 assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
427 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
428 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
429 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
430 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
431
432 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
433 {
434 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
435 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
436
437 if (hadc->Init.DiscontinuousConvMode == ENABLE)
438 {
439 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
440 }
441 }
442
443 /* DISCEN and CONT bits cannot be set at the same time */
444 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
445
446 /* Actions performed only if ADC is coming from state reset: */
447 /* - Initialization of ADC MSP */
448 if (hadc->State == HAL_ADC_STATE_RESET)
449 {
450 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
451 /* Init the ADC Callback settings */
452 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
453 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
454 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
455 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
456 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
457 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
458 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
459 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
460 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
461
462 if (hadc->MspInitCallback == NULL)
463 {
464 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
465 }
466
467 /* Init the low level hardware */
468 hadc->MspInitCallback(hadc);
469 #else
470 /* Init the low level hardware */
471 HAL_ADC_MspInit(hadc);
472 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
473
474 /* Set ADC error code to none */
475 ADC_CLEAR_ERRORCODE(hadc);
476
477 /* Initialize Lock */
478 hadc->Lock = HAL_UNLOCKED;
479 }
480
481 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
482 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
483 {
484 /* Disable ADC deep power down mode */
485 LL_ADC_DisableDeepPowerDown(hadc->Instance);
486
487 /* System was in deep power down mode, calibration must
488 be relaunched or a previously saved calibration factor
489 re-applied once the ADC voltage regulator is enabled */
490 }
491
492 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
493 {
494 /* Enable ADC internal voltage regulator */
495 LL_ADC_EnableInternalRegulator(hadc->Instance);
496
497 /* Note: Variable divided by 2 to compensate partially */
498 /* CPU processing cycles, scaling in us split to not */
499 /* exceed 32 bits register capacity and handle low frequency. */
500 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
501 while (wait_loop_index != 0UL)
502 {
503 wait_loop_index--;
504 }
505 }
506
507 /* Verification that ADC voltage regulator is correctly enabled, whether */
508 /* or not ADC is coming from state reset (if any potential problem of */
509 /* clocking, voltage regulator would not be enabled). */
510 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
511 {
512 /* Update ADC state machine to error */
513 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
514
515 /* Set ADC error code to ADC peripheral internal error */
516 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
517
518 tmp_hal_status = HAL_ERROR;
519 }
520
521 /* Configuration of ADC parameters if previous preliminary actions are */
522 /* correctly completed and if there is no conversion on going on regular */
523 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
524 /* called to update a parameter on the fly). */
525 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
526
527 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
528 && (tmp_adc_reg_is_conversion_on_going == 0UL)
529 )
530 {
531 /* Set ADC state */
532 ADC_STATE_CLR_SET(hadc->State,
533 HAL_ADC_STATE_REG_BUSY,
534 HAL_ADC_STATE_BUSY_INTERNAL);
535
536 /* Configuration of common ADC parameters */
537
538 /* Parameters update conditioned to ADC state: */
539 /* Parameters that can be updated only when ADC is disabled: */
540 /* - clock configuration */
541 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
542 {
543 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
544 {
545 /* Reset configuration of ADC common register CCR: */
546 /* */
547 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
548 /* according to adc->Init.ClockPrescaler. It selects the clock */
549 /* source and sets the clock division factor. */
550 /* */
551 /* Some parameters of this register are not reset, since they are set */
552 /* by other functions and must be kept in case of usage of this */
553 /* function on the fly (update of a parameter of ADC_InitTypeDef */
554 /* without needing to reconfigure all other ADC groups/channels */
555 /* parameters): */
556 /* - when multimode feature is available, multimode-related */
557 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
558 /* HAL_ADCEx_MultiModeConfigChannel() ) */
559 /* - internal measurement paths: Vbat, temperature sensor, Vref */
560 /* (set into HAL_ADC_ConfigChannel() or */
561 /* HAL_ADCEx_InjectedConfigChannel() ) */
562 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
563 }
564 }
565
566 /* Configuration of ADC: */
567 /* - resolution Init.Resolution */
568 /* - external trigger to start conversion Init.ExternalTrigConv */
569 /* - external trigger polarity Init.ExternalTrigConvEdge */
570 /* - continuous conversion mode Init.ContinuousConvMode */
571 /* - overrun Init.Overrun */
572 /* - discontinuous mode Init.DiscontinuousConvMode */
573 /* - discontinuous mode channel count Init.NbrOfDiscConversion */
574 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
575 hadc->Init.Overrun |
576 hadc->Init.Resolution |
577 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
578
579 if (hadc->Init.DiscontinuousConvMode == ENABLE)
580 {
581 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
582 }
583
584 /* Enable external trigger if trigger selection is different of software */
585 /* start. */
586 /* Note: This configuration keeps the hardware feature of parameter */
587 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
588 /* software start. */
589 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
590 {
591 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
592 | hadc->Init.ExternalTrigConvEdge
593 );
594 }
595
596 /* Update Configuration Register CFGR */
597 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
598
599 /* Parameters update conditioned to ADC state: */
600 /* Parameters that can be updated when ADC is disabled or enabled without */
601 /* conversion on going on regular and injected groups: */
602 /* - Conversion data management Init.ConversionDataManagement */
603 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
604 /* - Oversampling parameters Init.Oversampling */
605 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
606 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
607 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
608 && (tmp_adc_is_conversion_on_going_injected == 0UL)
609 )
610 {
611 tmpCFGR = (
612 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
613 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
614
615 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
616
617 if (hadc->Init.OversamplingMode == ENABLE)
618 {
619 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
620 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
621 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
622 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
623
624 if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
625 || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
626 {
627 /* Multi trigger is not applicable to software-triggered conversions */
628 assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
629 }
630
631 /* Configuration of Oversampler: */
632 /* - Oversampling Ratio */
633 /* - Right bit shift */
634 /* - Left bit shift */
635 /* - Triggered mode */
636 /* - Oversampling mode (continued/resumed) */
637 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
638 ADC_CFGR2_ROVSE |
639 ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
640 hadc->Init.Oversampling.RightBitShift |
641 hadc->Init.Oversampling.TriggeredMode |
642 hadc->Init.Oversampling.OversamplingStopReset);
643
644 }
645 else
646 {
647 /* Disable ADC oversampling scope on ADC group regular */
648 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
649 }
650
651 /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
652 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
653
654 /* Configure the BOOST Mode */
655 ADC_ConfigureBoostMode(hadc);
656 }
657
658 /* Configuration of regular group sequencer: */
659 /* - if scan mode is disabled, regular channels sequence length is set to */
660 /* 0x00: 1 channel converted (channel on regular rank 1) */
661 /* Parameter "NbrOfConversion" is discarded. */
662 /* Note: Scan mode is not present by hardware on this device, but */
663 /* emulated by software for alignment over all STM32 devices. */
664 /* - if scan mode is enabled, regular channels sequence length is set to */
665 /* parameter "NbrOfConversion". */
666
667 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
668 {
669 /* Set number of ranks in regular group sequencer */
670 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
671 }
672 else
673 {
674 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
675 }
676
677 /* Initialize the ADC state */
678 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
679 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
680 }
681 else
682 {
683 /* Update ADC state machine to error */
684 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
685
686 tmp_hal_status = HAL_ERROR;
687 }
688
689 /* Return function status */
690 return tmp_hal_status;
691 }
692
693 /**
694 * @brief Deinitialize the ADC peripheral registers to their default reset
695 * values, with deinitialization of the ADC MSP.
696 * @note For devices with several ADCs: reset of ADC common registers is done
697 * only if all ADCs sharing the same common group are disabled.
698 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
699 * all ADC instances use the same core clock at RCC level, disabling
700 * the core clock reset all ADC instances).
701 * If this is not the case, reset of these common parameters reset is
702 * bypassed without error reporting: it can be the intended behavior in
703 * case of reset of a single ADC while the other ADCs sharing the same
704 * common group is still running.
705 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
706 * this saves more power by reducing leakage currents
707 * and is particularly interesting before entering MCU low-power modes.
708 * @param hadc ADC handle
709 * @retval HAL status
710 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)711 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
712 {
713 HAL_StatusTypeDef tmp_hal_status;
714
715 /* Check ADC handle */
716 if (hadc == NULL)
717 {
718 return HAL_ERROR;
719 }
720
721 /* Check the parameters */
722 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
723
724 /* Set ADC state */
725 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
726
727 /* Stop potential conversion on going */
728 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
729
730 /* Disable ADC peripheral if conversions are effectively stopped */
731 /* Flush register JSQR: reset the queue sequencer when injected */
732 /* queue sequencer is enabled and ADC disabled. */
733 /* The software and hardware triggers of the injected sequence are both */
734 /* internally disabled just after the completion of the last valid */
735 /* injected sequence. */
736 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
737
738 /* Disable ADC peripheral if conversions are effectively stopped */
739 if (tmp_hal_status == HAL_OK)
740 {
741 /* Disable the ADC peripheral */
742 tmp_hal_status = ADC_Disable(hadc);
743
744 /* Check if ADC is effectively disabled */
745 if (tmp_hal_status == HAL_OK)
746 {
747 /* Change ADC state */
748 hadc->State = HAL_ADC_STATE_READY;
749 }
750 }
751
752 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
753 /* and disable return status. In case of status fail, attempt to */
754 /* perform deinitialization anyway and it is up user code in */
755 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
756 /* system RCC hard reset. */
757
758 /* ========== Reset ADC registers ========== */
759 /* Reset register IER */
760 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
761 ADC_IT_JQOVF | ADC_IT_OVR |
762 ADC_IT_JEOS | ADC_IT_JEOC |
763 ADC_IT_EOS | ADC_IT_EOC |
764 ADC_IT_EOSMP | ADC_IT_RDY));
765
766 /* Reset register ISR */
767 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
768 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
769 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
770 ADC_FLAG_EOS | ADC_FLAG_EOC |
771 ADC_FLAG_EOSMP | ADC_FLAG_RDY));
772
773 /* Reset register CR */
774 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
775 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
776 no direct reset applicable.
777 Update CR register to reset value where doable by software */
778 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
779 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
780
781 /* Reset register CFGR */
782 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
783 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
784 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
785 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
786 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
787 ADC_CFGR_RES | ADC_CFGR_DMNGT);
788 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
789
790 /* Reset register CFGR2 */
791 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
792 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
793
794 /* Reset register SMPR1 */
795 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
796
797 /* Reset register SMPR2 */
798 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
799 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
800 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
801
802 /* Reset register LTR1 and HTR1 */
803 CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
804 CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
805
806 /* Reset register LTR2 and HTR2*/
807 CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
808 CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
809
810 /* Reset register LTR3 and HTR3 */
811 CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2);
812 CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2);
813
814 /* Reset register SQR1 */
815 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
816 ADC_SQR1_SQ1 | ADC_SQR1_L);
817
818 /* Reset register SQR2 */
819 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
820 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
821
822 /* Reset register SQR3 */
823 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
824 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
825
826 /* Reset register SQR4 */
827 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
828
829 /* Register JSQR was reset when the ADC was disabled */
830
831 /* Reset register DR */
832 /* bits in access mode read only, no direct reset applicable*/
833
834 /* Reset register OFR1 */
835 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
836 /* Reset register OFR2 */
837 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
838 /* Reset register OFR3 */
839 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
840 /* Reset register OFR4 */
841 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
842
843 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
844 /* bits in access mode read only, no direct reset applicable*/
845
846 /* Reset register AWD2CR */
847 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
848
849 /* Reset register AWD3CR */
850 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
851
852 /* Reset register DIFSEL */
853 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
854
855 /* Reset register CALFACT */
856 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
857
858
859 /* ========== Reset common ADC registers ========== */
860
861 /* Software is allowed to change common parameters only when all the other
862 ADCs are disabled. */
863 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
864 {
865 /* Reset configuration of ADC common register CCR:
866 - clock mode: CKMODE, PRESCEN
867 - multimode related parameters(when this feature is available): DELAY, DUAL
868 (set into HAL_ADCEx_MultiModeConfigChannel() API)
869 - internal measurement paths: Vbat, temperature sensor, Vref (set into
870 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
871 */
872 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
873 }
874
875 /* DeInit the low level hardware.
876
877 For example:
878 __HAL_RCC_ADC_FORCE_RESET();
879 __HAL_RCC_ADC_RELEASE_RESET();
880 __HAL_RCC_ADC_CLK_DISABLE();
881
882 Keep in mind that all ADCs use the same clock: disabling
883 the clock will reset all ADCs.
884
885 */
886 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
887 if (hadc->MspDeInitCallback == NULL)
888 {
889 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
890 }
891
892 /* DeInit the low level hardware */
893 hadc->MspDeInitCallback(hadc);
894 #else
895 /* DeInit the low level hardware */
896 HAL_ADC_MspDeInit(hadc);
897 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
898
899 /* Set ADC error code to none */
900 ADC_CLEAR_ERRORCODE(hadc);
901
902 /* Reset injected channel configuration parameters */
903 hadc->InjectionConfig.ContextQueue = 0;
904 hadc->InjectionConfig.ChannelCount = 0;
905
906 /* Set ADC state */
907 hadc->State = HAL_ADC_STATE_RESET;
908
909 /* Process unlocked */
910 __HAL_UNLOCK(hadc);
911
912 /* Return function status */
913 return tmp_hal_status;
914 }
915
916 /**
917 * @brief Initialize the ADC MSP.
918 * @param hadc ADC handle
919 * @retval None
920 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)921 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
922 {
923 /* Prevent unused argument(s) compilation warning */
924 UNUSED(hadc);
925
926 /* NOTE : This function should not be modified. When the callback is needed,
927 function HAL_ADC_MspInit must be implemented in the user file.
928 */
929 }
930
931 /**
932 * @brief DeInitialize the ADC MSP.
933 * @param hadc ADC handle
934 * @note All ADC instances use the same core clock at RCC level, disabling
935 * the core clock reset all ADC instances).
936 * @retval None
937 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)938 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
939 {
940 /* Prevent unused argument(s) compilation warning */
941 UNUSED(hadc);
942
943 /* NOTE : This function should not be modified. When the callback is needed,
944 function HAL_ADC_MspDeInit must be implemented in the user file.
945 */
946 }
947
948 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
949 /**
950 * @brief Register a User ADC Callback
951 * To be used instead of the weak predefined callback
952 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
953 * the configuration information for the specified ADC.
954 * @param CallbackID ID of the callback to be registered
955 * This parameter can be one of the following values:
956 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
957 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
958 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
959 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
960 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
961 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
962 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
963 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
964 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
965 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
966 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
967 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
968 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
969 * @param pCallback pointer to the Callback function
970 * @retval HAL status
971 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)972 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
973 pADC_CallbackTypeDef pCallback)
974 {
975 HAL_StatusTypeDef status = HAL_OK;
976
977 if (pCallback == NULL)
978 {
979 /* Update the error code */
980 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
981
982 return HAL_ERROR;
983 }
984
985 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
986 {
987 switch (CallbackID)
988 {
989 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
990 hadc->ConvCpltCallback = pCallback;
991 break;
992
993 case HAL_ADC_CONVERSION_HALF_CB_ID :
994 hadc->ConvHalfCpltCallback = pCallback;
995 break;
996
997 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
998 hadc->LevelOutOfWindowCallback = pCallback;
999 break;
1000
1001 case HAL_ADC_ERROR_CB_ID :
1002 hadc->ErrorCallback = pCallback;
1003 break;
1004
1005 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1006 hadc->InjectedConvCpltCallback = pCallback;
1007 break;
1008
1009 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1010 hadc->InjectedQueueOverflowCallback = pCallback;
1011 break;
1012
1013 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1014 hadc->LevelOutOfWindow2Callback = pCallback;
1015 break;
1016
1017 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1018 hadc->LevelOutOfWindow3Callback = pCallback;
1019 break;
1020
1021 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1022 hadc->EndOfSamplingCallback = pCallback;
1023 break;
1024
1025 case HAL_ADC_MSPINIT_CB_ID :
1026 hadc->MspInitCallback = pCallback;
1027 break;
1028
1029 case HAL_ADC_MSPDEINIT_CB_ID :
1030 hadc->MspDeInitCallback = pCallback;
1031 break;
1032
1033 default :
1034 /* Update the error code */
1035 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1036
1037 /* Return error status */
1038 status = HAL_ERROR;
1039 break;
1040 }
1041 }
1042 else if (HAL_ADC_STATE_RESET == hadc->State)
1043 {
1044 switch (CallbackID)
1045 {
1046 case HAL_ADC_MSPINIT_CB_ID :
1047 hadc->MspInitCallback = pCallback;
1048 break;
1049
1050 case HAL_ADC_MSPDEINIT_CB_ID :
1051 hadc->MspDeInitCallback = pCallback;
1052 break;
1053
1054 default :
1055 /* Update the error code */
1056 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1057
1058 /* Return error status */
1059 status = HAL_ERROR;
1060 break;
1061 }
1062 }
1063 else
1064 {
1065 /* Update the error code */
1066 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1067
1068 /* Return error status */
1069 status = HAL_ERROR;
1070 }
1071
1072 return status;
1073 }
1074
1075 /**
1076 * @brief Unregister a ADC Callback
1077 * ADC callback is redirected to the weak predefined callback
1078 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1079 * the configuration information for the specified ADC.
1080 * @param CallbackID ID of the callback to be unregistered
1081 * This parameter can be one of the following values:
1082 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1083 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1084 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1085 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1086 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
1087 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
1088 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1089 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1090 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1091 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1092 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1093 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1094 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1095 * @retval HAL status
1096 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1097 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1098 {
1099 HAL_StatusTypeDef status = HAL_OK;
1100
1101 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1102 {
1103 switch (CallbackID)
1104 {
1105 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1106 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1107 break;
1108
1109 case HAL_ADC_CONVERSION_HALF_CB_ID :
1110 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1111 break;
1112
1113 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1114 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1115 break;
1116
1117 case HAL_ADC_ERROR_CB_ID :
1118 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1119 break;
1120
1121 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1122 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
1123 break;
1124
1125 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1126 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
1127 break;
1128
1129 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1130 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1131 break;
1132
1133 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1134 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1135 break;
1136
1137 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1138 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1139 break;
1140
1141 case HAL_ADC_MSPINIT_CB_ID :
1142 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1143 break;
1144
1145 case HAL_ADC_MSPDEINIT_CB_ID :
1146 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1147 break;
1148
1149 default :
1150 /* Update the error code */
1151 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1152
1153 /* Return error status */
1154 status = HAL_ERROR;
1155 break;
1156 }
1157 }
1158 else if (HAL_ADC_STATE_RESET == hadc->State)
1159 {
1160 switch (CallbackID)
1161 {
1162 case HAL_ADC_MSPINIT_CB_ID :
1163 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1164 break;
1165
1166 case HAL_ADC_MSPDEINIT_CB_ID :
1167 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1168 break;
1169
1170 default :
1171 /* Update the error code */
1172 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1173
1174 /* Return error status */
1175 status = HAL_ERROR;
1176 break;
1177 }
1178 }
1179 else
1180 {
1181 /* Update the error code */
1182 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1183
1184 /* Return error status */
1185 status = HAL_ERROR;
1186 }
1187
1188 return status;
1189 }
1190
1191 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1192
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1198 * @brief ADC IO operation functions
1199 *
1200 @verbatim
1201 ===============================================================================
1202 ##### IO operation functions #####
1203 ===============================================================================
1204 [..] This section provides functions allowing to:
1205 (+) Start conversion of regular group.
1206 (+) Stop conversion of regular group.
1207 (+) Poll for conversion complete on regular group.
1208 (+) Poll for conversion event.
1209 (+) Get result of regular channel conversion.
1210 (+) Start conversion of regular group and enable interruptions.
1211 (+) Stop conversion of regular group and disable interruptions.
1212 (+) Handle ADC interrupt request
1213 (+) Start conversion of regular group and enable DMA transfer.
1214 (+) Stop conversion of regular group and disable ADC DMA transfer.
1215 @endverbatim
1216 * @{
1217 */
1218
1219 /**
1220 * @brief Enable ADC, start conversion of regular group.
1221 * @note Interruptions enabled in this function: None.
1222 * @note Case of multimode enabled (when multimode feature is available):
1223 * if ADC is Slave, ADC is enabled but conversion is not started,
1224 * if ADC is master, ADC is enabled and multimode conversion is started.
1225 * @param hadc ADC handle
1226 * @retval HAL status
1227 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1228 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1229 {
1230 HAL_StatusTypeDef tmp_hal_status;
1231 #if defined(ADC_MULTIMODE_SUPPORT)
1232 const ADC_TypeDef *tmpADC_Master;
1233 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1234 #endif
1235
1236 /* Check the parameters */
1237 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1238
1239 /* Perform ADC enable and conversion start if no conversion is on going */
1240 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1241 {
1242 /* Process locked */
1243 __HAL_LOCK(hadc);
1244
1245 /* Enable the ADC peripheral */
1246 tmp_hal_status = ADC_Enable(hadc);
1247
1248 /* Start conversion if ADC is effectively enabled */
1249 if (tmp_hal_status == HAL_OK)
1250 {
1251 /* Set ADC state */
1252 /* - Clear state bitfield related to regular group conversion results */
1253 /* - Set state bitfield related to regular operation */
1254 ADC_STATE_CLR_SET(hadc->State,
1255 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1256 HAL_ADC_STATE_REG_BUSY);
1257
1258 #if defined(ADC_MULTIMODE_SUPPORT)
1259 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1260 - if ADC instance is master or if multimode feature is not available
1261 - if multimode setting is disabled (ADC instance slave in independent mode) */
1262 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1263 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1264 )
1265 {
1266 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1267 }
1268 #endif
1269
1270 /* Set ADC error code */
1271 /* Check if a conversion is on going on ADC group injected */
1272 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1273 {
1274 /* Reset ADC error code fields related to regular conversions only */
1275 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1276 }
1277 else
1278 {
1279 /* Reset all ADC error code fields */
1280 ADC_CLEAR_ERRORCODE(hadc);
1281 }
1282
1283 /* Clear ADC group regular conversion flag and overrun flag */
1284 /* (To ensure of no unknown state from potential previous ADC operations) */
1285 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1286
1287 /* Process unlocked */
1288 /* Unlock before starting ADC conversions: in case of potential */
1289 /* interruption, to let the process to ADC IRQ Handler. */
1290 __HAL_UNLOCK(hadc);
1291
1292 /* Enable conversion of regular group. */
1293 /* If software start has been selected, conversion starts immediately. */
1294 /* If external trigger has been selected, conversion will start at next */
1295 /* trigger event. */
1296 /* Case of multimode enabled (when multimode feature is available): */
1297 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1298 /* enabled only (conversion is not started), */
1299 /* - if ADC is master, ADC is enabled and conversion is started. */
1300 #if defined(ADC_MULTIMODE_SUPPORT)
1301 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1302 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1303 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1304 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1305 )
1306 {
1307 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1308 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1309 {
1310 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1311 }
1312
1313 /* Start ADC group regular conversion */
1314 LL_ADC_REG_StartConversion(hadc->Instance);
1315 }
1316 else
1317 {
1318 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1319 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1320 /* if Master ADC JAUTO bit is set, update Slave State in setting
1321 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
1322 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1323 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1324 {
1325 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1326 }
1327
1328 }
1329 #else
1330 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1331 {
1332 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1333 }
1334
1335 /* Start ADC group regular conversion */
1336 LL_ADC_REG_StartConversion(hadc->Instance);
1337 #endif
1338 }
1339 else
1340 {
1341 /* Process unlocked */
1342 __HAL_UNLOCK(hadc);
1343 }
1344 }
1345 else
1346 {
1347 tmp_hal_status = HAL_BUSY;
1348 }
1349
1350 /* Return function status */
1351 return tmp_hal_status;
1352 }
1353
1354 /**
1355 * @brief Stop ADC conversion of regular group (and injected channels in
1356 * case of auto_injection mode), disable ADC peripheral.
1357 * @note: ADC peripheral disable is forcing stop of potential
1358 * conversion on injected group. If injected group is under use, it
1359 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1360 * @param hadc ADC handle
1361 * @retval HAL status.
1362 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1363 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1364 {
1365 HAL_StatusTypeDef tmp_hal_status;
1366
1367 /* Check the parameters */
1368 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1369
1370 /* Process locked */
1371 __HAL_LOCK(hadc);
1372
1373 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1374 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1375
1376 /* Disable ADC peripheral if conversions are effectively stopped */
1377 if (tmp_hal_status == HAL_OK)
1378 {
1379 /* 2. Disable the ADC peripheral */
1380 tmp_hal_status = ADC_Disable(hadc);
1381
1382 /* Check if ADC is effectively disabled */
1383 if (tmp_hal_status == HAL_OK)
1384 {
1385 /* Set ADC state */
1386 ADC_STATE_CLR_SET(hadc->State,
1387 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1388 HAL_ADC_STATE_READY);
1389 }
1390 }
1391
1392 /* Process unlocked */
1393 __HAL_UNLOCK(hadc);
1394
1395 /* Return function status */
1396 return tmp_hal_status;
1397 }
1398
1399 /**
1400 * @brief Wait for regular group conversion to be completed.
1401 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1402 * conversion) are cleared by this function, with an exception:
1403 * if low power feature "LowPowerAutoWait" is enabled, flags are
1404 * not cleared to not interfere with this feature until data register
1405 * is read using function HAL_ADC_GetValue().
1406 * @note This function cannot be used in a particular setup: ADC configured
1407 * in DMA mode and polling for end of each conversion (ADC init
1408 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1409 * In this case, DMA resets the flag EOC and polling cannot be
1410 * performed on each conversion. Nevertheless, polling can still
1411 * be performed on the complete sequence (ADC init
1412 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1413 * @param hadc ADC handle
1414 * @param Timeout Timeout value in millisecond.
1415 * @retval HAL status
1416 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1417 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1418 {
1419 uint32_t tickstart;
1420 uint32_t tmp_Flag_End;
1421 uint32_t tmp_cfgr;
1422 #if defined(ADC_MULTIMODE_SUPPORT)
1423 const ADC_TypeDef *tmpADC_Master;
1424 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1425 #endif
1426
1427 /* Check the parameters */
1428 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1429
1430 /* If end of conversion selected to end of sequence conversions */
1431 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1432 {
1433 tmp_Flag_End = ADC_FLAG_EOS;
1434 }
1435 /* If end of conversion selected to end of unitary conversion */
1436 else /* ADC_EOC_SINGLE_CONV */
1437 {
1438 /* Verification that ADC configuration is compliant with polling for */
1439 /* each conversion: */
1440 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1441 /* several ranks and polling for end of each conversion. */
1442 /* For code simplicity sake, this particular case is generalized to */
1443 /* ADC configured in DMA mode and and polling for end of each conversion. */
1444 #if defined(ADC_MULTIMODE_SUPPORT)
1445 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1446 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1447 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1448 )
1449 {
1450 /* Check DMNGT bit in handle ADC CFGR register */
1451 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
1452 {
1453 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1454 return HAL_ERROR;
1455 }
1456 else
1457 {
1458 tmp_Flag_End = (ADC_FLAG_EOC);
1459 }
1460 }
1461 else
1462 {
1463 /* Check ADC DMA mode in multimode on ADC group regular */
1464 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
1465 {
1466 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1467 return HAL_ERROR;
1468 }
1469 else
1470 {
1471 tmp_Flag_End = (ADC_FLAG_EOC);
1472 }
1473 }
1474 #else
1475 /* Check ADC DMA mode */
1476 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
1477 {
1478 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1479 return HAL_ERROR;
1480 }
1481 else
1482 {
1483 tmp_Flag_End = (ADC_FLAG_EOC);
1484 }
1485 #endif
1486 }
1487
1488 /* Get tick count */
1489 tickstart = HAL_GetTick();
1490
1491 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1492 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1493 {
1494 /* Check if timeout is disabled (set to infinite wait) */
1495 if (Timeout != HAL_MAX_DELAY)
1496 {
1497 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1498 {
1499 /* Update ADC state machine to timeout */
1500 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1501
1502 /* Process unlocked */
1503 __HAL_UNLOCK(hadc);
1504
1505 return HAL_TIMEOUT;
1506 }
1507 }
1508 }
1509
1510 /* Update ADC state machine */
1511 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1512
1513 /* Determine whether any further conversion upcoming on group regular */
1514 /* by external trigger, continuous mode or scan sequence on going. */
1515 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1516 && (hadc->Init.ContinuousConvMode == DISABLE)
1517 )
1518 {
1519 /* Check whether end of sequence is reached */
1520 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1521 {
1522 /* Set ADC state */
1523 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1524
1525 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
1526 {
1527 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1528 }
1529 }
1530 }
1531
1532 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1533 /* in function of multimode state (for devices with multimode */
1534 /* available). */
1535 #if defined(ADC_MULTIMODE_SUPPORT)
1536 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1537 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1538 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1539 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1540 )
1541 {
1542 /* Retrieve handle ADC CFGR register */
1543 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1544 }
1545 else
1546 {
1547 /* Retrieve Master ADC CFGR register */
1548 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1549 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
1550 }
1551 #else
1552 /* Retrieve handle ADC CFGR register */
1553 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1554 #endif
1555
1556 /* Clear polled flag */
1557 if (tmp_Flag_End == ADC_FLAG_EOS)
1558 {
1559 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
1560 }
1561 else
1562 {
1563 /* Clear end of conversion EOC flag of regular group if low power feature */
1564 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1565 /* until data register is read using function HAL_ADC_GetValue(). */
1566 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
1567 {
1568 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1569 }
1570 }
1571
1572 /* Return function status */
1573 return HAL_OK;
1574 }
1575
1576 /**
1577 * @brief Poll for ADC event.
1578 * @param hadc ADC handle
1579 * @param EventType the ADC event type.
1580 * This parameter can be one of the following values:
1581 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1582 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1583 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1584 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1585 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1586 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
1587 * @param Timeout Timeout value in millisecond.
1588 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1589 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1590 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1591 * by a new converted data as soon as OVR is cleared.
1592 * To reset OVR flag once the preserved data is retrieved, the user can resort
1593 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1594 * @retval HAL status
1595 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1596 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1597 {
1598 uint32_t tickstart;
1599
1600 /* Check the parameters */
1601 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1602 assert_param(IS_ADC_EVENT_TYPE(EventType));
1603
1604 /* Get tick count */
1605 tickstart = HAL_GetTick();
1606
1607 /* Check selected event flag */
1608 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1609 {
1610 /* Check if timeout is disabled (set to infinite wait) */
1611 if (Timeout != HAL_MAX_DELAY)
1612 {
1613 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1614 {
1615 /* Update ADC state machine to timeout */
1616 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1617
1618 /* Process unlocked */
1619 __HAL_UNLOCK(hadc);
1620
1621 return HAL_TIMEOUT;
1622 }
1623 }
1624 }
1625
1626 switch (EventType)
1627 {
1628 /* End Of Sampling event */
1629 case ADC_EOSMP_EVENT:
1630 /* Set ADC state */
1631 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1632
1633 /* Clear the End Of Sampling flag */
1634 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1635
1636 break;
1637
1638 /* Analog watchdog (level out of window) event */
1639 /* Note: In case of several analog watchdog enabled, if needed to know */
1640 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1641 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1642 /* For example: */
1643 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1644 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1645 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1646
1647 /* Check analog watchdog 1 flag */
1648 case ADC_AWD_EVENT:
1649 /* Set ADC state */
1650 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1651
1652 /* Clear ADC analog watchdog flag */
1653 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1654
1655 break;
1656
1657 /* Check analog watchdog 2 flag */
1658 case ADC_AWD2_EVENT:
1659 /* Set ADC state */
1660 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1661
1662 /* Clear ADC analog watchdog flag */
1663 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1664
1665 break;
1666
1667 /* Check analog watchdog 3 flag */
1668 case ADC_AWD3_EVENT:
1669 /* Set ADC state */
1670 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1671
1672 /* Clear ADC analog watchdog flag */
1673 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1674
1675 break;
1676
1677 /* Injected context queue overflow event */
1678 case ADC_JQOVF_EVENT:
1679 /* Set ADC state */
1680 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1681
1682 /* Set ADC error code to Injected context queue overflow */
1683 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1684
1685 /* Clear ADC Injected context queue overflow flag */
1686 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1687
1688 break;
1689
1690 /* Overrun event */
1691 default: /* Case ADC_OVR_EVENT */
1692 /* If overrun is set to overwrite previous data, overrun event is not */
1693 /* considered as an error. */
1694 /* (cf ref manual "Managing conversions without using the DMA and without */
1695 /* overrun ") */
1696 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1697 {
1698 /* Set ADC state */
1699 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1700
1701 /* Set ADC error code to overrun */
1702 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1703 }
1704 else
1705 {
1706 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1707 otherwise, data register is potentially overwritten by new converted data as soon
1708 as OVR is cleared. */
1709 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1710 }
1711 break;
1712 }
1713
1714 /* Return function status */
1715 return HAL_OK;
1716 }
1717
1718 /**
1719 * @brief Enable ADC, start conversion of regular group with interruption.
1720 * @note Interruptions enabled in this function according to initialization
1721 * setting : EOC (end of conversion), EOS (end of sequence),
1722 * OVR overrun.
1723 * Each of these interruptions has its dedicated callback function.
1724 * @note Case of multimode enabled (when multimode feature is available):
1725 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
1726 * ADC Master.
1727 * For ADC Slave, ADC is enabled only (conversion is not started).
1728 * For ADC Master, ADC is enabled and multimode conversion is started.
1729 * @note To guarantee a proper reset of all interruptions once all the needed
1730 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1731 * a correct stop of the IT-based conversions.
1732 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1733 * interruption. If required (e.g. in case of oversampling with trigger
1734 * mode), the user must:
1735 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1736 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1737 * before calling HAL_ADC_Start_IT().
1738 * @param hadc ADC handle
1739 * @retval HAL status
1740 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1741 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1742 {
1743 HAL_StatusTypeDef tmp_hal_status;
1744 #if defined(ADC_MULTIMODE_SUPPORT)
1745 const ADC_TypeDef *tmpADC_Master;
1746 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1747 #endif
1748
1749 /* Check the parameters */
1750 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1751
1752 /* Perform ADC enable and conversion start if no conversion is on going */
1753 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1754 {
1755 /* Process locked */
1756 __HAL_LOCK(hadc);
1757
1758 /* Enable the ADC peripheral */
1759 tmp_hal_status = ADC_Enable(hadc);
1760
1761 /* Start conversion if ADC is effectively enabled */
1762 if (tmp_hal_status == HAL_OK)
1763 {
1764 /* Set ADC state */
1765 /* - Clear state bitfield related to regular group conversion results */
1766 /* - Set state bitfield related to regular operation */
1767 ADC_STATE_CLR_SET(hadc->State,
1768 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1769 HAL_ADC_STATE_REG_BUSY);
1770
1771 #if defined(ADC_MULTIMODE_SUPPORT)
1772 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1773 - if ADC instance is master or if multimode feature is not available
1774 - if multimode setting is disabled (ADC instance slave in independent mode) */
1775 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1776 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1777 )
1778 {
1779 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1780 }
1781 #endif
1782
1783 /* Set ADC error code */
1784 /* Check if a conversion is on going on ADC group injected */
1785 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
1786 {
1787 /* Reset ADC error code fields related to regular conversions only */
1788 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1789 }
1790 else
1791 {
1792 /* Reset all ADC error code fields */
1793 ADC_CLEAR_ERRORCODE(hadc);
1794 }
1795
1796 /* Clear ADC group regular conversion flag and overrun flag */
1797 /* (To ensure of no unknown state from potential previous ADC operations) */
1798 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1799
1800 /* Process unlocked */
1801 /* Unlock before starting ADC conversions: in case of potential */
1802 /* interruption, to let the process to ADC IRQ Handler. */
1803 __HAL_UNLOCK(hadc);
1804
1805 /* Disable all interruptions before enabling the desired ones */
1806 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1807
1808 /* Enable ADC end of conversion interrupt */
1809 switch (hadc->Init.EOCSelection)
1810 {
1811 case ADC_EOC_SEQ_CONV:
1812 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1813 break;
1814 /* case ADC_EOC_SINGLE_CONV */
1815 default:
1816 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1817 break;
1818 }
1819
1820 /* Enable ADC overrun interrupt */
1821 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1822 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1823 behavior and no CPU time is lost for a non-processed interruption */
1824 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1825 {
1826 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1827 }
1828
1829 /* Enable conversion of regular group. */
1830 /* If software start has been selected, conversion starts immediately. */
1831 /* If external trigger has been selected, conversion will start at next */
1832 /* trigger event. */
1833 /* Case of multimode enabled (when multimode feature is available): */
1834 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1835 /* enabled only (conversion is not started), */
1836 /* - if ADC is master, ADC is enabled and conversion is started. */
1837 #if defined(ADC_MULTIMODE_SUPPORT)
1838 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1839 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1840 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1841 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1842 )
1843 {
1844 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1845 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1846 {
1847 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1848
1849 /* Enable as well injected interruptions in case
1850 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1851 allows to start regular and injected conversions when JAUTO is
1852 set with a single call to HAL_ADC_Start_IT() */
1853 switch (hadc->Init.EOCSelection)
1854 {
1855 case ADC_EOC_SEQ_CONV:
1856 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1857 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1858 break;
1859 /* case ADC_EOC_SINGLE_CONV */
1860 default:
1861 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1862 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1863 break;
1864 }
1865 }
1866
1867 /* Start ADC group regular conversion */
1868 LL_ADC_REG_StartConversion(hadc->Instance);
1869 }
1870 else
1871 {
1872 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1873 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1874 /* if Master ADC JAUTO bit is set, Slave injected interruptions
1875 are enabled nevertheless (for same reason as above) */
1876 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1877 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1878 {
1879 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
1880 and in resetting HAL_ADC_STATE_INJ_EOC bit */
1881 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1882 /* Next, set Slave injected interruptions */
1883 switch (hadc->Init.EOCSelection)
1884 {
1885 case ADC_EOC_SEQ_CONV:
1886 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1887 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1888 break;
1889 /* case ADC_EOC_SINGLE_CONV */
1890 default:
1891 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1892 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1893 break;
1894 }
1895 }
1896 }
1897 #else
1898 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1899 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1900 {
1901 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1902
1903 /* Enable as well injected interruptions in case
1904 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1905 allows to start regular and injected conversions when JAUTO is
1906 set with a single call to HAL_ADC_Start_IT() */
1907 switch (hadc->Init.EOCSelection)
1908 {
1909 case ADC_EOC_SEQ_CONV:
1910 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1911 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1912 break;
1913 /* case ADC_EOC_SINGLE_CONV */
1914 default:
1915 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1916 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1917 break;
1918 }
1919 }
1920
1921 /* Start ADC group regular conversion */
1922 LL_ADC_REG_StartConversion(hadc->Instance);
1923 #endif
1924 }
1925 else
1926 {
1927 /* Process unlocked */
1928 __HAL_UNLOCK(hadc);
1929 }
1930
1931 }
1932 else
1933 {
1934 tmp_hal_status = HAL_BUSY;
1935 }
1936
1937 /* Return function status */
1938 return tmp_hal_status;
1939 }
1940
1941 /**
1942 * @brief Stop ADC conversion of regular group (and injected group in
1943 * case of auto_injection mode), disable interrution of
1944 * end-of-conversion, disable ADC peripheral.
1945 * @param hadc ADC handle
1946 * @retval HAL status.
1947 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1948 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1949 {
1950 HAL_StatusTypeDef tmp_hal_status;
1951
1952 /* Check the parameters */
1953 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1954
1955 /* Process locked */
1956 __HAL_LOCK(hadc);
1957
1958 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1959 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1960
1961 /* Disable ADC peripheral if conversions are effectively stopped */
1962 if (tmp_hal_status == HAL_OK)
1963 {
1964 /* Disable ADC end of conversion interrupt for regular group */
1965 /* Disable ADC overrun interrupt */
1966 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1967
1968 /* 2. Disable the ADC peripheral */
1969 tmp_hal_status = ADC_Disable(hadc);
1970
1971 /* Check if ADC is effectively disabled */
1972 if (tmp_hal_status == HAL_OK)
1973 {
1974 /* Set ADC state */
1975 ADC_STATE_CLR_SET(hadc->State,
1976 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1977 HAL_ADC_STATE_READY);
1978 }
1979 }
1980
1981 /* Process unlocked */
1982 __HAL_UNLOCK(hadc);
1983
1984 /* Return function status */
1985 return tmp_hal_status;
1986 }
1987
1988 /**
1989 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1990 * @note Interruptions enabled in this function:
1991 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1992 * Each of these interruptions has its dedicated callback function.
1993 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
1994 * is designed for single-ADC mode only. For multimode, the dedicated
1995 * HAL_ADCEx_MultiModeStart_DMA() function must be used.
1996 * @param hadc ADC handle
1997 * @param pData Destination Buffer address.
1998 * @param Length Number of data to be transferred from ADC peripheral to memory
1999 * @retval HAL status.
2000 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)2001 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
2002 {
2003 HAL_StatusTypeDef tmp_hal_status;
2004 #if defined(ADC_MULTIMODE_SUPPORT)
2005 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2006 #endif
2007
2008 /* Check the parameters */
2009 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2010
2011 /* Perform ADC enable and conversion start if no conversion is on going */
2012 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2013 {
2014 /* Process locked */
2015 __HAL_LOCK(hadc);
2016
2017 #if defined(ADC_MULTIMODE_SUPPORT)
2018 /* Ensure that multimode regular conversions are not enabled. */
2019 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
2020 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2021 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2022 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2023 )
2024 #endif
2025 {
2026 /* Enable the ADC peripheral */
2027 tmp_hal_status = ADC_Enable(hadc);
2028
2029 /* Start conversion if ADC is effectively enabled */
2030 if (tmp_hal_status == HAL_OK)
2031 {
2032 /* Set ADC state */
2033 /* - Clear state bitfield related to regular group conversion results */
2034 /* - Set state bitfield related to regular operation */
2035 ADC_STATE_CLR_SET(hadc->State,
2036 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2037 HAL_ADC_STATE_REG_BUSY);
2038
2039 #if defined(ADC_MULTIMODE_SUPPORT)
2040 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
2041 - if ADC instance is master or if multimode feature is not available
2042 - if multimode setting is disabled (ADC instance slave in independent mode) */
2043 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2044 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2045 )
2046 {
2047 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2048 }
2049 #endif
2050
2051 /* Check if a conversion is on going on ADC group injected */
2052 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
2053 {
2054 /* Reset ADC error code fields related to regular conversions only */
2055 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2056 }
2057 else
2058 {
2059 /* Reset all ADC error code fields */
2060 ADC_CLEAR_ERRORCODE(hadc);
2061 }
2062
2063 /* Set the DMA transfer complete callback */
2064 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2065
2066 /* Set the DMA half transfer complete callback */
2067 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2068
2069 /* Set the DMA error callback */
2070 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2071
2072
2073 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
2074 /* ADC start (in case of SW start): */
2075
2076 /* Clear regular group conversion flag and overrun flag */
2077 /* (To ensure of no unknown state from potential previous ADC */
2078 /* operations) */
2079 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2080
2081 /* Process unlocked */
2082 /* Unlock before starting ADC conversions: in case of potential */
2083 /* interruption, to let the process to ADC IRQ Handler. */
2084 __HAL_UNLOCK(hadc);
2085
2086 /* With DMA, overrun event is always considered as an error even if
2087 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
2088 ADC_IT_OVR is enabled. */
2089 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2090
2091 /* Enable ADC DMA mode*/
2092 LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
2093
2094 /* Start the DMA channel */
2095 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2096
2097 /* Enable conversion of regular group. */
2098 /* If software start has been selected, conversion starts immediately. */
2099 /* If external trigger has been selected, conversion will start at next */
2100 /* trigger event. */
2101 /* Start ADC group regular conversion */
2102 LL_ADC_REG_StartConversion(hadc->Instance);
2103 }
2104 else
2105 {
2106 /* Process unlocked */
2107 __HAL_UNLOCK(hadc);
2108 }
2109
2110 }
2111 #if defined(ADC_MULTIMODE_SUPPORT)
2112 else
2113 {
2114 tmp_hal_status = HAL_ERROR;
2115 /* Process unlocked */
2116 __HAL_UNLOCK(hadc);
2117 }
2118 #endif
2119 }
2120 else
2121 {
2122 tmp_hal_status = HAL_BUSY;
2123 }
2124
2125 /* Return function status */
2126 return tmp_hal_status;
2127 }
2128
2129 /**
2130 * @brief Stop ADC conversion of regular group (and injected group in
2131 * case of auto_injection mode), disable ADC DMA transfer, disable
2132 * ADC peripheral.
2133 * @note: ADC peripheral disable is forcing stop of potential
2134 * conversion on ADC group injected. If ADC group injected is under use, it
2135 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2136 * @note Case of multimode enabled (when multimode feature is available):
2137 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
2138 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
2139 * @param hadc ADC handle
2140 * @retval HAL status.
2141 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2142 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
2143 {
2144 HAL_StatusTypeDef tmp_hal_status;
2145
2146 /* Check the parameters */
2147 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2148
2149 /* Process locked */
2150 __HAL_LOCK(hadc);
2151
2152 /* 1. Stop potential ADC group regular conversion on going */
2153 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2154
2155 /* Disable ADC peripheral if conversions are effectively stopped */
2156 if (tmp_hal_status == HAL_OK)
2157 {
2158 /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
2159 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
2160
2161 /* Disable the DMA channel (in case of DMA in circular mode or stop */
2162 /* while DMA transfer is on going) */
2163 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2164 {
2165 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2166
2167 /* Check if DMA channel effectively disabled */
2168 if (tmp_hal_status != HAL_OK)
2169 {
2170 /* Update ADC state machine to error */
2171 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2172 }
2173 }
2174
2175 /* Disable ADC overrun interrupt */
2176 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2177
2178 /* 2. Disable the ADC peripheral */
2179 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2180 /* to keep in memory a potential failing status. */
2181 if (tmp_hal_status == HAL_OK)
2182 {
2183 tmp_hal_status = ADC_Disable(hadc);
2184 }
2185 else
2186 {
2187 (void)ADC_Disable(hadc);
2188 }
2189
2190 /* Check if ADC is effectively disabled */
2191 if (tmp_hal_status == HAL_OK)
2192 {
2193 /* Set ADC state */
2194 ADC_STATE_CLR_SET(hadc->State,
2195 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2196 HAL_ADC_STATE_READY);
2197 }
2198
2199 }
2200
2201 /* Process unlocked */
2202 __HAL_UNLOCK(hadc);
2203
2204 /* Return function status */
2205 return tmp_hal_status;
2206 }
2207
2208 /**
2209 * @brief Get ADC regular group conversion result.
2210 * @note Reading register DR automatically clears ADC flag EOC
2211 * (ADC group regular end of unitary conversion).
2212 * @note This function does not clear ADC flag EOS
2213 * (ADC group regular end of sequence conversion).
2214 * Occurrence of flag EOS rising:
2215 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2216 * to flag EOC.
2217 * - If sequencer is composed of several ranks, during the scan
2218 * sequence flag EOC only is raised, at the end of the scan sequence
2219 * both flags EOC and EOS are raised.
2220 * To clear this flag, either use function:
2221 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2222 * model polling: @ref HAL_ADC_PollForConversion()
2223 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2224 * @param hadc ADC handle
2225 * @retval ADC group regular conversion data
2226 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2227 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
2228 {
2229 /* Check the parameters */
2230 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2231
2232 /* Note: EOC flag is not cleared here by software because automatically */
2233 /* cleared by hardware when reading register DR. */
2234
2235 /* Return ADC converted value */
2236 return hadc->Instance->DR;
2237 }
2238
2239 /**
2240 * @brief Handle ADC interrupt request.
2241 * @param hadc ADC handle
2242 * @retval None
2243 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2244 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
2245 {
2246 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
2247 uint32_t tmp_isr = hadc->Instance->ISR;
2248 uint32_t tmp_ier = hadc->Instance->IER;
2249 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
2250 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
2251 uint32_t tmp_cfgr;
2252 #if defined(ADC_MULTIMODE_SUPPORT)
2253 const ADC_TypeDef *tmpADC_Master;
2254 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2255 #endif
2256
2257 /* Check the parameters */
2258 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2259 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2260
2261 /* ========== Check End of Sampling flag for ADC group regular ========== */
2262 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
2263 {
2264 /* Update state machine on end of sampling status if not in error state */
2265 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2266 {
2267 /* Set ADC state */
2268 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
2269 }
2270
2271 /* End Of Sampling callback */
2272 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2273 hadc->EndOfSamplingCallback(hadc);
2274 #else
2275 HAL_ADCEx_EndOfSamplingCallback(hadc);
2276 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2277
2278 /* Clear regular group conversion flag */
2279 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
2280 }
2281
2282 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
2283 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2284 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
2285 {
2286 /* Update state machine on conversion status if not in error state */
2287 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2288 {
2289 /* Set ADC state */
2290 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2291 }
2292
2293 /* Determine whether any further conversion upcoming on group regular */
2294 /* by external trigger, continuous mode or scan sequence on going */
2295 /* to disable interruption. */
2296 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2297 {
2298 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2299 /* in function of multimode state (for devices with multimode */
2300 /* available). */
2301 #if defined(ADC_MULTIMODE_SUPPORT)
2302 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2303 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2304 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2305 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2306 )
2307 {
2308 /* check CONT bit directly in handle ADC CFGR register */
2309 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2310 }
2311 else
2312 {
2313 /* else need to check Master ADC CONT bit */
2314 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2315 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2316 }
2317 #else
2318 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2319 #endif
2320
2321 /* Carry on if continuous mode is disabled */
2322 if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
2323 {
2324 /* If End of Sequence is reached, disable interrupts */
2325 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2326 {
2327 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2328 /* ADSTART==0 (no conversion on going) */
2329 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2330 {
2331 /* Disable ADC end of sequence conversion interrupt */
2332 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2333 /* HAL_Start_IT(), but is not disabled here because can be used */
2334 /* by overrun IRQ process below. */
2335 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2336
2337 /* Set ADC state */
2338 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2339
2340 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
2341 {
2342 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2343 }
2344 }
2345 else
2346 {
2347 /* Change ADC state to error state */
2348 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2349
2350 /* Set ADC error code to ADC peripheral internal error */
2351 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2352 }
2353 }
2354 }
2355 }
2356
2357 /* Conversion complete callback */
2358 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
2359 /* to determine if conversion has been triggered from EOC or EOS, */
2360 /* possibility to use: */
2361 /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2362 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2363 hadc->ConvCpltCallback(hadc);
2364 #else
2365 HAL_ADC_ConvCpltCallback(hadc);
2366 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2367
2368 /* Clear regular group conversion flag */
2369 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2370 /* conversion flags clear induces the release of the preserved data.*/
2371 /* Therefore, if the preserved data value is needed, it must be */
2372 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2373 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
2374 }
2375
2376 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
2377 if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2378 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
2379 {
2380 /* Update state machine on conversion status if not in error state */
2381 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2382 {
2383 /* Set ADC state */
2384 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2385 }
2386
2387 /* Retrieve ADC configuration */
2388 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
2389 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
2390 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2391 /* in function of multimode state (for devices with multimode */
2392 /* available). */
2393 #if defined(ADC_MULTIMODE_SUPPORT)
2394 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2395 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2396 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
2397 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
2398 )
2399 {
2400 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2401 }
2402 else
2403 {
2404 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2405 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2406 }
2407 #else
2408 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2409 #endif
2410
2411 /* Disable interruption if no further conversion upcoming by injected */
2412 /* external trigger or by automatic injected conversion with regular */
2413 /* group having no further conversion upcoming (same conditions as */
2414 /* regular group interruption disabling above), */
2415 /* and if injected scan sequence is completed. */
2416 if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
2417 {
2418 if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
2419 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
2420 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
2421 {
2422 /* If End of Sequence is reached, disable interrupts */
2423 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2424 {
2425 /* Particular case if injected contexts queue is enabled: */
2426 /* when the last context has been fully processed, JSQR is reset */
2427 /* by the hardware. Even if no injected conversion is planned to come */
2428 /* (queue empty, triggers are ignored), it can start again */
2429 /* immediately after setting a new context (JADSTART is still set). */
2430 /* Therefore, state of HAL ADC injected group is kept to busy. */
2431 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
2432 {
2433 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2434 /* JADSTART==0 (no conversion on going) */
2435 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2436 {
2437 /* Disable ADC end of sequence conversion interrupt */
2438 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2439
2440 /* Set ADC state */
2441 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
2442
2443 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
2444 {
2445 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2446 }
2447 }
2448 else
2449 {
2450 /* Update ADC state machine to error */
2451 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2452
2453 /* Set ADC error code to ADC peripheral internal error */
2454 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2455 }
2456 }
2457 }
2458 }
2459 }
2460
2461 /* Injected Conversion complete callback */
2462 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
2463 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
2464 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
2465 interruption has been triggered by end of conversion or end of
2466 sequence. */
2467 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2468 hadc->InjectedConvCpltCallback(hadc);
2469 #else
2470 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2471 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2472
2473 /* Clear injected group conversion flag */
2474 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2475 }
2476
2477 /* ========== Check Analog watchdog 1 flag ========== */
2478 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
2479 {
2480 /* Set ADC state */
2481 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2482
2483 /* Level out of window 1 callback */
2484 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2485 hadc->LevelOutOfWindowCallback(hadc);
2486 #else
2487 HAL_ADC_LevelOutOfWindowCallback(hadc);
2488 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2489
2490 /* Clear ADC analog watchdog flag */
2491 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2492 }
2493
2494 /* ========== Check analog watchdog 2 flag ========== */
2495 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2496 {
2497 /* Set ADC state */
2498 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2499
2500 /* Level out of window 2 callback */
2501 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2502 hadc->LevelOutOfWindow2Callback(hadc);
2503 #else
2504 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2505 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2506
2507 /* Clear ADC analog watchdog flag */
2508 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2509 }
2510
2511 /* ========== Check analog watchdog 3 flag ========== */
2512 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2513 {
2514 /* Set ADC state */
2515 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2516
2517 /* Level out of window 3 callback */
2518 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2519 hadc->LevelOutOfWindow3Callback(hadc);
2520 #else
2521 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2522 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2523
2524 /* Clear ADC analog watchdog flag */
2525 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2526 }
2527
2528 /* ========== Check Overrun flag ========== */
2529 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2530 {
2531 /* If overrun is set to overwrite previous data (default setting), */
2532 /* overrun event is not considered as an error. */
2533 /* (cf ref manual "Managing conversions without using the DMA and without */
2534 /* overrun ") */
2535 /* Exception for usage with DMA overrun event always considered as an */
2536 /* error. */
2537 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2538 {
2539 overrun_error = 1UL;
2540 }
2541 else
2542 {
2543 /* Check DMA configuration */
2544 #if defined(ADC_MULTIMODE_SUPPORT)
2545 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
2546 {
2547 /* Multimode (when feature is available) is enabled,
2548 Common Control Register MDMA bits must be checked. */
2549 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
2550 {
2551 overrun_error = 1UL;
2552 }
2553 }
2554 else
2555 #endif
2556 {
2557 /* Multimode not set or feature not available or ADC independent */
2558 if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
2559 {
2560 overrun_error = 1UL;
2561 }
2562 }
2563 }
2564
2565 if (overrun_error == 1UL)
2566 {
2567 /* Change ADC state to error state */
2568 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2569
2570 /* Set ADC error code to overrun */
2571 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2572
2573 /* Error callback */
2574 /* Note: In case of overrun, ADC conversion data is preserved until */
2575 /* flag OVR is reset. */
2576 /* Therefore, old ADC conversion data can be retrieved in */
2577 /* function "HAL_ADC_ErrorCallback()". */
2578 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2579 hadc->ErrorCallback(hadc);
2580 #else
2581 HAL_ADC_ErrorCallback(hadc);
2582 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2583 }
2584
2585 /* Clear ADC overrun flag */
2586 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2587 }
2588
2589 /* ========== Check Injected context queue overflow flag ========== */
2590 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
2591 {
2592 /* Change ADC state to overrun state */
2593 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2594
2595 /* Set ADC error code to Injected context queue overflow */
2596 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
2597
2598 /* Clear the Injected context queue overflow flag */
2599 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2600
2601 /* Injected context queue overflow callback */
2602 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2603 hadc->InjectedQueueOverflowCallback(hadc);
2604 #else
2605 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2606 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2607 }
2608
2609 }
2610
2611 /**
2612 * @brief Conversion complete callback in non-blocking mode.
2613 * @param hadc ADC handle
2614 * @retval None
2615 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2616 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2617 {
2618 /* Prevent unused argument(s) compilation warning */
2619 UNUSED(hadc);
2620
2621 /* NOTE : This function should not be modified. When the callback is needed,
2622 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2623 */
2624 }
2625
2626 /**
2627 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2628 * @param hadc ADC handle
2629 * @retval None
2630 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2631 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2632 {
2633 /* Prevent unused argument(s) compilation warning */
2634 UNUSED(hadc);
2635
2636 /* NOTE : This function should not be modified. When the callback is needed,
2637 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2638 */
2639 }
2640
2641 /**
2642 * @brief Analog watchdog 1 callback in non-blocking mode.
2643 * @param hadc ADC handle
2644 * @retval None
2645 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2646 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2647 {
2648 /* Prevent unused argument(s) compilation warning */
2649 UNUSED(hadc);
2650
2651 /* NOTE : This function should not be modified. When the callback is needed,
2652 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2653 */
2654 }
2655
2656 /**
2657 * @brief ADC error callback in non-blocking mode
2658 * (ADC conversion with interruption or transfer by DMA).
2659 * @note In case of error due to overrun when using ADC with DMA transfer
2660 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2661 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2662 * - If needed, restart a new ADC conversion using function
2663 * "HAL_ADC_Start_DMA()"
2664 * (this function is also clearing overrun flag)
2665 * @param hadc ADC handle
2666 * @retval None
2667 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2668 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2669 {
2670 /* Prevent unused argument(s) compilation warning */
2671 UNUSED(hadc);
2672
2673 /* NOTE : This function should not be modified. When the callback is needed,
2674 function HAL_ADC_ErrorCallback must be implemented in the user file.
2675 */
2676 }
2677
2678 /**
2679 * @}
2680 */
2681
2682 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2683 * @brief Peripheral Control functions
2684 *
2685 @verbatim
2686 ===============================================================================
2687 ##### Peripheral Control functions #####
2688 ===============================================================================
2689 [..] This section provides functions allowing to:
2690 (+) Configure channels on regular group
2691 (+) Configure the analog watchdog
2692
2693 @endverbatim
2694 * @{
2695 */
2696
2697 /**
2698 * @brief Configure a channel to be assigned to ADC group regular.
2699 * @note In case of usage of internal measurement channels:
2700 * Vbat/VrefInt/TempSensor/VddCore.
2701 * These internal paths can be disabled using function
2702 * HAL_ADC_DeInit().
2703 * @note Possibility to update parameters on the fly:
2704 * This function initializes channel into ADC group regular,
2705 * following calls to this function can be used to reconfigure
2706 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2707 * without resetting the ADC.
2708 * The setting of these parameters is conditioned to ADC state:
2709 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2710 * @param hadc ADC handle
2711 * @param sConfig Structure of ADC channel assigned to ADC group regular.
2712 * @retval HAL status
2713 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)2714 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
2715 {
2716 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2717 uint32_t tmpOffsetShifted;
2718 uint32_t tmp_config_internal_channel;
2719 __IO uint32_t wait_loop_index = 0UL;
2720 uint32_t tmp_adc_is_conversion_on_going_regular;
2721 uint32_t tmp_adc_is_conversion_on_going_injected;
2722
2723 /* Check the parameters */
2724 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2725 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
2726 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
2727 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
2728 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
2729 /* Check offset range according to oversampling setting */
2730 if (hadc->Init.OversamplingMode == ENABLE)
2731 {
2732 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
2733 }
2734 else
2735 {
2736 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
2737 }
2738
2739 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
2740 ignored (considered as reset) */
2741 assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
2742
2743 /* Verification of channel number */
2744 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
2745 {
2746 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
2747 }
2748 else
2749 {
2750 if (hadc->Instance == ADC1)
2751 {
2752 assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
2753 }
2754 if (hadc->Instance == ADC2)
2755 {
2756 assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
2757 }
2758 }
2759
2760 /* Process locked */
2761 __HAL_LOCK(hadc);
2762
2763 /* Parameters update conditioned to ADC state: */
2764 /* Parameters that can be updated when ADC is disabled or enabled without */
2765 /* conversion on going on regular group: */
2766 /* - Channel number */
2767 /* - Channel rank */
2768 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2769 {
2770 /* ADC channels preselection */
2771 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
2772
2773 /* Set ADC group regular sequence: channel on the selected scan sequence rank */
2774 LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
2775
2776 /* Parameters update conditioned to ADC state: */
2777 /* Parameters that can be updated when ADC is disabled or enabled without */
2778 /* conversion on going on regular group: */
2779 /* - Channel sampling time */
2780 /* - Channel offset */
2781 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2782 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2783 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2784 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2785 )
2786 {
2787 /* Set sampling time of the selected ADC channel */
2788 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2789
2790 /* Configure the offset: offset enable/disable, channel, offset value */
2791
2792 /* Shift the offset with respect to the selected ADC resolution. */
2793 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2794 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
2795
2796 if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
2797 {
2798 /* Set ADC selected offset number */
2799 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
2800
2801 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
2802 /* Set ADC selected offset signed saturation */
2803 LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2804
2805 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
2806 /* Set ADC selected offset right shift */
2807 LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
2808
2809 }
2810 else
2811 {
2812 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
2813 If this is the case, offset OFRx is disabled since
2814 sConfig->OffsetNumber = ADC_OFFSET_NONE. */
2815 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
2816 {
2817 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
2818 }
2819 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
2820 {
2821 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
2822 }
2823 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
2824 {
2825 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
2826 }
2827 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
2828 {
2829 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
2830 }
2831 }
2832 }
2833
2834 /* Parameters update conditioned to ADC state: */
2835 /* Parameters that can be updated only when ADC is disabled: */
2836 /* - Single or differential mode */
2837 /* - Internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
2838 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2839 {
2840 /* Set mode single-ended or differential input of the selected ADC channel */
2841 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
2842
2843 /* Configuration of differential mode */
2844 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
2845 {
2846 /* Set sampling time of the selected ADC channel */
2847 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2848 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2849 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
2850 sConfig->SamplingTime);
2851 }
2852
2853 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore. */
2854 /* If internal channel selected, enable dedicated internal buffers and */
2855 /* paths. */
2856 /* Note: these internal measurement paths can be disabled using */
2857 /* HAL_ADC_DeInit(). */
2858
2859 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
2860 {
2861 /* Configuration of common ADC parameters */
2862
2863 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2864
2865 /* Software is allowed to change common parameters only when all ADCs */
2866 /* of the common group are disabled. */
2867 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2868 {
2869 /* If the requested internal measurement path has already been enabled, */
2870 /* bypass the configuration processing. */
2871 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
2872 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2873 {
2874 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2875 {
2876 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2877
2878 /* Delay for temperature sensor stabilization time */
2879 /* Wait loop initialization and execution */
2880 /* Note: Variable divided by 2 to compensate partially */
2881 /* CPU processing cycles, scaling in us split to not */
2882 /* exceed 32 bits register capacity and handle low frequency. */
2883 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2884 while(wait_loop_index != 0UL)
2885 {
2886 wait_loop_index--;
2887 }
2888 }
2889 }
2890 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2891 {
2892 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2893 {
2894 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2895 }
2896 }
2897 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2898 {
2899 if (ADC_VREFINT_INSTANCE(hadc))
2900 {
2901 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2902 }
2903 }
2904 else if ((sConfig->Channel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL))
2905 {
2906 if (ADC_VDDCORE_INSTANCE(hadc))
2907 {
2908 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_internal_channel);
2909 }
2910 }
2911 else
2912 {
2913 /* nothing to do */
2914 }
2915 }
2916 /* If the requested internal measurement path has already been */
2917 /* enabled and other ADC of the common group are enabled, internal */
2918 /* measurement paths cannot be enabled. */
2919 else
2920 {
2921 /* Update ADC state machine to error */
2922 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2923
2924 tmp_hal_status = HAL_ERROR;
2925 }
2926 }
2927 }
2928 }
2929
2930 /* If a conversion is on going on regular group, no update on regular */
2931 /* channel could be done on neither of the channel configuration structure */
2932 /* parameters. */
2933 else
2934 {
2935 /* Update ADC state machine to error */
2936 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2937
2938 tmp_hal_status = HAL_ERROR;
2939 }
2940
2941 /* Process unlocked */
2942 __HAL_UNLOCK(hadc);
2943
2944 /* Return function status */
2945 return tmp_hal_status;
2946 }
2947
2948 /**
2949 * @brief Configure the analog watchdog.
2950 * @note Possibility to update parameters on the fly:
2951 * This function initializes the selected analog watchdog, successive
2952 * calls to this function can be used to reconfigure some parameters
2953 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2954 * the ADC.
2955 * The setting of these parameters is conditioned to ADC state.
2956 * For parameters constraints, see comments of structure
2957 * "ADC_AnalogWDGConfTypeDef".
2958 * @note On this STM32 series, analog watchdog thresholds cannot be modified
2959 * while ADC conversion is on going.
2960 * @param hadc ADC handle
2961 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
2962 * @retval HAL status
2963 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)2964 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
2965 {
2966 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2967 uint32_t tmpAWDHighThresholdShifted;
2968 uint32_t tmpAWDLowThresholdShifted;
2969 uint32_t tmp_adc_is_conversion_on_going_regular;
2970 uint32_t tmp_adc_is_conversion_on_going_injected;
2971
2972 /* Check the parameters */
2973 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2974 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
2975 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
2976 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
2977
2978 if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
2979 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
2980 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
2981 {
2982 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
2983 }
2984
2985 /* Verify thresholds range */
2986 if (hadc->Init.OversamplingMode == ENABLE)
2987 {
2988 /* Case of oversampling enabled: thresholds are compared to oversampling
2989 intermediate computation (after ratio, before shift application) */
2990 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
2991 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
2992 }
2993 else
2994 {
2995 /* Verify if thresholds are within the selected ADC resolution */
2996 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
2997 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
2998 }
2999
3000 /* Process locked */
3001 __HAL_LOCK(hadc);
3002
3003 /* Parameters update conditioned to ADC state: */
3004 /* Parameters that can be updated when ADC is disabled or enabled without */
3005 /* conversion on going on ADC groups regular and injected: */
3006 /* - Analog watchdog channels */
3007 /* - Analog watchdog thresholds */
3008 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3009 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3010 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
3011 && (tmp_adc_is_conversion_on_going_injected == 0UL)
3012 )
3013 {
3014 /* Analog watchdog configuration */
3015 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
3016 {
3017 /* Configuration of analog watchdog: */
3018 /* - Set the analog watchdog enable mode: one or overall group of */
3019 /* channels, on groups regular and-or injected. */
3020 switch (AnalogWDGConfig->WatchdogMode)
3021 {
3022 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3023 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3024 LL_ADC_GROUP_REGULAR));
3025 break;
3026
3027 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3028 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3029 LL_ADC_GROUP_INJECTED));
3030 break;
3031
3032 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3033 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3034 LL_ADC_GROUP_REGULAR_INJECTED));
3035 break;
3036
3037 case ADC_ANALOGWATCHDOG_ALL_REG:
3038 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
3039 break;
3040
3041 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3042 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
3043 break;
3044
3045 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3046 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3047 break;
3048
3049 default: /* ADC_ANALOGWATCHDOG_NONE */
3050 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
3051 break;
3052 }
3053
3054 /* Shift the offset in function of the selected ADC resolution: */
3055 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
3056 /* are set to 0 */
3057 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3058 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3059
3060 /* Set the high and low thresholds */
3061 MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmpAWDLowThresholdShifted);
3062 MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmpAWDHighThresholdShifted);
3063
3064 /* Update state, clear previous result related to AWD1 */
3065 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3066
3067 /* Clear flag ADC analog watchdog */
3068 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3069 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3070 /* (in case left enabled by previous ADC operations). */
3071 LL_ADC_ClearFlag_AWD1(hadc->Instance);
3072
3073 /* Configure ADC analog watchdog interrupt */
3074 if (AnalogWDGConfig->ITMode == ENABLE)
3075 {
3076 LL_ADC_EnableIT_AWD1(hadc->Instance);
3077 }
3078 else
3079 {
3080 LL_ADC_DisableIT_AWD1(hadc->Instance);
3081 }
3082 }
3083 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
3084 else
3085 {
3086 switch (AnalogWDGConfig->WatchdogMode)
3087 {
3088 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3089 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3090 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3091 /* Update AWD by bitfield to keep the possibility to monitor */
3092 /* several channels by successive calls of this function. */
3093 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3094 {
3095 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3096 }
3097 else
3098 {
3099 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3100 }
3101 break;
3102
3103 case ADC_ANALOGWATCHDOG_ALL_REG:
3104 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3105 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3106 /* Update AWD by bitfield to keep the possibility to monitor */
3107 /* several channels by successive calls of this function. */
3108 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3109 {
3110 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3111 }
3112 else
3113 {
3114 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3115 }
3116 break;
3117
3118 default: /* ADC_ANALOGWATCHDOG_NONE */
3119 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
3120 break;
3121 }
3122
3123 /* Shift the thresholds in function of the selected ADC resolution */
3124 /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
3125 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3126 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3127
3128 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3129 {
3130 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3131 MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmpAWDLowThresholdShifted);
3132 MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmpAWDHighThresholdShifted);
3133 }
3134 else
3135 {
3136 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3137 MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmpAWDLowThresholdShifted);
3138 MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmpAWDHighThresholdShifted);
3139 }
3140
3141 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3142 {
3143 /* Update state, clear previous result related to AWD2 */
3144 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3145
3146 /* Clear flag ADC analog watchdog */
3147 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3148 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3149 /* (in case left enabled by previous ADC operations). */
3150 LL_ADC_ClearFlag_AWD2(hadc->Instance);
3151
3152 /* Configure ADC analog watchdog interrupt */
3153 if (AnalogWDGConfig->ITMode == ENABLE)
3154 {
3155 LL_ADC_EnableIT_AWD2(hadc->Instance);
3156 }
3157 else
3158 {
3159 LL_ADC_DisableIT_AWD2(hadc->Instance);
3160 }
3161 }
3162 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
3163 else
3164 {
3165 /* Update state, clear previous result related to AWD3 */
3166 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3167
3168 /* Clear flag ADC analog watchdog */
3169 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3170 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3171 /* (in case left enabled by previous ADC operations). */
3172 LL_ADC_ClearFlag_AWD3(hadc->Instance);
3173
3174 /* Configure ADC analog watchdog interrupt */
3175 if (AnalogWDGConfig->ITMode == ENABLE)
3176 {
3177 LL_ADC_EnableIT_AWD3(hadc->Instance);
3178 }
3179 else
3180 {
3181 LL_ADC_DisableIT_AWD3(hadc->Instance);
3182 }
3183 }
3184 }
3185
3186 }
3187 /* If a conversion is on going on ADC group regular or injected, no update */
3188 /* could be done on neither of the AWD configuration structure parameters. */
3189 else
3190 {
3191 /* Update ADC state machine to error */
3192 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3193
3194 tmp_hal_status = HAL_ERROR;
3195 }
3196 /* Process unlocked */
3197 __HAL_UNLOCK(hadc);
3198
3199 /* Return function status */
3200 return tmp_hal_status;
3201 }
3202
3203
3204 /**
3205 * @}
3206 */
3207
3208 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
3209 * @brief ADC Peripheral State functions
3210 *
3211 @verbatim
3212 ===============================================================================
3213 ##### Peripheral state and errors functions #####
3214 ===============================================================================
3215 [..]
3216 This subsection provides functions to get in run-time the status of the
3217 peripheral.
3218 (+) Check the ADC state
3219 (+) Check the ADC error code
3220
3221 @endverbatim
3222 * @{
3223 */
3224
3225 /**
3226 * @brief Return the ADC handle state.
3227 * @note ADC state machine is managed by bitfields, ADC status must be
3228 * compared with states bits.
3229 * For example:
3230 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
3231 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
3232 * @param hadc ADC handle
3233 * @retval ADC handle state (bitfield on 32 bits)
3234 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)3235 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
3236 {
3237 /* Check the parameters */
3238 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3239
3240 /* Return ADC handle state */
3241 return hadc->State;
3242 }
3243
3244 /**
3245 * @brief Return the ADC error code.
3246 * @param hadc ADC handle
3247 * @retval ADC error code (bitfield on 32 bits)
3248 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)3249 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
3250 {
3251 /* Check the parameters */
3252 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3253
3254 return hadc->ErrorCode;
3255 }
3256
3257 /**
3258 * @}
3259 */
3260
3261 /**
3262 * @}
3263 */
3264
3265 /** @defgroup ADC_Private_Functions ADC Private Functions
3266 * @{
3267 */
3268
3269 /**
3270 * @brief Stop ADC conversion.
3271 * @param hadc ADC handle
3272 * @param ConversionGroup ADC group regular and/or injected.
3273 * This parameter can be one of the following values:
3274 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
3275 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
3276 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
3277 * @retval HAL status.
3278 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)3279 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
3280 {
3281 uint32_t tickstart;
3282 uint32_t Conversion_Timeout_CPU_cycles = 0UL;
3283 uint32_t conversion_group_reassigned = ConversionGroup;
3284 uint32_t tmp_ADC_CR_ADSTART_JADSTART;
3285 uint32_t tmp_adc_is_conversion_on_going_regular;
3286 uint32_t tmp_adc_is_conversion_on_going_injected;
3287
3288 /* Check the parameters */
3289 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3290 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
3291
3292 /* Verification if ADC is not already stopped (on regular and injected */
3293 /* groups) to bypass this function if not needed. */
3294 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3295 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3296 if ((tmp_adc_is_conversion_on_going_regular != 0UL)
3297 || (tmp_adc_is_conversion_on_going_injected != 0UL)
3298 )
3299 {
3300 /* Particular case of continuous auto-injection mode combined with */
3301 /* auto-delay mode. */
3302 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
3303 /* injected group stop ADC_CR_JADSTP). */
3304 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
3305 /* (see reference manual). */
3306 if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
3307 && (hadc->Init.ContinuousConvMode == ENABLE)
3308 && (hadc->Init.LowPowerAutoWait == ENABLE)
3309 )
3310 {
3311 /* Use stop of regular group */
3312 conversion_group_reassigned = ADC_REGULAR_GROUP;
3313
3314 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
3315 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
3316 {
3317 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
3318 {
3319 /* Update ADC state machine to error */
3320 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3321
3322 /* Set ADC error code to ADC peripheral internal error */
3323 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3324
3325 return HAL_ERROR;
3326 }
3327 Conversion_Timeout_CPU_cycles ++;
3328 }
3329
3330 /* Clear JEOS */
3331 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
3332 }
3333
3334 /* Stop potential conversion on going on ADC group regular */
3335 if (conversion_group_reassigned != ADC_INJECTED_GROUP)
3336 {
3337 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
3338 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
3339 {
3340 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3341 {
3342 /* Stop ADC group regular conversion */
3343 LL_ADC_REG_StopConversion(hadc->Instance);
3344 }
3345 }
3346 }
3347
3348 /* Stop potential conversion on going on ADC group injected */
3349 if (conversion_group_reassigned != ADC_REGULAR_GROUP)
3350 {
3351 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
3352 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
3353 {
3354 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3355 {
3356 /* Stop ADC group injected conversion */
3357 LL_ADC_INJ_StopConversion(hadc->Instance);
3358 }
3359 }
3360 }
3361
3362 /* Selection of start and stop bits with respect to the regular or injected group */
3363 switch (conversion_group_reassigned)
3364 {
3365 case ADC_REGULAR_INJECTED_GROUP:
3366 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
3367 break;
3368 case ADC_INJECTED_GROUP:
3369 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
3370 break;
3371 /* Case ADC_REGULAR_GROUP only*/
3372 default:
3373 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
3374 break;
3375 }
3376
3377 /* Wait for conversion effectively stopped */
3378 tickstart = HAL_GetTick();
3379
3380 while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3381 {
3382 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
3383 {
3384 /* Update ADC state machine to error */
3385 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3386
3387 /* Set ADC error code to ADC peripheral internal error */
3388 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3389
3390 return HAL_ERROR;
3391 }
3392 }
3393
3394 }
3395
3396 /* Return HAL status */
3397 return HAL_OK;
3398 }
3399
3400 /**
3401 * @brief Enable the selected ADC.
3402 * @note Prerequisite condition to use this function: ADC must be disabled
3403 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
3404 * @param hadc ADC handle
3405 * @retval HAL status.
3406 */
ADC_Enable(ADC_HandleTypeDef * hadc)3407 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
3408 {
3409 uint32_t tickstart;
3410
3411 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
3412 /* enabling phase not yet completed: flag ADC ready not yet set). */
3413 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
3414 /* causes: ADC clock not running, ...). */
3415 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3416 {
3417 /* Check if conditions to enable the ADC are fulfilled */
3418 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
3419 | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
3420 {
3421 /* Update ADC state machine to error */
3422 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3423
3424 /* Set ADC error code to ADC peripheral internal error */
3425 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3426
3427 return HAL_ERROR;
3428 }
3429
3430 /* Enable the ADC peripheral */
3431 LL_ADC_Enable(hadc->Instance);
3432
3433 /* Wait for ADC effectively enabled */
3434 tickstart = HAL_GetTick();
3435
3436 #if defined(ADC_MULTIMODE_SUPPORT)
3437 /* Poll for ADC ready flag raised except case of multimode enabled
3438 and ADC slave selected. */
3439 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
3440 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
3441 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
3442 )
3443 {
3444 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3445 {
3446 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
3447 has been cleared (after a calibration), ADEN bit is reset by the
3448 calibration logic.
3449 The workaround is to continue setting ADEN until ADRDY is becomes 1.
3450 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
3451 4 ADC clock cycle duration */
3452 /* Note: Test of ADC enabled required due to hardware constraint to */
3453 /* not enable ADC if already enabled. */
3454 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3455 {
3456 LL_ADC_Enable(hadc->Instance);
3457 }
3458
3459 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
3460 {
3461 /* Update ADC state machine to error */
3462 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3463
3464 /* Set ADC error code to ADC peripheral internal error */
3465 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3466
3467 return HAL_ERROR;
3468 }
3469 }
3470 }
3471 #endif
3472 }
3473
3474 /* Return HAL status */
3475 return HAL_OK;
3476 }
3477
3478 /**
3479 * @brief Disable the selected ADC.
3480 * @note Prerequisite condition to use this function: ADC conversions must be
3481 * stopped.
3482 * @param hadc ADC handle
3483 * @retval HAL status.
3484 */
ADC_Disable(ADC_HandleTypeDef * hadc)3485 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
3486 {
3487 uint32_t tickstart;
3488 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
3489
3490 /* Verification if ADC is not already disabled: */
3491 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
3492 /* disabled. */
3493 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
3494 && (tmp_adc_is_disable_on_going == 0UL)
3495 )
3496 {
3497 /* Check if conditions to disable the ADC are fulfilled */
3498 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
3499 {
3500 /* Disable the ADC peripheral */
3501 LL_ADC_Disable(hadc->Instance);
3502 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
3503 }
3504 else
3505 {
3506 /* Update ADC state machine to error */
3507 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3508
3509 /* Set ADC error code to ADC peripheral internal error */
3510 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3511
3512 return HAL_ERROR;
3513 }
3514
3515 /* Wait for ADC effectively disabled */
3516 /* Get tick count */
3517 tickstart = HAL_GetTick();
3518
3519 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3520 {
3521 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
3522 {
3523 /* Update ADC state machine to error */
3524 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3525
3526 /* Set ADC error code to ADC peripheral internal error */
3527 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3528
3529 return HAL_ERROR;
3530 }
3531 }
3532 }
3533
3534 /* Return HAL status */
3535 return HAL_OK;
3536 }
3537
3538 /**
3539 * @brief DMA transfer complete callback.
3540 * @param hdma pointer to DMA handle.
3541 * @retval None
3542 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)3543 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
3544 {
3545 /* Retrieve ADC handle corresponding to current DMA handle */
3546 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3547
3548 /* Update state machine on conversion status if not in error state */
3549 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
3550 {
3551 /* Set ADC state */
3552 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3553
3554 /* Determine whether any further conversion upcoming on group regular */
3555 /* by external trigger, continuous mode or scan sequence on going */
3556 /* to disable interruption. */
3557 /* Is it the end of the regular sequence ? */
3558 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
3559 {
3560 /* Are conversions software-triggered ? */
3561 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
3562 {
3563 /* Is CONT bit set ? */
3564 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
3565 {
3566 /* CONT bit is not set, no more conversions expected */
3567 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3568 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3569 {
3570 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3571 }
3572 }
3573 }
3574 }
3575 else
3576 {
3577 /* DMA End of Transfer interrupt was triggered but conversions sequence
3578 is not over. If DMACFG is set to 0, conversions are stopped. */
3579 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
3580 {
3581 /* DMACFG bit is not set, conversions are stopped. */
3582 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3583 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3584 {
3585 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3586 }
3587 }
3588 }
3589
3590 /* Conversion complete callback */
3591 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3592 hadc->ConvCpltCallback(hadc);
3593 #else
3594 HAL_ADC_ConvCpltCallback(hadc);
3595 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3596 }
3597 else /* DMA and-or internal error occurred */
3598 {
3599 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3600 {
3601 /* Call HAL ADC Error Callback function */
3602 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3603 hadc->ErrorCallback(hadc);
3604 #else
3605 HAL_ADC_ErrorCallback(hadc);
3606 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3607 }
3608 else
3609 {
3610 /* Call ADC DMA error callback */
3611 hadc->DMA_Handle->XferErrorCallback(hdma);
3612 }
3613 }
3614 }
3615
3616 /**
3617 * @brief DMA half transfer complete callback.
3618 * @param hdma pointer to DMA handle.
3619 * @retval None
3620 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3621 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3622 {
3623 /* Retrieve ADC handle corresponding to current DMA handle */
3624 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3625
3626 /* Half conversion callback */
3627 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3628 hadc->ConvHalfCpltCallback(hadc);
3629 #else
3630 HAL_ADC_ConvHalfCpltCallback(hadc);
3631 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3632 }
3633
3634 /**
3635 * @brief DMA error callback.
3636 * @param hdma pointer to DMA handle.
3637 * @retval None
3638 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3639 void ADC_DMAError(DMA_HandleTypeDef *hdma)
3640 {
3641 /* Retrieve ADC handle corresponding to current DMA handle */
3642 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3643
3644 /* Set ADC state */
3645 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3646
3647 /* Set ADC error code to DMA error */
3648 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3649
3650 /* Error callback */
3651 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3652 hadc->ErrorCallback(hadc);
3653 #else
3654 HAL_ADC_ErrorCallback(hadc);
3655 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3656 }
3657
3658 /**
3659 * @brief Configure boost mode of selected ADC.
3660 * @note Prerequisite condition to use this function: ADC conversions must be
3661 * stopped.
3662 * @param hadc ADC handle
3663 * @retval None.
3664 */
ADC_ConfigureBoostMode(ADC_HandleTypeDef * hadc)3665 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
3666 {
3667 uint32_t freq;
3668 if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
3669 {
3670 freq = HAL_RCC_GetHCLK2Freq();
3671 switch(hadc->Init.ClockPrescaler)
3672 {
3673 case ADC_CLOCK_SYNC_PCLK_DIV1:
3674 case ADC_CLOCK_SYNC_PCLK_DIV2:
3675 freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
3676 break;
3677 case ADC_CLOCK_SYNC_PCLK_DIV4:
3678 freq /= 4UL;
3679 break;
3680 default:
3681 break;
3682 }
3683 }
3684 else
3685 {
3686 freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
3687 switch(hadc->Init.ClockPrescaler)
3688 {
3689 case ADC_CLOCK_ASYNC_DIV2:
3690 case ADC_CLOCK_ASYNC_DIV4:
3691 case ADC_CLOCK_ASYNC_DIV6:
3692 case ADC_CLOCK_ASYNC_DIV8:
3693 case ADC_CLOCK_ASYNC_DIV10:
3694 case ADC_CLOCK_ASYNC_DIV12:
3695 freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
3696 break;
3697 case ADC_CLOCK_ASYNC_DIV16:
3698 freq /= 16UL;
3699 break;
3700 case ADC_CLOCK_ASYNC_DIV32:
3701 freq /= 32UL;
3702 break;
3703 case ADC_CLOCK_ASYNC_DIV64:
3704 freq /= 64UL;
3705 break;
3706 case ADC_CLOCK_ASYNC_DIV128:
3707 freq /= 128UL;
3708 break;
3709 case ADC_CLOCK_ASYNC_DIV256:
3710 freq /= 256UL;
3711 break;
3712 default:
3713 break;
3714 }
3715 }
3716
3717 if (freq > 20000000UL)
3718 {
3719 SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
3720 }
3721 else
3722 {
3723 CLEAR_BIT(hadc->Instance->CR, 0);
3724 }
3725 }
3726
3727 /**
3728 * @}
3729 */
3730
3731 #endif /* HAL_ADC_MODULE_ENABLED */
3732 /**
3733 * @}
3734 */
3735
3736 /**
3737 * @}
3738 */
3739
3740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3741