1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_RTC_H 10 #define HPM_RTC_H 11 12 typedef struct { 13 __RW uint32_t SECOND; /* 0x0: Second counter */ 14 __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ 15 __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ 16 __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ 17 __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ 18 __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ 19 __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ 20 __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ 21 __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ 22 __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ 23 } RTC_Type; 24 25 26 /* Bitfield definition for register: SECOND */ 27 /* 28 * SECOND (RW) 29 * 30 * second counter 31 */ 32 #define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) 33 #define RTC_SECOND_SECOND_SHIFT (0U) 34 #define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) 35 #define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) 36 37 /* Bitfield definition for register: SUBSEC */ 38 /* 39 * SUBSEC (RO) 40 * 41 * sub second counter 42 */ 43 #define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) 44 #define RTC_SUBSEC_SUBSEC_SHIFT (0U) 45 #define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) 46 47 /* Bitfield definition for register: SEC_SNAP */ 48 /* 49 * SEC_SNAP (RW) 50 * 51 * second snap shot, write to take snap shot 52 */ 53 #define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) 54 #define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) 55 #define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) 56 #define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) 57 58 /* Bitfield definition for register: SUB_SNAP */ 59 /* 60 * SUB_SNAP (RW) 61 * 62 * sub second snap shot, write to take snap shot 63 */ 64 #define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) 65 #define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) 66 #define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) 67 #define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) 68 69 /* Bitfield definition for register: ALARM0 */ 70 /* 71 * ALARM (RW) 72 * 73 * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC 74 */ 75 #define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) 76 #define RTC_ALARM0_ALARM_SHIFT (0U) 77 #define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) 78 #define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) 79 80 /* Bitfield definition for register: ALARM0_INC */ 81 /* 82 * INCREASE (RW) 83 * 84 * adder when ARLAM0 happen, helps to create periodical alarm 85 */ 86 #define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) 87 #define RTC_ALARM0_INC_INCREASE_SHIFT (0U) 88 #define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) 89 #define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) 90 91 /* Bitfield definition for register: ALARM1 */ 92 /* 93 * ALARM (RW) 94 * 95 * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC 96 */ 97 #define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) 98 #define RTC_ALARM1_ALARM_SHIFT (0U) 99 #define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) 100 #define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) 101 102 /* Bitfield definition for register: ALARM1_INC */ 103 /* 104 * INCREASE (RW) 105 * 106 * adder when ARLAM0 happen, helps to create periodical alarm 107 */ 108 #define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) 109 #define RTC_ALARM1_INC_INCREASE_SHIFT (0U) 110 #define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) 111 #define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) 112 113 /* Bitfield definition for register: ALARM_FLAG */ 114 /* 115 * ALARM1 (RW) 116 * 117 * alarm1 happen 118 */ 119 #define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) 120 #define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) 121 #define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) 122 #define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) 123 124 /* 125 * ALARM0 (RW) 126 * 127 * alarm0 happen 128 */ 129 #define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) 130 #define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) 131 #define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) 132 #define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) 133 134 /* Bitfield definition for register: ALARM_EN */ 135 /* 136 * ENABLE1 (RW) 137 * 138 * alarm1 mask 139 * 0: alarm1 disabled 140 * 1: alarm1 enabled 141 */ 142 #define RTC_ALARM_EN_ENABLE1_MASK (0x2U) 143 #define RTC_ALARM_EN_ENABLE1_SHIFT (1U) 144 #define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) 145 #define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) 146 147 /* 148 * ENABLE0 (RW) 149 * 150 * alarm0 mask 151 * 0: alarm0 disabled 152 * 1: alarm0 enabled 153 */ 154 #define RTC_ALARM_EN_ENABLE0_MASK (0x1U) 155 #define RTC_ALARM_EN_ENABLE0_SHIFT (0U) 156 #define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) 157 #define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) 158 159 160 161 162 #endif /* HPM_RTC_H */ 163