1 /* 2 * include/linux/amlogic/media/registers/regs/dos_regs.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef DOS_REGS_HEADERS__ 19 #define DOS_REGS_HEADERS__ 20 21 22 23 #define MC_CTRL_REG 0x0900 24 #define MC_MB_INFO 0x0901 25 #define MC_PIC_INFO 0x0902 26 #define MC_HALF_PEL_ONE 0x0903 27 #define MC_HALF_PEL_TWO 0x0904 28 #define POWER_CTL_MC 0x0905 29 #define MC_CMD 0x0906 30 #define MC_CTRL0 0x0907 31 #define MC_PIC_W_H 0x0908 32 #define MC_STATUS0 0x0909 33 #define MC_STATUS1 0x090a 34 #define MC_CTRL1 0x090b 35 #define MC_MIX_RATIO0 0x090c 36 #define MC_MIX_RATIO1 0x090d 37 #define MC_DP_MB_XY 0x090e 38 #define MC_OM_MB_XY 0x090f 39 #define PSCALE_RST 0x0910 40 #define PSCALE_CTRL 0x0911 41 #define PSCALE_PICI_W 0x912 42 #define PSCALE_PICI_H 0x913 43 #define PSCALE_PICO_W 0x914 44 #define PSCALE_PICO_H 0x915 45 #define PSCALE_BMEM_ADDR 0x091f 46 #define PSCALE_BMEM_DAT 0x0920 47 48 #define PSCALE_RBUF_START_BLKX 0x925 49 #define PSCALE_RBUF_START_BLKY 0x926 50 #define PSCALE_PICO_SHIFT_XY 0x928 51 #define PSCALE_CTRL1 0x929 52 #define PSCALE_SRCKEY_CTRL0 0x92a 53 #define PSCALE_SRCKEY_CTRL1 0x92b 54 #define PSCALE_CANVAS_RD_ADDR 0x92c 55 #define PSCALE_CANVAS_WR_ADDR 0x92d 56 57 58 /**/ 59 #define MC_MPORT_CTRL 0x0940 60 #define MC_MPORT_DAT 0x0941 61 #define MC_WT_PRED_CTRL 0x0942 62 #define MC_MBBOT_ST_EVEN_ADDR 0x0944 63 #define MC_MBBOT_ST_ODD_ADDR 0x0945 64 #define MC_DPDN_MB_XY 0x0946 65 #define MC_OMDN_MB_XY 0x0947 66 #define MC_HCMDBUF_H 0x0948 67 #define MC_HCMDBUF_L 0x0949 68 #define MC_HCMD_H 0x094a 69 #define MC_HCMD_L 0x094b 70 #define MC_IDCT_DAT 0x094c 71 #define MC_CTRL_GCLK_CTRL 0x094d 72 #define MC_OTHER_GCLK_CTRL 0x094e 73 #define MC_CTRL2 0x094f 74 #define MDEC_PIC_DC_MUX_CTRL 0x98d 75 #define MDEC_PIC_DC_CTRL 0x098e 76 #define MDEC_PIC_DC_STATUS 0x098f 77 #define ANC0_CANVAS_ADDR 0x0990 78 #define ANC1_CANVAS_ADDR 0x0991 79 #define ANC2_CANVAS_ADDR 0x0992 80 #define ANC3_CANVAS_ADDR 0x0993 81 #define ANC4_CANVAS_ADDR 0x0994 82 #define ANC5_CANVAS_ADDR 0x0995 83 #define ANC6_CANVAS_ADDR 0x0996 84 #define ANC7_CANVAS_ADDR 0x0997 85 #define ANC8_CANVAS_ADDR 0x0998 86 #define ANC9_CANVAS_ADDR 0x0999 87 #define ANC10_CANVAS_ADDR 0x099a 88 #define ANC11_CANVAS_ADDR 0x099b 89 #define ANC12_CANVAS_ADDR 0x099c 90 #define ANC13_CANVAS_ADDR 0x099d 91 #define ANC14_CANVAS_ADDR 0x099e 92 #define ANC15_CANVAS_ADDR 0x099f 93 #define ANC16_CANVAS_ADDR 0x09a0 94 #define ANC17_CANVAS_ADDR 0x09a1 95 #define ANC18_CANVAS_ADDR 0x09a2 96 #define ANC19_CANVAS_ADDR 0x09a3 97 #define ANC20_CANVAS_ADDR 0x09a4 98 #define ANC21_CANVAS_ADDR 0x09a5 99 #define ANC22_CANVAS_ADDR 0x09a6 100 #define ANC23_CANVAS_ADDR 0x09a7 101 #define ANC24_CANVAS_ADDR 0x09a8 102 #define ANC25_CANVAS_ADDR 0x09a9 103 #define ANC26_CANVAS_ADDR 0x09aa 104 #define ANC27_CANVAS_ADDR 0x09ab 105 #define ANC28_CANVAS_ADDR 0x09ac 106 #define ANC29_CANVAS_ADDR 0x09ad 107 #define ANC30_CANVAS_ADDR 0x09ae 108 #define ANC31_CANVAS_ADDR 0x09af 109 #define DBKR_CANVAS_ADDR 0x09b0 110 #define DBKW_CANVAS_ADDR 0x09b1 111 #define REC_CANVAS_ADDR 0x09b2 112 #define CURR_CANVAS_CTRL 0x09b3 113 #define MDEC_PIC_DC_THRESH 0x09b8 114 #define MDEC_PICR_BUF_STATUS 0x09b9 115 #define MDEC_PICW_BUF_STATUS 0x09ba 116 #define MCW_DBLK_WRRSP_CNT 0x09bb 117 #define MC_MBBOT_WRRSP_CNT 0x09bc 118 #define MDEC_PICW_BUF2_STATUS 0x09bd 119 #define WRRSP_FIFO_PICW_DBK 0x09be 120 #define WRRSP_FIFO_PICW_MC 0x09bf 121 #define AV_SCRATCH_0 0x09c0 122 #define AV_SCRATCH_1 0x09c1 123 #define AV_SCRATCH_2 0x09c2 124 #define AV_SCRATCH_3 0x09c3 125 #define AV_SCRATCH_4 0x09c4 126 #define AV_SCRATCH_5 0x09c5 127 #define AV_SCRATCH_6 0x09c6 128 #define AV_SCRATCH_7 0x09c7 129 #define AV_SCRATCH_8 0x09c8 130 #define AV_SCRATCH_9 0x09c9 131 #define AV_SCRATCH_A 0x09ca 132 #define AV_SCRATCH_B 0x09cb 133 #define AV_SCRATCH_C 0x09cc 134 #define AV_SCRATCH_D 0x09cd 135 #define AV_SCRATCH_E 0x09ce 136 #define AV_SCRATCH_F 0x09cf 137 #define AV_SCRATCH_G 0x09d0 138 #define AV_SCRATCH_H 0x09d1 139 #define AV_SCRATCH_I 0x09d2 140 #define AV_SCRATCH_J 0x09d3 141 #define AV_SCRATCH_K 0x09d4 142 #define AV_SCRATCH_L 0x09d5 143 #define AV_SCRATCH_M 0x09d6 144 #define AV_SCRATCH_N 0x09d7 145 #define WRRSP_CO_MB 0x09d8 146 #define WRRSP_DCAC 0x09d9 147 /*add from M8M2*/ 148 #define WRRSP_VLD 0x09da 149 #define MDEC_DOUBLEW_CFG0 0x09db 150 #define MDEC_DOUBLEW_CFG1 0x09dc 151 #define MDEC_DOUBLEW_CFG2 0x09dd 152 #define MDEC_DOUBLEW_CFG3 0x09de 153 #define MDEC_DOUBLEW_CFG4 0x09df 154 #define MDEC_DOUBLEW_CFG5 0x09e0 155 #define MDEC_DOUBLEW_CFG6 0x09e1 156 #define MDEC_DOUBLEW_CFG7 0x09e2 157 #define MDEC_DOUBLEW_STATUS 0x09e3 158 #define MDEC_EXTIF_CFG0 0x09e4 159 #define MDEC_EXTIF_CFG1 0x09e5 160 161 162 /**/ 163 #define DBLK_RST 0x0950 164 #define DBLK_CTRL 0x0951 165 #define DBLK_MB_WID_HEIGHT 0x0952 166 #define DBLK_STATUS 0x0953 167 #define DBLK_CMD_CTRL 0x0954 168 #define MCRCC_CTL1 0x0980 169 #define MCRCC_CTL2 0x0981 170 #define MCRCC_CTL3 0x0982 171 #define GCLK_EN 0x0983 172 #define MDEC_SW_RESET 0x0984 173 #define VLD_STATUS_CTRL 0x0c00 174 #define MPEG1_2_REG 0x0c01 175 #define F_CODE_REG 0x0c02 176 #define PIC_HEAD_INFO 0x0c03 177 #define SLICE_VER_POS_PIC_TYPE 0x0c04 178 #define QP_VALUE_REG 0x0c05 179 #define MBA_INC 0x0c06 180 #define MB_MOTION_MODE 0x0c07 181 #define POWER_CTL_VLD 0x0c08 182 #define MB_WIDTH 0x0c09 183 #define SLICE_QP 0x0c0a 184 #define PRE_START_CODE 0x0c0b 185 #define SLICE_START_BYTE_01 0x0c0c 186 #define SLICE_START_BYTE_23 0x0c0d 187 #define RESYNC_MARKER_LENGTH 0x0c0e 188 #define DECODER_BUFFER_INFO 0x0c0f 189 #define FST_FOR_MV_X 0x0c10 190 #define FST_FOR_MV_Y 0x0c11 191 #define SCD_FOR_MV_X 0x0c12 192 #define SCD_FOR_MV_Y 0x0c13 193 #define FST_BAK_MV_X 0x0c14 194 #define FST_BAK_MV_Y 0x0c15 195 #define SCD_BAK_MV_X 0x0c16 196 #define SCD_BAK_MV_Y 0x0c17 197 #define VLD_DECODE_CONTROL 0x0c18 198 #define VLD_REVERVED_19 0x0c19 199 #define VIFF_BIT_CNT 0x0c1a 200 #define BYTE_ALIGN_PEAK_HI 0x0c1b 201 #define BYTE_ALIGN_PEAK_LO 0x0c1c 202 #define NEXT_ALIGN_PEAK 0x0c1d 203 #define VC1_CONTROL_REG 0x0c1e 204 #define PMV1_X 0x0c20 205 #define PMV1_Y 0x0c21 206 #define PMV2_X 0x0c22 207 #define PMV2_Y 0x0c23 208 #define PMV3_X 0x0c24 209 #define PMV3_Y 0x0c25 210 #define PMV4_X 0x0c26 211 #define PMV4_Y 0x0c27 212 #define M4_TABLE_SELECT 0x0c28 213 #define M4_CONTROL_REG 0x0c29 214 #define BLOCK_NUM 0x0c2a 215 #define PATTERN_CODE 0x0c2b 216 #define MB_INFO 0x0c2c 217 #define VLD_DC_PRED 0x0c2d 218 #define VLD_ERROR_MASK 0x0c2e 219 #define VLD_DC_PRED_C 0x0c2f 220 #define LAST_SLICE_MV_ADDR 0x0c30 221 #define LAST_MVX 0x0c31 222 #define LAST_MVY 0x0c32 223 #define VLD_C38 0x0c38 224 #define VLD_C39 0x0c39 225 #define VLD_STATUS 0x0c3a 226 #define VLD_SHIFT_STATUS 0x0c3b 227 #define VOFF_STATUS 0x0c3c 228 #define VLD_C3D 0x0c3d 229 #define VLD_DBG_INDEX 0x0c3e 230 #define VLD_DBG_DATA 0x0c3f 231 #define VLD_MEM_VIFIFO_START_PTR 0x0c40 232 #define VLD_MEM_VIFIFO_CURR_PTR 0x0c41 233 #define VLD_MEM_VIFIFO_END_PTR 0x0c42 234 #define VLD_MEM_VIFIFO_BYTES_AVAIL 0x0c43 235 #define VLD_MEM_VIFIFO_CONTROL 0x0c44 236 #define VLD_MEM_VIFIFO_WP 0x0c45 237 #define VLD_MEM_VIFIFO_RP 0x0c46 238 #define VLD_MEM_VIFIFO_LEVEL 0x0c47 239 #define VLD_MEM_VIFIFO_BUF_CNTL 0x0c48 240 #define VLD_TIME_STAMP_CNTL 0x0c49 241 #define VLD_TIME_STAMP_SYNC_0 0x0c4a 242 #define VLD_TIME_STAMP_SYNC_1 0x0c4b 243 #define VLD_TIME_STAMP_0 0x0c4c 244 #define VLD_TIME_STAMP_1 0x0c4d 245 #define VLD_TIME_STAMP_2 0x0c4e 246 #define VLD_TIME_STAMP_3 0x0c4f 247 #define VLD_TIME_STAMP_LENGTH 0x0c50 248 #define VLD_MEM_VIFIFO_WRAP_COUNT 0x0c51 249 #define VLD_MEM_VIFIFO_MEM_CTL 0x0c52 250 #define VLD_MEM_VBUF_RD_PTR 0x0c53 251 #define VLD_MEM_VBUF2_RD_PTR 0x0c54 252 #define VLD_MEM_SWAP_ADDR 0x0c55 253 #define VLD_MEM_SWAP_CTL 0x0c56 254 // bit[12] -- zero_use_cbp_blk 255 // bit[11] -- mv_use_abs (only calculate abs) 256 // bit[10] -- mv_use_simple_mode (every size count has same weight) 257 // bit[9] -- use_simple_mode (every size count has same weight) 258 // bit[8] -- reseet_all_count // write only 259 // bit[7:5] Reserved 260 // bit[4:0] pic_quality_rd_idx 261 #define VDEC_PIC_QUALITY_CTRL 0x0c57 262 // idx -- read out 263 // 0 -- blk88_y_count // 4k will use 20 bits 264 // 1 -- qp_y_sum // 4k use 27 bits 265 // 2 -- intra_y_oount // 4k use 20 bits 266 // 3 -- skipped_y_count // 4k use 20 bits 267 // 4 -- coeff_non_zero_y_count // 4k use 20 bits 268 // 5 -- blk66_c_count // 4k will use 20 bits 269 // 6 -- qp_c_sum // 4k use 26 bits 270 // 7 -- intra_c_oount // 4k use 20 bits 271 // 8 -- skipped_cu_c_count // 4k use 20 bits 272 // 9 -- coeff_non_zero_c_count // 4k use 20 bits 273 // 10 -- { 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0], 274 // 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0]} 275 // 11 -- blk22_mv_count 276 // 12 -- {mvy_L1_count[39:32], mvx_L1_count[39:32], 277 // mvy_L0_count[39:32], mvx_L0_count[39:32]} 278 // 13 -- mvx_L0_count[31:0] 279 // 14 -- mvy_L0_count[31:0] 280 // 15 -- mvx_L1_count[31:0] 281 // 16 -- mvy_L1_count[31:0] 282 // 17 -- {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} 283 // 18 -- {mvy_L0_max, mvy_L0_min} 284 // 19 -- {mvx_L1_max, mvx_L1_min} 285 // 20 -- {mvy_L1_max, mvy_L1_min} 286 #define VDEC_PIC_QUALITY_DATA 0x0c58 287 288 #define VCOP_CTRL_REG 0x0e00 289 #define QP_CTRL_REG 0x0e01 290 #define INTRA_QUANT_MATRIX 0x0e02 291 #define NON_I_QUANT_MATRIX 0x0e03 292 #define DC_SCALER 0x0e04 293 #define DC_AC_CTRL 0x0e05 294 #define DC_AC_SCALE_MUL 0x0e06 295 #define DC_AC_SCALE_DIV 0x0e07 296 #define POWER_CTL_IQIDCT 0x0e08 297 #define RV_AI_Y_X 0x0e09 298 #define RV_AI_U_X 0x0e0a 299 #define RV_AI_V_X 0x0e0b 300 #define RV_AI_MB_COUNT 0x0e0c 301 #define NEXT_INTRA_DMA_ADDRESS 0x0e0d 302 #define IQIDCT_CONTROL 0x0e0e 303 #define IQIDCT_DEBUG_INFO_0 0x0e0f 304 #define DEBLK_CMD 0x0e10 305 #define IQIDCT_DEBUG_IDCT 0x0e11 306 #define DCAC_DMA_CTRL 0x0e12 307 #define DCAC_DMA_ADDRESS 0x0e13 308 #define DCAC_CPU_ADDRESS 0x0e14 309 #define DCAC_CPU_DATA 0x0e15 310 #define DCAC_MB_COUNT 0x0e16 311 #define IQ_QUANT 0x0e17 312 #define VC1_BITPLANE_CTL 0x0e18 313 314 315 316 #define DOS_SW_RESET0 0x3f00 317 #define DOS_GCLK_EN0 0x3f01 318 #define DOS_GEN_CTRL0 0x3f02 319 #define DOS_APB_ERR_CTRL 0x3f03 320 #define DOS_APB_ERR_STAT 0x3f04 321 #define DOS_VDEC_INT_EN 0x3f05 322 #define DOS_HCODEC_INT_EN 0x3f06 323 #define DOS_SW_RESET1 0x3f07 324 #define DOS_SW_RESET2 0x3f08 325 #define DOS_GCLK_EN1 0x3f09 326 #define DOS_VDEC2_INT_EN 0x3f0a 327 #define DOS_VDIN_LCNT 0x3f0b 328 #define DOS_VDIN_FCNT 0x3f0c 329 #define DOS_VDIN_CCTL 0x3f0d 330 #define DOS_SCRATCH0 0x3f10 331 #define DOS_SCRATCH1 0x3f11 332 #define DOS_SCRATCH2 0x3f12 333 #define DOS_SCRATCH3 0x3f13 334 #define DOS_SCRATCH4 0x3f14 335 #define DOS_SCRATCH5 0x3f15 336 #define DOS_SCRATCH6 0x3f16 337 #define DOS_SCRATCH7 0x3f17 338 #define DOS_SCRATCH8 0x3f18 339 #define DOS_SCRATCH9 0x3f19 340 #define DOS_SCRATCH10 0x3f1a 341 #define DOS_SCRATCH11 0x3f1b 342 #define DOS_SCRATCH12 0x3f1c 343 #define DOS_SCRATCH13 0x3f1d 344 #define DOS_SCRATCH14 0x3f1e 345 #define DOS_SCRATCH15 0x3f1f 346 #define DOS_SCRATCH16 0x3f20 347 #define DOS_SCRATCH17 0x3f21 348 #define DOS_SCRATCH18 0x3f22 349 #define DOS_SCRATCH19 0x3f23 350 #define DOS_SCRATCH20 0x3f24 351 #define DOS_SCRATCH21 0x3f25 352 #define DOS_SCRATCH22 0x3f26 353 #define DOS_SCRATCH23 0x3f27 354 #define DOS_SCRATCH24 0x3f28 355 #define DOS_SCRATCH25 0x3f29 356 #define DOS_SCRATCH26 0x3f2a 357 #define DOS_SCRATCH27 0x3f2b 358 #define DOS_SCRATCH28 0x3f2c 359 #define DOS_SCRATCH29 0x3f2d 360 #define DOS_SCRATCH30 0x3f2e 361 #define DOS_SCRATCH31 0x3f2f 362 #define DOS_MEM_PD_VDEC 0x3f30 363 #define DOS_MEM_PD_VDEC2 0x3f31 364 #define DOS_MEM_PD_HCODEC 0x3f32 365 /*add from M8M2*/ 366 #define DOS_MEM_PD_HEVC 0x3f33 367 #define DOS_SW_RESET3 0x3f34 368 #define DOS_GCLK_EN3 0x3f35 369 #define DOS_HEVC_INT_EN 0x3f36 370 /**/ 371 372 #define DOS_SW_RESET4 0x3f37 373 #define DOS_GCLK_EN4 0x3f38 374 #define DOS_MEM_PD_WAVE420L 0x3f39 375 #define DOS_WAVE420L_CNTL_STAT 0x3f3a 376 377 /**/ 378 #define DOS_VDEC_MCRCC_STALL_CTRL 0x3f40 379 #define DOS_VDEC_MCRCC_STALL2_CTRL 0x3f42 380 #define DOS_VDEC2_MCRCC_STALL_CTRL 0x3f41 381 #define DOS_VDEC2_MCRCC_STALL2_CTRL 0x3f43 382 383 384 385 #endif 386 387