1 /* 2 * Change Logs 3 * Date Author Notes 4 * 2022-04-17 aozima the first version for CherryUSB. 5 */ 6 7 #ifndef __LINUX_USBNET_ASIX_H 8 #define __LINUX_USBNET_ASIX_H 9 10 // #define __BIG_ENDIAN_BITFIELD 11 #define __LITTLE_ENDIAN_BITFIELD 12 typedef uint8_t u8; 13 typedef uint16_t u16; 14 typedef uint32_t u32; 15 16 #define KERNEL_VERSION(...) (0) 17 #define LINUX_VERSION_CODE (1) 18 19 /* 20 * Turn on this flag if the implementation of your USB host controller 21 * cannot handle non-double word aligned buffer. 22 * When turn on this flag, driver will fixup egress packet aligned on double 23 * word boundary before deliver to USB host controller. And will Disable the 24 * function "skb_reserve (skb, NET_IP_ALIGN)" to retain the buffer aligned on 25 * double word alignment for ingress packets. 26 */ 27 #define AX_FORCE_BUFF_ALIGN 0 28 29 //#define RX_SKB_COPY 30 31 #define AX_MONITOR_MODE 0x01 32 #define AX_MONITOR_LINK 0x02 33 #define AX_MONITOR_MAGIC 0x04 34 #define AX_MONITOR_HSFS 0x10 35 36 /* AX88172 Medium Status Register values */ 37 #define AX_MEDIUM_FULL_DUPLEX 0x02 38 #define AX_MEDIUM_TX_ABORT_ALLOW 0x04 39 #define AX_MEDIUM_FLOW_CONTROL_EN 0x10 40 #define AX_MCAST_FILTER_SIZE 8 41 #define AX_MAX_MCAST 64 42 43 #define AX_EEPROM_LEN 0x40 44 45 #define AX_SWRESET_CLEAR 0x00 46 #define AX_SWRESET_RR 0x01 47 #define AX_SWRESET_RT 0x02 48 #define AX_SWRESET_PRTE 0x04 49 #define AX_SWRESET_PRL 0x08 50 #define AX_SWRESET_BZ 0x10 51 #define AX_SWRESET_IPRL 0x20 52 #define AX_SWRESET_IPPD 0x40 53 #define AX_SWRESET_IPOSC 0x0080 54 #define AX_SWRESET_IPPSL_0 0x0100 55 #define AX_SWRESET_IPPSL_1 0x0200 56 #define AX_SWRESET_IPCOPS 0x0400 57 #define AX_SWRESET_IPCOPSC 0x0800 58 #define AX_SWRESET_AUTODETACH 0x1000 59 #define AX_SWRESET_WOLLP 0x8000 60 61 #define AX88772_IPG0_DEFAULT 0x15 62 #define AX88772_IPG1_DEFAULT 0x0c 63 #define AX88772_IPG2_DEFAULT 0x0E 64 65 #define AX88772A_IPG0_DEFAULT 0x15 66 #define AX88772A_IPG1_DEFAULT 0x16 67 #define AX88772A_IPG2_DEFAULT 0x1A 68 69 #define AX88772_MEDIUM_FULL_DUPLEX 0x0002 70 #define AX88772_MEDIUM_RESERVED 0x0004 71 #define AX88772_MEDIUM_RX_FC_ENABLE 0x0010 72 #define AX88772_MEDIUM_TX_FC_ENABLE 0x0020 73 #define AX88772_MEDIUM_PAUSE_FORMAT 0x0080 74 #define AX88772_MEDIUM_RX_ENABLE 0x0100 75 #define AX88772_MEDIUM_100MB 0x0200 76 #define AX88772_MEDIUM_DEFAULT \ 77 (AX88772_MEDIUM_FULL_DUPLEX | AX88772_MEDIUM_RX_FC_ENABLE | \ 78 AX88772_MEDIUM_TX_FC_ENABLE | AX88772_MEDIUM_100MB | \ 79 AX88772_MEDIUM_RESERVED | AX88772_MEDIUM_RX_ENABLE) 80 81 #define AX_CMD_SET_SW_MII 0x06 82 #define AX_CMD_READ_MII_REG 0x07 83 #define AX_CMD_WRITE_MII_REG 0x08 84 #define AX_CMD_READ_STATMNGSTS_REG 0x09 85 #define AX_HOST_EN 0x01 86 87 #define AX_CMD_SET_HW_MII 0x0a 88 #define AX_CMD_READ_EEPROM 0x0b 89 #define AX_CMD_WRITE_EEPROM 0x0c 90 #define AX_CMD_WRITE_EEPROM_EN 0x0d 91 #define AX_CMD_WRITE_EEPROM_DIS 0x0e 92 #define AX_CMD_WRITE_RX_CTL 0x10 93 #define AX_CMD_READ_IPG012 0x11 94 #define AX_CMD_WRITE_IPG0 0x12 95 #define AX_CMD_WRITE_IPG1 0x13 96 #define AX_CMD_WRITE_IPG2 0x14 97 #define AX_CMD_WRITE_MULTI_FILTER 0x16 98 #define AX_CMD_READ_NODE_ID 0x17 99 #define AX_CMD_READ_PHY_ID 0x19 100 #define AX_CMD_READ_MEDIUM_MODE 0x1a 101 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b 102 #define AX_CMD_READ_MONITOR_MODE 0x1c 103 #define AX_CMD_WRITE_MONITOR_MODE 0x1d 104 #define AX_CMD_WRITE_GPIOS 0x1f 105 #define AX_CMD_SW_RESET 0x20 106 #define AX_CMD_SW_PHY_STATUS 0x21 107 #define AX_CMD_SW_PHY_SELECT 0x22 108 #define AX_PHYSEL_PSEL (1 << 0) 109 #define AX_PHYSEL_ASEL (1 << 1) 110 #define AX_PHYSEL_SSMII (0 << 2) 111 #define AX_PHYSEL_SSRMII (1 << 2) 112 #define AX_PHYSEL_SSRRMII (3 << 2) 113 #define AX_PHYSEL_SSEN (1 << 4) 114 #define AX88772_CMD_READ_NODE_ID 0x13 115 #define AX88772_CMD_WRITE_NODE_ID 0x14 116 #define AX_CMD_READ_WKFARY 0x23 117 #define AX_CMD_WRITE_WKFARY 0x24 118 #define AX_CMD_READ_RXCOE_CTL 0x2b 119 #define AX_CMD_WRITE_RXCOE_CTL 0x2c 120 #define AX_CMD_READ_TXCOE_CTL 0x2d 121 #define AX_CMD_WRITE_TXCOE_CTL 0x2e 122 123 #define REG_LENGTH 2 124 #define PHY_ID_MASK 0x1f 125 126 #define AX_RXCOE_IPCE 0x0001 127 #define AX_RXCOE_IPVE 0x0002 128 #define AX_RXCOE_V6VE 0x0004 129 #define AX_RXCOE_TCPE 0x0008 130 #define AX_RXCOE_UDPE 0x0010 131 #define AX_RXCOE_ICMP 0x0020 132 #define AX_RXCOE_IGMP 0x0040 133 #define AX_RXCOE_ICV6 0x0080 134 #define AX_RXCOE_TCPV6 0x0100 135 #define AX_RXCOE_UDPV6 0x0200 136 #define AX_RXCOE_ICMV6 0x0400 137 #define AX_RXCOE_IGMV6 0x0800 138 #define AX_RXCOE_ICV6V6 0x1000 139 #define AX_RXCOE_FOPC 0x8000 140 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22) 141 #define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \ 142 AX_RXCOE_V6VE | AX_RXCOE_TCPE | \ 143 AX_RXCOE_UDPE | AX_RXCOE_ICV6 | \ 144 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6) 145 #else 146 #define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \ 147 AX_RXCOE_TCPE | AX_RXCOE_UDPE) 148 #endif 149 150 #define AX_RXCOE_64TE 0x0100 151 #define AX_RXCOE_PPPOE 0x0200 152 #define AX_RXCOE_RPCE 0x8000 153 154 #define AX_TXCOE_IP 0x0001 155 #define AX_TXCOE_TCP 0x0002 156 #define AX_TXCOE_UDP 0x0004 157 #define AX_TXCOE_ICMP 0x0008 158 #define AX_TXCOE_IGMP 0x0010 159 #define AX_TXCOE_ICV6 0x0020 160 161 #define AX_TXCOE_TCPV6 0x0100 162 #define AX_TXCOE_UDPV6 0x0200 163 #define AX_TXCOE_ICMV6 0x0400 164 #define AX_TXCOE_IGMV6 0x0800 165 #define AX_TXCOE_ICV6V6 0x1000 166 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22) 167 #define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP | \ 168 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6) 169 #else 170 #define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP) 171 #endif 172 173 #define AX_TXCOE_64TE 0x0001 174 #define AX_TXCOE_PPPE 0x0002 175 176 #define AX88772B_MAX_BULKIN_2K 0 177 #define AX88772B_MAX_BULKIN_4K 1 178 #define AX88772B_MAX_BULKIN_6K 2 179 #define AX88772B_MAX_BULKIN_8K 3 180 #define AX88772B_MAX_BULKIN_16K 4 181 #define AX88772B_MAX_BULKIN_20K 5 182 #define AX88772B_MAX_BULKIN_24K 6 183 #define AX88772B_MAX_BULKIN_32K 7 184 struct {unsigned short size, byte_cnt, threshold; } AX88772B_BULKIN_SIZE[] = { 185 /* 2k */ 186 {2048, 0x8000, 0x8001}, 187 /* 4k */ 188 {4096, 0x8100, 0x8147}, 189 /* 6k */ 190 {6144, 0x8200, 0x81EB}, 191 /* 8k */ 192 {8192, 0x8300, 0x83D7}, 193 /* 16 */ 194 {16384, 0x8400, 0x851E}, 195 /* 20k */ 196 {20480, 0x8500, 0x8666}, 197 /* 24k */ 198 {24576, 0x8600, 0x87AE}, 199 /* 32k */ 200 {32768, 0x8700, 0x8A3D}, 201 }; 202 203 204 #define AX_RX_CTL_RH1M 0x0100 /* Enable RX-Header mode 0 */ 205 #define AX_RX_CTL_RH2M 0x0200 /* Enable IP header in receive buffer aligned on 32-bit aligment */ 206 #define AX_RX_CTL_RH3M 0x0400 /* checksum value in rx header 3 */ 207 #define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M) 208 209 #define AX_RX_CTL_MFB 0x0300 /* Maximum Frame size 16384bytes */ 210 #define AX_RX_CTL_START 0x0080 /* Ethernet MAC start */ 211 #define AX_RX_CTL_AP 0x0020 /* Accept physcial address from Multicast array */ 212 #define AX_RX_CTL_AM 0x0010 213 #define AX_RX_CTL_AB 0x0008 /* Accetp Brocadcast frames*/ 214 #define AX_RX_CTL_SEP 0x0004 /* Save error packets */ 215 #define AX_RX_CTL_AMALL 0x0002 /* Accetp all multicast frames */ 216 #define AX_RX_CTL_PRO 0x0001 /* Promiscuous Mode */ 217 #define AX_RX_CTL_STOP 0x0000 /* Stop MAC */ 218 219 #define AX_MONITOR_MODE 0x01 220 #define AX_MONITOR_LINK 0x02 221 #define AX_MONITOR_MAGIC 0x04 222 #define AX_MONITOR_HSFS 0x10 223 224 #define AX_MCAST_FILTER_SIZE 8 225 #define AX_MAX_MCAST 64 226 #define AX_INTERRUPT_BUFSIZE 8 227 228 #define AX_EEPROM_LEN 0x40 229 #define AX_EEPROM_MAGIC 0xdeadbeef 230 #define EEPROMMASK 0x7f 231 232 /* GPIO REGISTER */ 233 #define AXGPIOS_GPO0EN 0X01 /* 1 << 0 */ 234 #define AXGPIOS_GPO0 0X02 /* 1 << 1 */ 235 #define AXGPIOS_GPO1EN 0X04 /* 1 << 2 */ 236 #define AXGPIOS_GPO1 0X08 /* 1 << 3 */ 237 #define AXGPIOS_GPO2EN 0X10 /* 1 << 4 */ 238 #define AXGPIOS_GPO2 0X20 /* 1 << 5 */ 239 #define AXGPIOS_RSE 0X80 /* 1 << 7 */ 240 241 /* TX-header format */ 242 #define AX_TX_HDR_CPHI 0x4000 243 #define AX_TX_HDR_DICF 0x8000 244 245 /* GMII register definitions */ 246 #define GMII_PHY_CONTROL 0x00 /* control reg */ 247 #define GMII_PHY_STATUS 0x01 /* status reg */ 248 #define GMII_PHY_OUI 0x02 /* most of the OUI bits */ 249 #define GMII_PHY_MODEL 0x03 /* model/rev bits, and rest of OUI */ 250 #define GMII_PHY_ANAR 0x04 /* AN advertisement reg */ 251 #define GMII_PHY_ANLPAR 0x05 /* AN Link Partner */ 252 #define GMII_PHY_ANER 0x06 /* AN expansion reg */ 253 #define GMII_PHY_1000BT_CONTROL 0x09 /* control reg for 1000BT */ 254 #define GMII_PHY_1000BT_STATUS 0x0A /* status reg for 1000BT */ 255 256 /* Bit definitions: GMII Control */ 257 #define GMII_CONTROL_RESET 0x8000 /* reset bit in control reg */ 258 #define GMII_CONTROL_LOOPBACK 0x4000 /* loopback bit in control reg */ 259 #define GMII_CONTROL_10MB 0x0000 /* 10 Mbit */ 260 #define GMII_CONTROL_100MB 0x2000 /* 100Mbit */ 261 #define GMII_CONTROL_1000MB 0x0040 /* 1000Mbit */ 262 #define GMII_CONTROL_SPEED_BITS 0x2040 /* speed bit mask */ 263 #define GMII_CONTROL_ENABLE_AUTO 0x1000 /* autonegotiate enable */ 264 #define GMII_CONTROL_POWER_DOWN 0x0800 265 #define GMII_CONTROL_ISOLATE 0x0400 /* islolate bit */ 266 #define GMII_CONTROL_START_AUTO 0x0200 /* restart autonegotiate */ 267 #define GMII_CONTROL_FULL_DUPLEX 0x0100 268 269 /* Bit definitions: GMII Status */ 270 #define GMII_STATUS_100MB_MASK 0xE000 /* any of these indicate 100 Mbit */ 271 #define GMII_STATUS_10MB_MASK 0x1800 /* either of these indicate 10 Mbit */ 272 #define GMII_STATUS_AUTO_DONE 0x0020 /* auto negotiation complete */ 273 #define GMII_STATUS_AUTO 0x0008 /* auto negotiation is available */ 274 #define GMII_STATUS_LINK_UP 0x0004 /* link status bit */ 275 #define GMII_STATUS_EXTENDED 0x0001 /* extended regs exist */ 276 #define GMII_STATUS_100T4 0x8000 /* capable of 100BT4 */ 277 #define GMII_STATUS_100TXFD 0x4000 /* capable of 100BTX full duplex */ 278 #define GMII_STATUS_100TX 0x2000 /* capable of 100BTX */ 279 #define GMII_STATUS_10TFD 0x1000 /* capable of 10BT full duplex */ 280 #define GMII_STATUS_10T 0x0800 /* capable of 10BT */ 281 282 /* Bit definitions: Auto-Negotiation Advertisement */ 283 #define GMII_ANAR_ASYM_PAUSE 0x0800 /* support asymetric pause */ 284 #define GMII_ANAR_PAUSE 0x0400 /* support pause packets */ 285 #define GMII_ANAR_100T4 0x0200 /* support 100BT4 */ 286 #define GMII_ANAR_100TXFD 0x0100 /* support 100BTX full duplex */ 287 #define GMII_ANAR_100TX 0x0080 /* support 100BTX half duplex */ 288 #define GMII_ANAR_10TFD 0x0040 /* support 10BT full duplex */ 289 #define GMII_ANAR_10T 0x0020 /* support 10BT half duplex */ 290 #define GMII_SELECTOR_FIELD 0x001F /* selector field. */ 291 292 /* Bit definitions: Auto-Negotiation Link Partner Ability */ 293 #define GMII_ANLPAR_100T4 0x0200 /* support 100BT4 */ 294 #define GMII_ANLPAR_100TXFD 0x0100 /* support 100BTX full duplex */ 295 #define GMII_ANLPAR_100TX 0x0080 /* support 100BTX half duplex */ 296 #define GMII_ANLPAR_10TFD 0x0040 /* support 10BT full duplex */ 297 #define GMII_ANLPAR_10T 0x0020 /* support 10BT half duplex */ 298 #define GMII_ANLPAR_PAUSE 0x0400 /* support pause packets */ 299 #define GMII_ANLPAR_ASYM_PAUSE 0x0800 /* support asymetric pause */ 300 #define GMII_ANLPAR_ACK 0x4000 /* means LCB was successfully rx'd */ 301 #define GMII_SELECTOR_8023 0x0001; 302 303 /* Bit definitions: 1000BaseT AUX Control */ 304 #define GMII_1000_AUX_CTRL_MASTER_SLAVE 0x1000 305 #define GMII_1000_AUX_CTRL_FD_CAPABLE 0x0200 /* full duplex capable */ 306 #define GMII_1000_AUX_CTRL_HD_CAPABLE 0x0100 /* half duplex capable */ 307 308 /* Bit definitions: 1000BaseT AUX Status */ 309 #define GMII_1000_AUX_STATUS_FD_CAPABLE 0x0800 /* full duplex capable */ 310 #define GMII_1000_AUX_STATUS_HD_CAPABLE 0x0400 /* half duplex capable */ 311 312 /* Cicada MII Registers */ 313 #define GMII_AUX_CTRL_STATUS 0x1C 314 #define GMII_AUX_ANEG_CPLT 0x8000 315 #define GMII_AUX_FDX 0x0020 316 #define GMII_AUX_SPEED_1000 0x0010 317 #define GMII_AUX_SPEED_100 0x0008 318 319 #ifndef ADVERTISE_PAUSE_CAP 320 #define ADVERTISE_PAUSE_CAP 0x0400 321 #endif 322 323 #ifndef MII_STAT1000 324 #define MII_STAT1000 0x000A 325 #endif 326 327 #ifndef LPA_1000FULL 328 #define LPA_1000FULL 0x0800 329 #endif 330 331 /* medium mode register */ 332 #define MEDIUM_GIGA_MODE 0x0001 333 #define MEDIUM_FULL_DUPLEX_MODE 0x0002 334 #define MEDIUM_TX_ABORT_MODE 0x0004 335 #define MEDIUM_ENABLE_125MHZ 0x0008 336 #define MEDIUM_ENABLE_RX_FLOWCTRL 0x0010 337 #define MEDIUM_ENABLE_TX_FLOWCTRL 0x0020 338 #define MEDIUM_ENABLE_JUMBO_FRAME 0x0040 339 #define MEDIUM_CHECK_PAUSE_FRAME_MODE 0x0080 340 #define MEDIUM_ENABLE_RECEIVE 0x0100 341 #define MEDIUM_MII_100M_MODE 0x0200 342 #define MEDIUM_ENABLE_JAM_PATTERN 0x0400 343 #define MEDIUM_ENABLE_STOP_BACKPRESSURE 0x0800 344 #define MEDIUM_ENABLE_SUPPER_MAC_SUPPORT 0x1000 345 346 /* PHY mode */ 347 #define PHY_MODE_MARVELL 0 348 #define PHY_MODE_CICADA_FAMILY 1 349 #define PHY_MODE_CICADA_V1 1 350 #define PHY_MODE_AGERE_FAMILY 2 351 #define PHY_MODE_AGERE_V0 2 352 #define PHY_MODE_CICADA_V2 5 353 #define PHY_MODE_AGERE_V0_GMII 6 354 #define PHY_MODE_CICADA_V2_ASIX 9 355 #define PHY_MODE_VSC8601 10 356 #define PHY_MODE_RTL8211CL 12 357 #define PHY_MODE_RTL8211BN 13 358 #define PHY_MODE_RTL8251CL 14 359 #define PHY_MODE_ATTANSIC_V0 0x40 360 #define PHY_MODE_ATTANSIC_FAMILY 0x40 361 #define PHY_MODE_MAC_TO_MAC_GMII 0x7C 362 363 /* */ 364 #define LED_MODE_MARVELL 0 365 #define LED_MODE_CAMEO 1 366 367 #define MARVELL_LED_CTRL 0x18 368 #define MARVELL_MANUAL_LED 0x19 369 370 #define PHY_IDENTIFIER 0x0002 371 #define PHY_AGERE_IDENTIFIER 0x0282 372 #define PHY_CICADA_IDENTIFIER 0x000f 373 #define PHY_MARVELL_IDENTIFIER 0x0141 374 375 #define PHY_MARVELL_STATUS 0x001b 376 #define MARVELL_STATUS_HWCFG 0x0004 /* SGMII without clock */ 377 378 #define PHY_MARVELL_CTRL 0x0014 379 #define MARVELL_CTRL_RXDELAY 0x0080 380 #define MARVELL_CTRL_TXDELAY 0x0002 381 382 #define PHY_CICADA_EXTPAGE 0x001f 383 #define CICADA_EXTPAGE_EN 0x0001 384 #define CICADA_EXTPAGE_DIS 0x0000 385 386 /* External ethernet phy */ 387 #define EXTPHY_ID_MASK_OUI(phyid1, phyid2) ((phyid1 << 6) | ((phyid2 & 0xFC00) >> 10)) 388 #define EXTPHY_ID_MASK_MODEL(phyid2) ((phyid2 & 0x3F0) >> 4) 389 390 #define EXTPHY_BROADCOM_OUI 0x2B8094 391 #define EXTPHY_BCM89811_MODEL 0x02 392 393 struct {unsigned short value, offset; } CICADA_FAMILY_HWINIT[] = { 394 {0x0001, 0x001f}, {0x1c25, 0x0017}, {0x2a30, 0x001f}, {0x234c, 0x0010}, 395 {0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa7fa, 0x0000}, 396 {0x0012, 0x0002}, {0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f}, 397 {0xafac, 0x0000}, {0x000d, 0x0002}, {0x001c, 0x0001}, {0x8fac, 0x0000}, 398 {0x2a30, 0x001f}, {0x0012, 0x0008}, {0x2a30, 0x001f}, {0x0400, 0x0014}, 399 {0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa760, 0x0000}, 400 {0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000}, {0x52b5, 0x001f}, 401 {0xa760, 0x0000}, {0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000}, 402 {0x52b5, 0x001f}, {0xafae, 0x0000}, {0x0004, 0x0002}, {0x0671, 0x0001}, 403 {0x8fae, 0x0000}, {0x2a30, 0x001f}, {0x0012, 0x0008}, {0x0000, 0x001f}, 404 }; 405 406 struct {unsigned short value, offset; } CICADA_V2_HWINIT[] = { 407 {0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x000f, 0x0002}, 408 {0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008}, 409 {0x0000, 0x001f}, 410 }; 411 412 struct {unsigned short value, offset; } CICADA_V2_ASIX_HWINIT[] = { 413 {0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x0012, 0x0002}, 414 {0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f}, {0x000f, 0x0002}, 415 {0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008}, 416 {0x0000, 0x001f}, 417 }; 418 419 struct {unsigned short value, offset; } AGERE_FAMILY_HWINIT[] = { 420 {0x0800, 0x0000}, {0x0007, 0x0012}, {0x8805, 0x0010}, {0xb03e, 0x0011}, 421 {0x8808, 0x0010}, {0xe110, 0x0011}, {0x8806, 0x0010}, {0xb03e, 0x0011}, 422 {0x8807, 0x0010}, {0xff00, 0x0011}, {0x880e, 0x0010}, {0xb4d3, 0x0011}, 423 {0x880f, 0x0010}, {0xb4d3, 0x0011}, {0x8810, 0x0010}, {0xb4d3, 0x0011}, 424 {0x8817, 0x0010}, {0x1c00, 0x0011}, {0x300d, 0x0010}, {0x0001, 0x0011}, 425 {0x0002, 0x0012}, 426 }; 427 428 struct ax88178_data { 429 u16 EepromData; 430 u16 MediaLink; 431 int UseGpio0; 432 int UseRgmii; 433 u8 PhyMode; 434 u8 LedMode; 435 u8 BuffaloOld; 436 }; 437 438 enum watchdog_state { 439 AX_NOP = 0, 440 CHK_LINK, /* Routine A */ 441 CHK_CABLE_EXIST, /* Called by A */ 442 CHK_CABLE_EXIST_AGAIN, /* Routine B */ 443 PHY_POWER_UP, /* Called by B */ 444 PHY_POWER_UP_BH, 445 PHY_POWER_DOWN, 446 CHK_CABLE_STATUS, /* Routine C */ 447 WAIT_AUTONEG_COMPLETE, 448 AX_SET_RX_CFG, 449 AX_CHK_AUTODETACH, 450 }; 451 452 #if 0 453 struct ax88772b_data { 454 struct usbnet *dev; 455 struct workqueue_struct *ax_work; 456 struct work_struct check_link; 457 unsigned long time_to_chk; 458 u16 psc; 459 u8 pw_enabled; 460 u8 Event; 461 u8 checksum; 462 u8 PhySelect:1; 463 u8 OperationMode:1; 464 u16 presvd_phy_advertise; 465 u16 presvd_phy_bmcr; 466 467 u32 ext_phy_oui; 468 u8 ext_phy_model; 469 }; 470 #endif 471 472 /* define for MAC or PHY mode */ 473 #define OPERATION_MAC_MODE 0 474 #define OPERATION_PHY_MODE 1 475 476 #if 0 477 struct ax88772a_data { 478 struct usbnet *dev; 479 struct workqueue_struct *ax_work; 480 struct work_struct check_link; 481 unsigned long autoneg_start; 482 #define AX88772B_WATCHDOG (6 * HZ) 483 u8 Event; 484 u8 TickToExpire; 485 u8 DlyIndex; 486 u8 DlySel; 487 u16 EepromData; 488 u16 presvd_phy_advertise; 489 u16 presvd_phy_bmcr; 490 }; 491 492 struct ax88772_data { 493 struct usbnet *dev; 494 struct workqueue_struct *ax_work; 495 struct work_struct check_link; 496 unsigned long autoneg_start; 497 u8 Event; 498 u8 TickToExpire; 499 u16 presvd_phy_advertise; 500 u16 presvd_phy_bmcr; 501 }; 502 #endif 503 504 #define AX_RX_CHECKSUM 1 505 #define AX_TX_CHECKSUM 2 506 507 #if 0 508 /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ 509 struct ax8817x_data { 510 u8 multi_filter[AX_MCAST_FILTER_SIZE]; 511 int (*resume) (struct usb_interface *intf); 512 int (*suspend) (struct usb_interface *intf, 513 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 10) 514 pm_message_t message); 515 #else 516 u32 message); 517 #endif 518 }; 519 #endif 520 521 struct ax88172_int_data { 522 u16 res1; 523 #define AX_INT_PPLS_LINK (1 << 0) 524 #define AX_INT_SPLS_LINK (1 << 1) 525 #define AX_INT_CABOFF_UNPLUG (1 << 7) 526 u8 link; 527 u16 res2; 528 u8 status; 529 u16 res3; 530 } __attribute__ ((packed)); 531 532 #define AX_RXHDR_L4_ERR (1 << 8) 533 #define AX_RXHDR_L3_ERR (1 << 9) 534 535 #define AX_RXHDR_L4_TYPE_UDP 1 536 #define AX_RXHDR_L4_TYPE_ICMP 2 537 #define AX_RXHDR_L4_TYPE_IGMP 3 538 #define AX_RXHDR_L4_TYPE_TCP 4 539 #define AX_RXHDR_L4_TYPE_TCMPV6 5 540 #define AX_RXHDR_L4_TYPE_MASK 7 541 542 #define AX_RXHDR_L3_TYPE_IP 1 543 #define AX_RXHDR_L3_TYPE_IPV6 2 544 545 struct ax88772b_rx_header { 546 #if defined(__LITTLE_ENDIAN_BITFIELD) 547 u16 len:11, 548 res1:1, 549 crc:1, 550 mii:1, 551 runt:1, 552 mc_bc:1; 553 554 u16 len_bar:11, 555 res2:5; 556 557 u8 vlan_ind:3, 558 vlan_tag_striped:1, 559 pri:3, 560 res3:1; 561 562 u8 l4_csum_err:1, 563 l3_csum_err:1, 564 l4_type:3, 565 l3_type:2, 566 ce:1; 567 #elif defined(__BIG_ENDIAN_BITFIELD) 568 u16 mc_bc:1, 569 runt:1, 570 mii:1, 571 crc:1, 572 res1:1, 573 len:11; 574 575 u16 res2:5, 576 len_bar:11; 577 578 u8 res3:1, 579 pri:3, 580 vlan_tag_striped:1, 581 vlan_ind:3; 582 583 u8 ce:1, 584 l3_type:2, 585 l4_type:3, 586 l3_csum_err:1, 587 l4_csum_err:1; 588 #else 589 #error "Please fix <asm/byteorder.h>" 590 #endif 591 592 } __attribute__ ((packed)); 593 594 595 #endif /* __LINUX_USBNET_ASIX_H */ 596 597