1 /**************************************************************************//** 2 * @file system_gr55xx.h 3 * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for 4 * Device GR55xx 5 * @version V1.00 6 * @date 12. June 2018 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2016-2018, Shenzhen Huiding Technology Co., Ltd 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #ifndef __SYSTEM_GR55xx_H__ 27 #define __SYSTEM_GR55xx_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define CLK_64M 64000000 36 #define CLK_48M 48000000 37 #define CLK_32M 32000000 38 #define CLK_24M 24000000 39 #define CLK_16M 16000000 40 41 typedef enum { 42 XO_S16M_CLK = 2, 43 CPLL_S16M_CLK = 4, 44 CPLL_T24M_CLK = 3, 45 CPLL_T32M_CLK = 5, 46 CPLL_F48M_CLK = 1, 47 CPLL_S64M_CLK = 0, 48 CLK_TYPE_NUM = 6, 49 } mcu_clock_type_t; 50 51 typedef enum { 52 QSPI_64M_CLK = 0, 53 QSPI_48M_CLK = 1, 54 QSPI_32M_CLK = 2, 55 QSPI_24M_CLK = 3, 56 QSPI_16M_CLK = 4, 57 QSPI_CLK_TYPE_NUM = 5, 58 } qspi_clock_type_t; 59 60 /** @addtogroup Peripheral_interrupt_number_definition 61 * @{ 62 */ 63 64 /** 65 * @brief GR55xx Interrupt Number Definition, according to the selected device 66 * in @ref Library_configuration_section 67 */ 68 69 /* ================================================================================================================= */ 70 /* ================ Interrupt Number Definition ================ */ 71 /* ================================================================================================================= */ 72 typedef enum IRQn { 73 /* ================================== ARM Cortex-M# Specific Interrupt Numbers =================================== */ 74 75 NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ 76 HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ 77 MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation 78 and No Match */ 79 BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 80 related Fault */ 81 UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 82 SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /**< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /**< -1 System Tick Timer */ 86 87 /* ====================================== <Device> Specific Interrupt Numbers ==================================== */ 88 WDT_IRQn = 0, /**< Watchdog Timer Interrupt */ 89 BLE_SDK_IRQn = 1, /**< BLE_SDK_SCHEDULE Interrupt */ 90 BLE_IRQn = 2, /**< BLE Interrupt */ 91 DMA_IRQn = 3, /**< DMA Interrupt */ 92 SPI_M_IRQn = 4, /**< SPI_M Interrupt */ 93 SPI_S_IRQn = 5, /**< SPI_S Interrupt */ 94 EXT0_IRQn = 6, /**< EXT0 Interrupt */ 95 EXT1_IRQn = 7, /**< EXT1 Interrupt */ 96 TIMER0_IRQn = 8, /**< Timer0 Interrupt */ 97 TIMER1_IRQn = 9, /**< Timer1 Interrupt */ 98 DUAL_TIMER_IRQn = 10, /**< Dual_Timer Interrupt */ 99 QSPI0_IRQn = 11, /**< QSPI0 Interrupt */ 100 UART0_IRQn = 12, /**< UART0 Interrupt */ 101 UART1_IRQn = 13, /**< UART1 Interrupt */ 102 I2C0_IRQn = 14, /**< I2C0 Interrupt */ 103 I2C1_IRQn = 15, /**< I2C1 Interrupt */ 104 AES_IRQn = 16, /**< AES Interrupt */ 105 HMAC_IRQn = 17, /**< HMAC Interrupt */ 106 EXT2_IRQn = 18, /**< EXT2 Interrupt */ 107 RNG_IRQn = 19, /**< RNG Interrupt */ 108 PMU_IRQn = 20, /**< PMU Interrupt */ 109 PKC_IRQn = 21, /**< PKC Interrupt */ 110 XQSPI_IRQn = 22, /**< XQSPI Interrupt */ 111 QSPI1_IRQn = 23, /**< QSPI1 Interrupt */ 112 PWR_CMD_IRQn = 24, /**< POWER CMD ACK Interrupt */ 113 BLESLP_IRQn = 25, /**< BLE Sleep Interrupt */ 114 SLPTIMER_IRQn = 26, /**< Sleep Timer Interrupt */ 115 COMP_EXT_IRQn = 27, /**< Comparator and External Wakeup Interrupt */ 116 AON_WDT_IRQn = 28, /**< Always on Watchdog Interrupt */ 117 I2S_M_IRQn = 29, /**< I2S_M Interrupt */ 118 I2S_S_IRQn = 30, /**< I2S_S Interrupt */ 119 ISO7816_IRQn = 31, /**< ISO7816 Interrupt */ 120 PRESENT_IRQn = 32, /**< Presnet Done Interrupt */ 121 CALENDAR_IRQn = 33, /**< AON Calendar Timer Interrupt */ 122 MAX_NUMS_IRQn = 34, /**< Last Interrupt */ 123 } IRQn_Type; 124 125 /** @} */ /* End of group Peripheral _interrupt_number_definition */ 126 127 /* ================================================================================================================= */ 128 /* ================ Processor and Core Peripheral Section ================ */ 129 /* ================================================================================================================= */ 130 131 /* =================================== Start of section using anonymous unions =================================== */ 132 133 /* ====================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals ====================== */ 134 #define __CM4_REV 0x0001U /* Core revision r0p1 */ 135 #define __MPU_PRESENT 1 /* MPU present */ 136 #define __VTOR_PRESENT 1 /* VTOR present */ 137 #define __NVIC_PRIO_BITS 8 /* Number of Bits used for Priority Levels */ 138 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 139 #define __FPU_PRESENT 1 /* FPU present */ 140 141 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 142 143 /** @brief Setup the microcontroller system. 144 145 Initialize the System and update the SystemCoreClock variable. 146 */ 147 extern void SystemInit(void); 148 149 /** \brief Update SystemCoreClock variable. 150 151 Updates the SystemCoreClock with current core Clock 152 retrieved from cpu registers. 153 */ 154 extern void SystemCoreSetClock(mcu_clock_type_t clock); 155 156 /** \brief Get SystemCoreClock variable. 157 158 Get the SystemCoreClock with current core Clock 159 retrieved from cpu registers. 160 */ 161 extern void SystemCoreGetClock(mcu_clock_type_t *clock); 162 163 164 extern void SystemCoreUpdateClock(void); 165 166 167 #ifdef __cplusplus 168 } 169 #endif 170 171 #endif /* __SYSTEM_GR55xx_H__ */ 172