1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DAC_H 10 #define HPM_DAC_H 11 12 typedef struct { 13 __W uint32_t CFG0; /* 0x0: */ 14 __RW uint32_t CFG1; /* 0x4: */ 15 __RW uint32_t CFG2; /* 0x8: */ 16 __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ 17 __RW uint32_t STEP_CFG[4]; /* 0x10 - 0x1C: */ 18 __RW uint32_t BUF_ADDR[2]; /* 0x20 - 0x24: */ 19 __RW uint32_t BUF_LENGTH; /* 0x28: */ 20 __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ 21 __W uint32_t IRQ_STS; /* 0x30: */ 22 __RW uint32_t IRQ_EN; /* 0x34: */ 23 __RW uint32_t DMA_EN; /* 0x38: */ 24 __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ 25 __RW uint32_t ANA_CFG0; /* 0x40: */ 26 __RW uint32_t CFG0_BAK; /* 0x44: */ 27 __RW uint32_t STATUS0; /* 0x48: */ 28 } DAC_Type; 29 30 31 /* Bitfield definition for register: CFG0 */ 32 /* 33 * SW_DAC_DATA (WO) 34 * 35 * dac data used in direct mode(dac_mode==2'b10) 36 */ 37 #define DAC_CFG0_SW_DAC_DATA_MASK (0xFFF0000UL) 38 #define DAC_CFG0_SW_DAC_DATA_SHIFT (16U) 39 #define DAC_CFG0_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_SW_DAC_DATA_SHIFT) & DAC_CFG0_SW_DAC_DATA_MASK) 40 #define DAC_CFG0_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_SW_DAC_DATA_MASK) >> DAC_CFG0_SW_DAC_DATA_SHIFT) 41 42 /* 43 * DMA_AHB_EN (WO) 44 * 45 * set to enable internal DMA, it will read one burst if enough space in FIFO. 46 * Should only be used in buffer mode. 47 */ 48 #define DAC_CFG0_DMA_AHB_EN_MASK (0x200U) 49 #define DAC_CFG0_DMA_AHB_EN_SHIFT (9U) 50 #define DAC_CFG0_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_DMA_AHB_EN_SHIFT) & DAC_CFG0_DMA_AHB_EN_MASK) 51 #define DAC_CFG0_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_DMA_AHB_EN_MASK) >> DAC_CFG0_DMA_AHB_EN_SHIFT) 52 53 /* 54 * SYNC_MODE (WO) 55 * 56 * 1: sync dac clock and ahb clock. 57 * all HW trigger signals are pulse in sync mode, can get faster response; 58 * 0: async dac clock and ahb_clock 59 * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) 60 */ 61 #define DAC_CFG0_SYNC_MODE_MASK (0x100U) 62 #define DAC_CFG0_SYNC_MODE_SHIFT (8U) 63 #define DAC_CFG0_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_SYNC_MODE_SHIFT) & DAC_CFG0_SYNC_MODE_MASK) 64 #define DAC_CFG0_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_SYNC_MODE_MASK) >> DAC_CFG0_SYNC_MODE_SHIFT) 65 66 /* 67 * TRIG_MODE (WO) 68 * 69 * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 70 * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. 71 */ 72 #define DAC_CFG0_TRIG_MODE_MASK (0x80U) 73 #define DAC_CFG0_TRIG_MODE_SHIFT (7U) 74 #define DAC_CFG0_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_TRIG_MODE_SHIFT) & DAC_CFG0_TRIG_MODE_MASK) 75 #define DAC_CFG0_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_TRIG_MODE_MASK) >> DAC_CFG0_TRIG_MODE_SHIFT) 76 77 /* 78 * HW_TRIG_EN (WO) 79 * 80 * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode 81 */ 82 #define DAC_CFG0_HW_TRIG_EN_MASK (0x40U) 83 #define DAC_CFG0_HW_TRIG_EN_SHIFT (6U) 84 #define DAC_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_HW_TRIG_EN_SHIFT) & DAC_CFG0_HW_TRIG_EN_MASK) 85 #define DAC_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_HW_TRIG_EN_MASK) >> DAC_CFG0_HW_TRIG_EN_SHIFT) 86 87 /* 88 * DAC_MODE (WO) 89 * 90 * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 91 * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 92 * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; 93 * 11: trigger mode, DAC output from external trigger signals 94 * Note: 95 * Trigger mode is not supported in hpm63xx and hpm62xx families. 96 */ 97 #define DAC_CFG0_DAC_MODE_MASK (0x30U) 98 #define DAC_CFG0_DAC_MODE_SHIFT (4U) 99 #define DAC_CFG0_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_DAC_MODE_SHIFT) & DAC_CFG0_DAC_MODE_MASK) 100 #define DAC_CFG0_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_DAC_MODE_MASK) >> DAC_CFG0_DAC_MODE_SHIFT) 101 102 /* 103 * BUF_DATA_MODE (WO) 104 * 105 * data structure for buffer mode, 106 * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 107 * 1: each 32-bit data contains 1 point, b11:0 for first 108 */ 109 #define DAC_CFG0_BUF_DATA_MODE_MASK (0x8U) 110 #define DAC_CFG0_BUF_DATA_MODE_SHIFT (3U) 111 #define DAC_CFG0_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BUF_DATA_MODE_MASK) 112 #define DAC_CFG0_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BUF_DATA_MODE_MASK) >> DAC_CFG0_BUF_DATA_MODE_SHIFT) 113 114 /* 115 * HBURST_CFG (WO) 116 * 117 * DAC support following fixed burst only 118 * 000-SINGLE; 011-INCR4; 101: INCR8 119 * others are reserved 120 */ 121 #define DAC_CFG0_HBURST_CFG_MASK (0x7U) 122 #define DAC_CFG0_HBURST_CFG_SHIFT (0U) 123 #define DAC_CFG0_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_HBURST_CFG_SHIFT) & DAC_CFG0_HBURST_CFG_MASK) 124 #define DAC_CFG0_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_HBURST_CFG_MASK) >> DAC_CFG0_HBURST_CFG_SHIFT) 125 126 /* Bitfield definition for register: CFG1 */ 127 /* 128 * ANA_CLK_EN (RW) 129 * 130 * set to enable analog clock(divided by ana_div_cfg) 131 * need to be set in direct mode and trigger mode 132 */ 133 #define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) 134 #define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) 135 #define DAC_CFG1_ANA_CLK_EN_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_CLK_EN_SHIFT) & DAC_CFG1_ANA_CLK_EN_MASK) 136 #define DAC_CFG1_ANA_CLK_EN_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_CLK_EN_MASK) >> DAC_CFG1_ANA_CLK_EN_SHIFT) 137 138 /* 139 * ANA_DIV_CFG (RW) 140 * 141 * clock divider config for ana_clk to dac analog; 142 * 00: div2 143 * 01: div4 144 * 10: div6 145 * 11: div8 146 */ 147 #define DAC_CFG1_ANA_DIV_CFG_MASK (0x30000UL) 148 #define DAC_CFG1_ANA_DIV_CFG_SHIFT (16U) 149 #define DAC_CFG1_ANA_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_DIV_CFG_SHIFT) & DAC_CFG1_ANA_DIV_CFG_MASK) 150 #define DAC_CFG1_ANA_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_DIV_CFG_MASK) >> DAC_CFG1_ANA_DIV_CFG_SHIFT) 151 152 /* 153 * DIV_CFG (RW) 154 * 155 * step mode and buffer mode: 156 * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. 157 * Direct mode and trigger mode: 158 * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. 159 * Note: 160 * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. 161 */ 162 #define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) 163 #define DAC_CFG1_DIV_CFG_SHIFT (0U) 164 #define DAC_CFG1_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_DIV_CFG_SHIFT) & DAC_CFG1_DIV_CFG_MASK) 165 #define DAC_CFG1_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_DIV_CFG_MASK) >> DAC_CFG1_DIV_CFG_SHIFT) 166 167 /* Bitfield definition for register: CFG2 */ 168 /* 169 * DMA_RST1 (WO) 170 * 171 * set to reset dma read pointer to buf1_start_addr; 172 * if set both dma_rst0&dma_rst1, will set to buf0_start_addr 173 * user can set fifo_clr bit when use dma_rst* 174 */ 175 #define DAC_CFG2_DMA_RST1_MASK (0x80U) 176 #define DAC_CFG2_DMA_RST1_SHIFT (7U) 177 #define DAC_CFG2_DMA_RST1_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST1_SHIFT) & DAC_CFG2_DMA_RST1_MASK) 178 #define DAC_CFG2_DMA_RST1_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST1_MASK) >> DAC_CFG2_DMA_RST1_SHIFT) 179 180 /* 181 * DMA_RST0 (WO) 182 * 183 * set to reset dma read pointer to buf0_start_addr 184 */ 185 #define DAC_CFG2_DMA_RST0_MASK (0x40U) 186 #define DAC_CFG2_DMA_RST0_SHIFT (6U) 187 #define DAC_CFG2_DMA_RST0_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST0_SHIFT) & DAC_CFG2_DMA_RST0_MASK) 188 #define DAC_CFG2_DMA_RST0_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST0_MASK) >> DAC_CFG2_DMA_RST0_SHIFT) 189 190 /* 191 * FIFO_CLR (WO) 192 * 193 * set to clear FIFO content(set both read/write pointer to 0) 194 */ 195 #define DAC_CFG2_FIFO_CLR_MASK (0x20U) 196 #define DAC_CFG2_FIFO_CLR_SHIFT (5U) 197 #define DAC_CFG2_FIFO_CLR_SET(x) (((uint32_t)(x) << DAC_CFG2_FIFO_CLR_SHIFT) & DAC_CFG2_FIFO_CLR_MASK) 198 #define DAC_CFG2_FIFO_CLR_GET(x) (((uint32_t)(x) & DAC_CFG2_FIFO_CLR_MASK) >> DAC_CFG2_FIFO_CLR_SHIFT) 199 200 /* 201 * BUF_SW_TRIG (RW) 202 * 203 * software trigger for buffer mode, 204 * W1C in single mode. 205 * RW in continual mode 206 */ 207 #define DAC_CFG2_BUF_SW_TRIG_MASK (0x10U) 208 #define DAC_CFG2_BUF_SW_TRIG_SHIFT (4U) 209 #define DAC_CFG2_BUF_SW_TRIG_SET(x) (((uint32_t)(x) << DAC_CFG2_BUF_SW_TRIG_SHIFT) & DAC_CFG2_BUF_SW_TRIG_MASK) 210 #define DAC_CFG2_BUF_SW_TRIG_GET(x) (((uint32_t)(x) & DAC_CFG2_BUF_SW_TRIG_MASK) >> DAC_CFG2_BUF_SW_TRIG_SHIFT) 211 212 /* 213 * STEP_SW_TRIG3 (RW) 214 * 215 */ 216 #define DAC_CFG2_STEP_SW_TRIG3_MASK (0x8U) 217 #define DAC_CFG2_STEP_SW_TRIG3_SHIFT (3U) 218 #define DAC_CFG2_STEP_SW_TRIG3_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG3_SHIFT) & DAC_CFG2_STEP_SW_TRIG3_MASK) 219 #define DAC_CFG2_STEP_SW_TRIG3_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG3_MASK) >> DAC_CFG2_STEP_SW_TRIG3_SHIFT) 220 221 /* 222 * STEP_SW_TRIG2 (RW) 223 * 224 */ 225 #define DAC_CFG2_STEP_SW_TRIG2_MASK (0x4U) 226 #define DAC_CFG2_STEP_SW_TRIG2_SHIFT (2U) 227 #define DAC_CFG2_STEP_SW_TRIG2_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG2_SHIFT) & DAC_CFG2_STEP_SW_TRIG2_MASK) 228 #define DAC_CFG2_STEP_SW_TRIG2_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG2_MASK) >> DAC_CFG2_STEP_SW_TRIG2_SHIFT) 229 230 /* 231 * STEP_SW_TRIG1 (RW) 232 * 233 */ 234 #define DAC_CFG2_STEP_SW_TRIG1_MASK (0x2U) 235 #define DAC_CFG2_STEP_SW_TRIG1_SHIFT (1U) 236 #define DAC_CFG2_STEP_SW_TRIG1_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG1_SHIFT) & DAC_CFG2_STEP_SW_TRIG1_MASK) 237 #define DAC_CFG2_STEP_SW_TRIG1_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG1_MASK) >> DAC_CFG2_STEP_SW_TRIG1_SHIFT) 238 239 /* 240 * STEP_SW_TRIG0 (RW) 241 * 242 * software trigger0 for step mode, 243 * W1C in single mode. 244 * RW in continual mode 245 */ 246 #define DAC_CFG2_STEP_SW_TRIG0_MASK (0x1U) 247 #define DAC_CFG2_STEP_SW_TRIG0_SHIFT (0U) 248 #define DAC_CFG2_STEP_SW_TRIG0_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG0_SHIFT) & DAC_CFG2_STEP_SW_TRIG0_MASK) 249 #define DAC_CFG2_STEP_SW_TRIG0_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG0_MASK) >> DAC_CFG2_STEP_SW_TRIG0_SHIFT) 250 251 /* Bitfield definition for register array: STEP_CFG */ 252 /* 253 * ROUND_MODE (RW) 254 * 255 * 0: stop at end point; 256 * 1: reload start point, step again 257 */ 258 #define DAC_STEP_CFG_ROUND_MODE_MASK (0x20000000UL) 259 #define DAC_STEP_CFG_ROUND_MODE_SHIFT (29U) 260 #define DAC_STEP_CFG_ROUND_MODE_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_ROUND_MODE_SHIFT) & DAC_STEP_CFG_ROUND_MODE_MASK) 261 #define DAC_STEP_CFG_ROUND_MODE_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_ROUND_MODE_MASK) >> DAC_STEP_CFG_ROUND_MODE_SHIFT) 262 263 /* 264 * UP_DOWN (RW) 265 * 266 * 0 for up, 1 for down 267 */ 268 #define DAC_STEP_CFG_UP_DOWN_MASK (0x10000000UL) 269 #define DAC_STEP_CFG_UP_DOWN_SHIFT (28U) 270 #define DAC_STEP_CFG_UP_DOWN_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_UP_DOWN_SHIFT) & DAC_STEP_CFG_UP_DOWN_MASK) 271 #define DAC_STEP_CFG_UP_DOWN_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_UP_DOWN_MASK) >> DAC_STEP_CFG_UP_DOWN_SHIFT) 272 273 /* 274 * END_POINT (RW) 275 * 276 */ 277 #define DAC_STEP_CFG_END_POINT_MASK (0xFFF0000UL) 278 #define DAC_STEP_CFG_END_POINT_SHIFT (16U) 279 #define DAC_STEP_CFG_END_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_END_POINT_SHIFT) & DAC_STEP_CFG_END_POINT_MASK) 280 #define DAC_STEP_CFG_END_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_END_POINT_MASK) >> DAC_STEP_CFG_END_POINT_SHIFT) 281 282 /* 283 * STEP_NUM (RW) 284 * 285 * output data change step_num each DAC clock cycle. 286 * Ex: if step_num=3, output data sequence is 0,3,6,9 287 * NOTE: user should make sure end_point can be reached if step_num is not 1 288 * if step_num is 0, output data will always at start point 289 */ 290 #define DAC_STEP_CFG_STEP_NUM_MASK (0xF000U) 291 #define DAC_STEP_CFG_STEP_NUM_SHIFT (12U) 292 #define DAC_STEP_CFG_STEP_NUM_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_STEP_NUM_SHIFT) & DAC_STEP_CFG_STEP_NUM_MASK) 293 #define DAC_STEP_CFG_STEP_NUM_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_STEP_NUM_MASK) >> DAC_STEP_CFG_STEP_NUM_SHIFT) 294 295 /* 296 * START_POINT (RW) 297 * 298 */ 299 #define DAC_STEP_CFG_START_POINT_MASK (0xFFFU) 300 #define DAC_STEP_CFG_START_POINT_SHIFT (0U) 301 #define DAC_STEP_CFG_START_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_START_POINT_SHIFT) & DAC_STEP_CFG_START_POINT_MASK) 302 #define DAC_STEP_CFG_START_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_START_POINT_MASK) >> DAC_STEP_CFG_START_POINT_SHIFT) 303 304 /* Bitfield definition for register array: BUF_ADDR */ 305 /* 306 * BUF_START_ADDR (RW) 307 * 308 * buffer start address, should be 4-byte aligned 309 * AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. 310 */ 311 #define DAC_BUF_ADDR_BUF_START_ADDR_MASK (0xFFFFFFFCUL) 312 #define DAC_BUF_ADDR_BUF_START_ADDR_SHIFT (2U) 313 #define DAC_BUF_ADDR_BUF_START_ADDR_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) 314 #define DAC_BUF_ADDR_BUF_START_ADDR_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) >> DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) 315 316 /* 317 * BUF_STOP (RW) 318 * 319 * set to stop read point at end of bufffer0 320 */ 321 #define DAC_BUF_ADDR_BUF_STOP_MASK (0x1U) 322 #define DAC_BUF_ADDR_BUF_STOP_SHIFT (0U) 323 #define DAC_BUF_ADDR_BUF_STOP_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_STOP_SHIFT) & DAC_BUF_ADDR_BUF_STOP_MASK) 324 #define DAC_BUF_ADDR_BUF_STOP_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_STOP_MASK) >> DAC_BUF_ADDR_BUF_STOP_SHIFT) 325 326 /* Bitfield definition for register: BUF_LENGTH */ 327 /* 328 * BUF1_LEN (RW) 329 * 330 * buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer 331 */ 332 #define DAC_BUF_LENGTH_BUF1_LEN_MASK (0xFFFF0000UL) 333 #define DAC_BUF_LENGTH_BUF1_LEN_SHIFT (16U) 334 #define DAC_BUF_LENGTH_BUF1_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF1_LEN_SHIFT) & DAC_BUF_LENGTH_BUF1_LEN_MASK) 335 #define DAC_BUF_LENGTH_BUF1_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF1_LEN_MASK) >> DAC_BUF_LENGTH_BUF1_LEN_SHIFT) 336 337 /* 338 * BUF0_LEN (RW) 339 * 340 */ 341 #define DAC_BUF_LENGTH_BUF0_LEN_MASK (0xFFFFU) 342 #define DAC_BUF_LENGTH_BUF0_LEN_SHIFT (0U) 343 #define DAC_BUF_LENGTH_BUF0_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF0_LEN_SHIFT) & DAC_BUF_LENGTH_BUF0_LEN_MASK) 344 #define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) 345 346 /* Bitfield definition for register: IRQ_STS */ 347 /* 348 * STEP_CMPT (W1C) 349 * 350 */ 351 #define DAC_IRQ_STS_STEP_CMPT_MASK (0x10U) 352 #define DAC_IRQ_STS_STEP_CMPT_SHIFT (4U) 353 #define DAC_IRQ_STS_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_STEP_CMPT_SHIFT) & DAC_IRQ_STS_STEP_CMPT_MASK) 354 #define DAC_IRQ_STS_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_STEP_CMPT_MASK) >> DAC_IRQ_STS_STEP_CMPT_SHIFT) 355 356 /* 357 * AHB_ERROR (W1C) 358 * 359 * set if hresp==2'b01(ERROR) 360 */ 361 #define DAC_IRQ_STS_AHB_ERROR_MASK (0x8U) 362 #define DAC_IRQ_STS_AHB_ERROR_SHIFT (3U) 363 #define DAC_IRQ_STS_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_AHB_ERROR_SHIFT) & DAC_IRQ_STS_AHB_ERROR_MASK) 364 #define DAC_IRQ_STS_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_AHB_ERROR_MASK) >> DAC_IRQ_STS_AHB_ERROR_SHIFT) 365 366 /* 367 * FIFO_EMPTY (W1C) 368 * 369 */ 370 #define DAC_IRQ_STS_FIFO_EMPTY_MASK (0x4U) 371 #define DAC_IRQ_STS_FIFO_EMPTY_SHIFT (2U) 372 #define DAC_IRQ_STS_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_FIFO_EMPTY_SHIFT) & DAC_IRQ_STS_FIFO_EMPTY_MASK) 373 #define DAC_IRQ_STS_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_FIFO_EMPTY_MASK) >> DAC_IRQ_STS_FIFO_EMPTY_SHIFT) 374 375 /* 376 * BUF1_CMPT (W1C) 377 * 378 */ 379 #define DAC_IRQ_STS_BUF1_CMPT_MASK (0x2U) 380 #define DAC_IRQ_STS_BUF1_CMPT_SHIFT (1U) 381 #define DAC_IRQ_STS_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF1_CMPT_SHIFT) & DAC_IRQ_STS_BUF1_CMPT_MASK) 382 #define DAC_IRQ_STS_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF1_CMPT_MASK) >> DAC_IRQ_STS_BUF1_CMPT_SHIFT) 383 384 /* 385 * BUF0_CMPT (W1C) 386 * 387 */ 388 #define DAC_IRQ_STS_BUF0_CMPT_MASK (0x1U) 389 #define DAC_IRQ_STS_BUF0_CMPT_SHIFT (0U) 390 #define DAC_IRQ_STS_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF0_CMPT_SHIFT) & DAC_IRQ_STS_BUF0_CMPT_MASK) 391 #define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) 392 393 /* Bitfield definition for register: IRQ_EN */ 394 /* 395 * STEP_CMPT (RW) 396 * 397 */ 398 #define DAC_IRQ_EN_STEP_CMPT_MASK (0x10U) 399 #define DAC_IRQ_EN_STEP_CMPT_SHIFT (4U) 400 #define DAC_IRQ_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_STEP_CMPT_SHIFT) & DAC_IRQ_EN_STEP_CMPT_MASK) 401 #define DAC_IRQ_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_STEP_CMPT_MASK) >> DAC_IRQ_EN_STEP_CMPT_SHIFT) 402 403 /* 404 * AHB_ERROR (RW) 405 * 406 */ 407 #define DAC_IRQ_EN_AHB_ERROR_MASK (0x8U) 408 #define DAC_IRQ_EN_AHB_ERROR_SHIFT (3U) 409 #define DAC_IRQ_EN_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_AHB_ERROR_SHIFT) & DAC_IRQ_EN_AHB_ERROR_MASK) 410 #define DAC_IRQ_EN_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_AHB_ERROR_MASK) >> DAC_IRQ_EN_AHB_ERROR_SHIFT) 411 412 /* 413 * FIFO_EMPTY (RW) 414 * 415 */ 416 #define DAC_IRQ_EN_FIFO_EMPTY_MASK (0x4U) 417 #define DAC_IRQ_EN_FIFO_EMPTY_SHIFT (2U) 418 #define DAC_IRQ_EN_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_FIFO_EMPTY_SHIFT) & DAC_IRQ_EN_FIFO_EMPTY_MASK) 419 #define DAC_IRQ_EN_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_FIFO_EMPTY_MASK) >> DAC_IRQ_EN_FIFO_EMPTY_SHIFT) 420 421 /* 422 * BUF1_CMPT (RW) 423 * 424 */ 425 #define DAC_IRQ_EN_BUF1_CMPT_MASK (0x2U) 426 #define DAC_IRQ_EN_BUF1_CMPT_SHIFT (1U) 427 #define DAC_IRQ_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF1_CMPT_SHIFT) & DAC_IRQ_EN_BUF1_CMPT_MASK) 428 #define DAC_IRQ_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF1_CMPT_MASK) >> DAC_IRQ_EN_BUF1_CMPT_SHIFT) 429 430 /* 431 * BUF0_CMPT (RW) 432 * 433 */ 434 #define DAC_IRQ_EN_BUF0_CMPT_MASK (0x1U) 435 #define DAC_IRQ_EN_BUF0_CMPT_SHIFT (0U) 436 #define DAC_IRQ_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF0_CMPT_SHIFT) & DAC_IRQ_EN_BUF0_CMPT_MASK) 437 #define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) 438 439 /* Bitfield definition for register: DMA_EN */ 440 /* 441 * STEP_CMPT (RW) 442 * 443 */ 444 #define DAC_DMA_EN_STEP_CMPT_MASK (0x10U) 445 #define DAC_DMA_EN_STEP_CMPT_SHIFT (4U) 446 #define DAC_DMA_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_STEP_CMPT_SHIFT) & DAC_DMA_EN_STEP_CMPT_MASK) 447 #define DAC_DMA_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_STEP_CMPT_MASK) >> DAC_DMA_EN_STEP_CMPT_SHIFT) 448 449 /* 450 * BUF1_CMPT (RW) 451 * 452 */ 453 #define DAC_DMA_EN_BUF1_CMPT_MASK (0x2U) 454 #define DAC_DMA_EN_BUF1_CMPT_SHIFT (1U) 455 #define DAC_DMA_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF1_CMPT_SHIFT) & DAC_DMA_EN_BUF1_CMPT_MASK) 456 #define DAC_DMA_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF1_CMPT_MASK) >> DAC_DMA_EN_BUF1_CMPT_SHIFT) 457 458 /* 459 * BUF0_CMPT (RW) 460 * 461 */ 462 #define DAC_DMA_EN_BUF0_CMPT_MASK (0x1U) 463 #define DAC_DMA_EN_BUF0_CMPT_SHIFT (0U) 464 #define DAC_DMA_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF0_CMPT_SHIFT) & DAC_DMA_EN_BUF0_CMPT_MASK) 465 #define DAC_DMA_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF0_CMPT_MASK) >> DAC_DMA_EN_BUF0_CMPT_SHIFT) 466 467 /* Bitfield definition for register: ANA_CFG0 */ 468 /* 469 * DAC12BIT_LP_MODE (RW) 470 * 471 */ 472 #define DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK (0x100U) 473 #define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT (8U) 474 #define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) 475 #define DAC_ANA_CFG0_DAC12BIT_LP_MODE_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) >> DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) 476 477 /* 478 * DAC_CONFIG (RW) 479 * 480 */ 481 #define DAC_ANA_CFG0_DAC_CONFIG_MASK (0xF0U) 482 #define DAC_ANA_CFG0_DAC_CONFIG_SHIFT (4U) 483 #define DAC_ANA_CFG0_DAC_CONFIG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC_CONFIG_SHIFT) & DAC_ANA_CFG0_DAC_CONFIG_MASK) 484 #define DAC_ANA_CFG0_DAC_CONFIG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC_CONFIG_MASK) >> DAC_ANA_CFG0_DAC_CONFIG_SHIFT) 485 486 /* 487 * CALI_DELTA_V_CFG (RW) 488 * 489 */ 490 #define DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK (0xCU) 491 #define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT (2U) 492 #define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) 493 #define DAC_ANA_CFG0_CALI_DELTA_V_CFG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) >> DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) 494 495 /* 496 * BYPASS_CALI_GM (RW) 497 * 498 */ 499 #define DAC_ANA_CFG0_BYPASS_CALI_GM_MASK (0x2U) 500 #define DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT (1U) 501 #define DAC_ANA_CFG0_BYPASS_CALI_GM_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) 502 #define DAC_ANA_CFG0_BYPASS_CALI_GM_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) >> DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) 503 504 /* 505 * DAC12BIT_EN (RW) 506 * 507 */ 508 #define DAC_ANA_CFG0_DAC12BIT_EN_MASK (0x1U) 509 #define DAC_ANA_CFG0_DAC12BIT_EN_SHIFT (0U) 510 #define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) 511 #define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) 512 513 /* Bitfield definition for register: CFG0_BAK */ 514 /* 515 * SW_DAC_DATA (RW) 516 * 517 * dac data used in direct mode(dac_mode==2'b10) 518 */ 519 #define DAC_CFG0_BAK_SW_DAC_DATA_MASK (0xFFF0000UL) 520 #define DAC_CFG0_BAK_SW_DAC_DATA_SHIFT (16U) 521 #define DAC_CFG0_BAK_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) 522 #define DAC_CFG0_BAK_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) >> DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) 523 524 /* 525 * DMA_AHB_EN (RW) 526 * 527 * set to enable internal DMA, it will read one burst if enough space in FIFO. 528 * Should only be used in buffer mode. 529 */ 530 #define DAC_CFG0_BAK_DMA_AHB_EN_MASK (0x200U) 531 #define DAC_CFG0_BAK_DMA_AHB_EN_SHIFT (9U) 532 #define DAC_CFG0_BAK_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) 533 #define DAC_CFG0_BAK_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) >> DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) 534 535 /* 536 * SYNC_MODE (RW) 537 * 538 * 1: sync dac clock and ahb clock. 539 * all HW trigger signals are pulse in sync mode, can get faster response; 540 * 0: async dac clock and ahb_clock 541 * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) 542 */ 543 #define DAC_CFG0_BAK_SYNC_MODE_MASK (0x100U) 544 #define DAC_CFG0_BAK_SYNC_MODE_SHIFT (8U) 545 #define DAC_CFG0_BAK_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SYNC_MODE_SHIFT) & DAC_CFG0_BAK_SYNC_MODE_MASK) 546 #define DAC_CFG0_BAK_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SYNC_MODE_MASK) >> DAC_CFG0_BAK_SYNC_MODE_SHIFT) 547 548 /* 549 * TRIG_MODE (RW) 550 * 551 * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 552 * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. 553 */ 554 #define DAC_CFG0_BAK_TRIG_MODE_MASK (0x80U) 555 #define DAC_CFG0_BAK_TRIG_MODE_SHIFT (7U) 556 #define DAC_CFG0_BAK_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_TRIG_MODE_SHIFT) & DAC_CFG0_BAK_TRIG_MODE_MASK) 557 #define DAC_CFG0_BAK_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_TRIG_MODE_MASK) >> DAC_CFG0_BAK_TRIG_MODE_SHIFT) 558 559 /* 560 * HW_TRIG_EN (RW) 561 * 562 * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode 563 */ 564 #define DAC_CFG0_BAK_HW_TRIG_EN_MASK (0x40U) 565 #define DAC_CFG0_BAK_HW_TRIG_EN_SHIFT (6U) 566 #define DAC_CFG0_BAK_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) 567 #define DAC_CFG0_BAK_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) >> DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) 568 569 /* 570 * DAC_MODE (RW) 571 * 572 * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 573 * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 574 * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; 575 */ 576 #define DAC_CFG0_BAK_DAC_MODE_MASK (0x30U) 577 #define DAC_CFG0_BAK_DAC_MODE_SHIFT (4U) 578 #define DAC_CFG0_BAK_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DAC_MODE_SHIFT) & DAC_CFG0_BAK_DAC_MODE_MASK) 579 #define DAC_CFG0_BAK_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DAC_MODE_MASK) >> DAC_CFG0_BAK_DAC_MODE_SHIFT) 580 581 /* 582 * BUF_DATA_MODE (RW) 583 * 584 * data structure for buffer mode, 585 * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 586 * 1: each 32-bit data contains 1 point, b11:0 for first 587 */ 588 #define DAC_CFG0_BAK_BUF_DATA_MODE_MASK (0x8U) 589 #define DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT (3U) 590 #define DAC_CFG0_BAK_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) 591 #define DAC_CFG0_BAK_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) >> DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) 592 593 /* 594 * HBURST_CFG (RW) 595 * 596 * DAC support following fixed burst only 597 * 000-SINGLE; 011-INCR4; 101: INCR8 598 * others are reserved 599 */ 600 #define DAC_CFG0_BAK_HBURST_CFG_MASK (0x7U) 601 #define DAC_CFG0_BAK_HBURST_CFG_SHIFT (0U) 602 #define DAC_CFG0_BAK_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HBURST_CFG_SHIFT) & DAC_CFG0_BAK_HBURST_CFG_MASK) 603 #define DAC_CFG0_BAK_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HBURST_CFG_MASK) >> DAC_CFG0_BAK_HBURST_CFG_SHIFT) 604 605 /* Bitfield definition for register: STATUS0 */ 606 /* 607 * CUR_BUF_OFFSET (RW) 608 * 609 */ 610 #define DAC_STATUS0_CUR_BUF_OFFSET_MASK (0xFFFF00UL) 611 #define DAC_STATUS0_CUR_BUF_OFFSET_SHIFT (8U) 612 #define DAC_STATUS0_CUR_BUF_OFFSET_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) 613 #define DAC_STATUS0_CUR_BUF_OFFSET_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) >> DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) 614 615 /* 616 * CUR_BUF_INDEX (RW) 617 * 618 */ 619 #define DAC_STATUS0_CUR_BUF_INDEX_MASK (0x80U) 620 #define DAC_STATUS0_CUR_BUF_INDEX_SHIFT (7U) 621 #define DAC_STATUS0_CUR_BUF_INDEX_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_INDEX_SHIFT) & DAC_STATUS0_CUR_BUF_INDEX_MASK) 622 #define DAC_STATUS0_CUR_BUF_INDEX_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_INDEX_MASK) >> DAC_STATUS0_CUR_BUF_INDEX_SHIFT) 623 624 625 626 /* STEP_CFG register group index macro definition */ 627 #define DAC_STEP_CFG_STEP0 (0UL) 628 #define DAC_STEP_CFG_STEP1 (1UL) 629 #define DAC_STEP_CFG_STEP2 (2UL) 630 #define DAC_STEP_CFG_STEP3 (3UL) 631 632 /* BUF_ADDR register group index macro definition */ 633 #define DAC_BUF_ADDR_BUF0 (0UL) 634 #define DAC_BUF_ADDR_BUF1 (1UL) 635 636 637 #endif /* HPM_DAC_H */ 638