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Searched defs:CACHE_LINE_SIZE (Results 1 – 5 of 5) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/targets/hi3861v100/include/
Dtarget_config.h232 #define CACHE_LINE_SIZE 32 // cache line size, macro
/device/soc/rockchip/rk2206/hardware/lib/CMSIS/Device/RK2206/Include/
Dsoc.h200 #define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) macro
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
Dosal_mmz.h22 #define CACHE_LINE_SIZE 0x40 macro
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
Dosal_mmz.h21 #define CACHE_LINE_SIZE 0x40 macro
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/include/
Dosal_mmz.h24 #define CACHE_LINE_SIZE 0x40 macro