1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_CAM_H 10 #define HPM_CAM_H 11 12 typedef struct { 13 __RW uint32_t CR1; /* 0x0: Control Register */ 14 __RW uint32_t INT_EN; /* 0x4: Interrupt Enable Register */ 15 __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ 16 __RW uint32_t CR2; /* 0x10: Control 2 Register */ 17 __R uint8_t RESERVED1[16]; /* 0x14 - 0x23: Reserved */ 18 __RW uint32_t STA; /* 0x24: Status Register */ 19 __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ 20 __RW uint32_t DMASA_FB1; /* 0x30: Pixel DMA Frame Buffer 1 Address */ 21 __RW uint32_t DMASA_FB2; /* 0x34: Pixel DMA Frame Buffer 2 Address */ 22 __RW uint32_t BUF_PARA; /* 0x38: Buffer Parameters Register */ 23 __RW uint32_t IDEAL_WN_SIZE; /* 0x3C: Ideal Image Size Register */ 24 __R uint8_t RESERVED3[12]; /* 0x40 - 0x4B: Reserved */ 25 __RW uint32_t CR18; /* 0x4C: Control CR18 Register */ 26 __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ 27 __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ 28 __RW uint32_t CR20; /* 0x58: Control CR20 Register */ 29 __R uint8_t RESERVED4[20]; /* 0x5C - 0x6F: Reserved */ 30 __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ 31 __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ 32 __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ 33 __RW uint32_t CLRKEY_LOW; /* 0x7C: Low Color Key Register */ 34 __RW uint32_t CLRKEY_HIGH; /* 0x80: High Color Key Register */ 35 __R uint8_t RESERVED5[12]; /* 0x84 - 0x8F: Reserved */ 36 __R uint32_t HISTOGRAM_FIFO[256]; /* 0x90 - 0x48C: Histogram Registers */ 37 __RW uint32_t ROI_WIDTH; /* 0x490: Roi Width Config Register */ 38 __RW uint32_t ROI_HEIGHT; /* 0x494: Roi Width Config Register */ 39 __RW uint32_t PRO_CTRL; /* 0x498: Pro Config Register */ 40 __RW uint32_t ACT_SIZE; /* 0x49C: actual size */ 41 __RW uint32_t VSYNC_VALID_CNT; /* 0x4A0: vsync valid counter */ 42 __RW uint32_t HSYNC_VALID_CNT; /* 0x4A4: hsync valid counter */ 43 __RW uint32_t VALID_MARGIN; /* 0x4A8: valid margin */ 44 __RW uint32_t ALARM_SET; /* 0x4AC: alarm set */ 45 } CAM_Type; 46 47 48 /* Bitfield definition for register: CR1 */ 49 /* 50 * INV_DEN (RW) 51 * 52 * invert den pad input before it is used 53 */ 54 #define CAM_CR1_INV_DEN_MASK (0x40000000UL) 55 #define CAM_CR1_INV_DEN_SHIFT (30U) 56 #define CAM_CR1_INV_DEN_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DEN_SHIFT) & CAM_CR1_INV_DEN_MASK) 57 #define CAM_CR1_INV_DEN_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DEN_MASK) >> CAM_CR1_INV_DEN_SHIFT) 58 59 /* 60 * COLOR_EXT (RW) 61 * 62 * If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. 63 * The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. 64 */ 65 #define CAM_CR1_COLOR_EXT_MASK (0x20000000UL) 66 #define CAM_CR1_COLOR_EXT_SHIFT (29U) 67 #define CAM_CR1_COLOR_EXT_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_EXT_SHIFT) & CAM_CR1_COLOR_EXT_MASK) 68 #define CAM_CR1_COLOR_EXT_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_EXT_MASK) >> CAM_CR1_COLOR_EXT_SHIFT) 69 70 /* 71 * INV_PIXCLK (RW) 72 * 73 * invert pixclk pad input before it is used 74 */ 75 #define CAM_CR1_INV_PIXCLK_MASK (0x10000000UL) 76 #define CAM_CR1_INV_PIXCLK_SHIFT (28U) 77 #define CAM_CR1_INV_PIXCLK_SET(x) (((uint32_t)(x) << CAM_CR1_INV_PIXCLK_SHIFT) & CAM_CR1_INV_PIXCLK_MASK) 78 #define CAM_CR1_INV_PIXCLK_GET(x) (((uint32_t)(x) & CAM_CR1_INV_PIXCLK_MASK) >> CAM_CR1_INV_PIXCLK_SHIFT) 79 80 /* 81 * INV_HSYNC (RW) 82 * 83 * invert hsync pad input before it is used 84 */ 85 #define CAM_CR1_INV_HSYNC_MASK (0x8000000UL) 86 #define CAM_CR1_INV_HSYNC_SHIFT (27U) 87 #define CAM_CR1_INV_HSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_HSYNC_SHIFT) & CAM_CR1_INV_HSYNC_MASK) 88 #define CAM_CR1_INV_HSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_HSYNC_MASK) >> CAM_CR1_INV_HSYNC_SHIFT) 89 90 /* 91 * INV_VSYNC (RW) 92 * 93 * invert vsync pad input before it is used 94 */ 95 #define CAM_CR1_INV_VSYNC_MASK (0x4000000UL) 96 #define CAM_CR1_INV_VSYNC_SHIFT (26U) 97 #define CAM_CR1_INV_VSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_VSYNC_SHIFT) & CAM_CR1_INV_VSYNC_MASK) 98 #define CAM_CR1_INV_VSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_VSYNC_MASK) >> CAM_CR1_INV_VSYNC_SHIFT) 99 100 /* 101 * SWAP16_EN (RW) 102 * 103 * SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. 104 * NOTE: Example of swapping enabled: 105 * Data input to FIFO = 0x11223344 106 * Data in RX FIFO = 0x 33441122 107 * NOTE: Example of swapping disabled: 108 * Data input to FIFO = 0x11223344 109 * Data in RX FIFO = 0x11223344 110 * 0 Disable swapping 111 * 1 Enable swapping 112 */ 113 #define CAM_CR1_SWAP16_EN_MASK (0x2000000UL) 114 #define CAM_CR1_SWAP16_EN_SHIFT (25U) 115 #define CAM_CR1_SWAP16_EN_SET(x) (((uint32_t)(x) << CAM_CR1_SWAP16_EN_SHIFT) & CAM_CR1_SWAP16_EN_MASK) 116 #define CAM_CR1_SWAP16_EN_GET(x) (((uint32_t)(x) & CAM_CR1_SWAP16_EN_MASK) >> CAM_CR1_SWAP16_EN_SHIFT) 117 118 /* 119 * PACK_DIR (RW) 120 * 121 * Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. 122 * 0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. 123 * 1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. 124 */ 125 #define CAM_CR1_PACK_DIR_MASK (0x1000000UL) 126 #define CAM_CR1_PACK_DIR_SHIFT (24U) 127 #define CAM_CR1_PACK_DIR_SET(x) (((uint32_t)(x) << CAM_CR1_PACK_DIR_SHIFT) & CAM_CR1_PACK_DIR_MASK) 128 #define CAM_CR1_PACK_DIR_GET(x) (((uint32_t)(x) & CAM_CR1_PACK_DIR_MASK) >> CAM_CR1_PACK_DIR_SHIFT) 129 130 /* 131 * RESTART_BUSPTR (RW) 132 * 133 * force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer 134 */ 135 #define CAM_CR1_RESTART_BUSPTR_MASK (0x800000UL) 136 #define CAM_CR1_RESTART_BUSPTR_SHIFT (23U) 137 #define CAM_CR1_RESTART_BUSPTR_SET(x) (((uint32_t)(x) << CAM_CR1_RESTART_BUSPTR_SHIFT) & CAM_CR1_RESTART_BUSPTR_MASK) 138 #define CAM_CR1_RESTART_BUSPTR_GET(x) (((uint32_t)(x) & CAM_CR1_RESTART_BUSPTR_MASK) >> CAM_CR1_RESTART_BUSPTR_SHIFT) 139 140 /* 141 * ASYNC_RXFIFO_CLR (RW) 142 * 143 * ASynchronous Rx FIFO Clear. 144 * When asserted, this bit clears RXFIFO immediately. 145 * It will be auto-cleared. 146 */ 147 #define CAM_CR1_ASYNC_RXFIFO_CLR_MASK (0x100000UL) 148 #define CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT (20U) 149 #define CAM_CR1_ASYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) 150 #define CAM_CR1_ASYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) >> CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) 151 152 /* 153 * SYNC_RXFIFO_CLR (RW) 154 * 155 * Synchronous Rx FIFO Clear. 156 * When asserted, this bit clears RXFIFO on every SOF. 157 */ 158 #define CAM_CR1_SYNC_RXFIFO_CLR_MASK (0x80000UL) 159 #define CAM_CR1_SYNC_RXFIFO_CLR_SHIFT (19U) 160 #define CAM_CR1_SYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) 161 #define CAM_CR1_SYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) >> CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) 162 163 /* 164 * SOF_INT_POL (RW) 165 * 166 * SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. 167 * 0 SOF interrupt is generated on SOF falling edge 168 * 1 SOF interrupt is generated on SOF rising edge 169 */ 170 #define CAM_CR1_SOF_INT_POL_MASK (0x20000UL) 171 #define CAM_CR1_SOF_INT_POL_SHIFT (17U) 172 #define CAM_CR1_SOF_INT_POL_SET(x) (((uint32_t)(x) << CAM_CR1_SOF_INT_POL_SHIFT) & CAM_CR1_SOF_INT_POL_MASK) 173 #define CAM_CR1_SOF_INT_POL_GET(x) (((uint32_t)(x) & CAM_CR1_SOF_INT_POL_MASK) >> CAM_CR1_SOF_INT_POL_SHIFT) 174 175 /* 176 * INV_DATA (RW) 177 * 178 * Invert Data Input. This bit enables or disables internal inverters on the data lines. 179 * 0 CAM_D data lines are directly applied to internal circuitry 180 * 1 CAM_D data lines are inverted before applied to internal circuitry 181 */ 182 #define CAM_CR1_INV_DATA_MASK (0x8000U) 183 #define CAM_CR1_INV_DATA_SHIFT (15U) 184 #define CAM_CR1_INV_DATA_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DATA_SHIFT) & CAM_CR1_INV_DATA_MASK) 185 #define CAM_CR1_INV_DATA_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DATA_MASK) >> CAM_CR1_INV_DATA_SHIFT) 186 187 /* 188 * STORAGE_MODE (RW) 189 * 190 * 00: Normal Mode (one plane mode) 191 * 01: Two Plane Mode (Y, UV plane) 192 * 10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 193 * 11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 194 */ 195 #define CAM_CR1_STORAGE_MODE_MASK (0xC00U) 196 #define CAM_CR1_STORAGE_MODE_SHIFT (10U) 197 #define CAM_CR1_STORAGE_MODE_SET(x) (((uint32_t)(x) << CAM_CR1_STORAGE_MODE_SHIFT) & CAM_CR1_STORAGE_MODE_MASK) 198 #define CAM_CR1_STORAGE_MODE_GET(x) (((uint32_t)(x) & CAM_CR1_STORAGE_MODE_MASK) >> CAM_CR1_STORAGE_MODE_SHIFT) 199 200 /* 201 * COLOR_FORMATS (RW) 202 * 203 * input color formats: 204 * 0010b:24bit:RGB888 205 * 0011b:24bit:RGB666 206 * 0100b:16bit:RGB565 207 * 0101b:16bit:RGB444 208 * 0110b:16bit:RGB555 209 * 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) 210 * YUV 211 * YCrCb 212 * Note: YUV420 is not supported. 213 * 1000b: 24bit: YUV444 214 */ 215 #define CAM_CR1_COLOR_FORMATS_MASK (0x78U) 216 #define CAM_CR1_COLOR_FORMATS_SHIFT (3U) 217 #define CAM_CR1_COLOR_FORMATS_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_FORMATS_SHIFT) & CAM_CR1_COLOR_FORMATS_MASK) 218 #define CAM_CR1_COLOR_FORMATS_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_FORMATS_MASK) >> CAM_CR1_COLOR_FORMATS_SHIFT) 219 220 /* 221 * SENSOR_BIT_WIDTH (RW) 222 * 223 * the bit width of the sensor 224 * 0: 8 bits 225 * 1: 10 bits 226 * 3:24bits 227 * Others: Undefined 228 */ 229 #define CAM_CR1_SENSOR_BIT_WIDTH_MASK (0x7U) 230 #define CAM_CR1_SENSOR_BIT_WIDTH_SHIFT (0U) 231 #define CAM_CR1_SENSOR_BIT_WIDTH_SET(x) (((uint32_t)(x) << CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) 232 #define CAM_CR1_SENSOR_BIT_WIDTH_GET(x) (((uint32_t)(x) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) >> CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) 233 234 /* Bitfield definition for register: INT_EN */ 235 /* 236 * ERR_CL_BWID_CFG_INT_EN (RW) 237 * 238 * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable 239 */ 240 #define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK (0x2000U) 241 #define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT (13U) 242 #define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) 243 #define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) >> CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) 244 245 /* 246 * HIST_DONE_INT_EN (RW) 247 * 248 * Enable hist done int 249 */ 250 #define CAM_INT_EN_HIST_DONE_INT_EN_MASK (0x1000U) 251 #define CAM_INT_EN_HIST_DONE_INT_EN_SHIFT (12U) 252 #define CAM_INT_EN_HIST_DONE_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) 253 #define CAM_INT_EN_HIST_DONE_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) >> CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) 254 255 /* 256 * HRESP_ERR_EN (RW) 257 * 258 * Hresponse Error Enable. This bit enables the hresponse error interrupt. 259 * 0 Disable hresponse error interrupt 260 * 1 Enable hresponse error interrupt 261 */ 262 #define CAM_INT_EN_HRESP_ERR_EN_MASK (0x800U) 263 #define CAM_INT_EN_HRESP_ERR_EN_SHIFT (11U) 264 #define CAM_INT_EN_HRESP_ERR_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HRESP_ERR_EN_SHIFT) & CAM_INT_EN_HRESP_ERR_EN_MASK) 265 #define CAM_INT_EN_HRESP_ERR_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HRESP_ERR_EN_MASK) >> CAM_INT_EN_HRESP_ERR_EN_SHIFT) 266 267 /* 268 * EOF_INT_EN (RW) 269 * 270 * End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. 271 * 0 EOF interrupt is disabled. 272 * 1 EOF interrupt is generated when RX count value is reached. 273 */ 274 #define CAM_INT_EN_EOF_INT_EN_MASK (0x200U) 275 #define CAM_INT_EN_EOF_INT_EN_SHIFT (9U) 276 #define CAM_INT_EN_EOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_EOF_INT_EN_SHIFT) & CAM_INT_EN_EOF_INT_EN_MASK) 277 #define CAM_INT_EN_EOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_EOF_INT_EN_MASK) >> CAM_INT_EN_EOF_INT_EN_SHIFT) 278 279 /* 280 * RF_OR_INTEN (RW) 281 * 282 * RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. 283 * 0 RxFIFO overrun interrupt is disabled 284 * 1 RxFIFO overrun interrupt is enabled 285 */ 286 #define CAM_INT_EN_RF_OR_INTEN_MASK (0x40U) 287 #define CAM_INT_EN_RF_OR_INTEN_SHIFT (6U) 288 #define CAM_INT_EN_RF_OR_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_RF_OR_INTEN_SHIFT) & CAM_INT_EN_RF_OR_INTEN_MASK) 289 #define CAM_INT_EN_RF_OR_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_RF_OR_INTEN_MASK) >> CAM_INT_EN_RF_OR_INTEN_SHIFT) 290 291 /* 292 * FB2_DMA_DONE_INTEN (RW) 293 * 294 * Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA 295 * transfer done. 296 * 0 Frame Buffer2 DMA Transfer Done interrupt disable 297 * 1 Frame Buffer2 DMA Transfer Done interrupt enable 298 */ 299 #define CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK (0x8U) 300 #define CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT (3U) 301 #define CAM_INT_EN_FB2_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) 302 #define CAM_INT_EN_FB2_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) 303 304 /* 305 * FB1_DMA_DONE_INTEN (RW) 306 * 307 * Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA 308 * transfer done. 309 * 0 Frame Buffer1 DMA Transfer Done interrupt disable 310 * 1 Frame Buffer1 DMA Transfer Done interrupt enable 311 */ 312 #define CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK (0x4U) 313 #define CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT (2U) 314 #define CAM_INT_EN_FB1_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) 315 #define CAM_INT_EN_FB1_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) 316 317 /* 318 * SOF_INT_EN (RW) 319 * 320 * Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. 321 * 0 SOF interrupt disable 322 * 1 SOF interrupt enable 323 */ 324 #define CAM_INT_EN_SOF_INT_EN_MASK (0x1U) 325 #define CAM_INT_EN_SOF_INT_EN_SHIFT (0U) 326 #define CAM_INT_EN_SOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_SOF_INT_EN_SHIFT) & CAM_INT_EN_SOF_INT_EN_MASK) 327 #define CAM_INT_EN_SOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_SOF_INT_EN_MASK) >> CAM_INT_EN_SOF_INT_EN_SHIFT) 328 329 /* Bitfield definition for register: CR2 */ 330 /* 331 * FRMCNT_15_0 (RO) 332 * 333 * Frame Counter. This is a 16-bit Frame Counter 334 * (Wraps around automatically after reaching the maximum) 335 */ 336 #define CAM_CR2_FRMCNT_15_0_MASK (0xFFFF0000UL) 337 #define CAM_CR2_FRMCNT_15_0_SHIFT (16U) 338 #define CAM_CR2_FRMCNT_15_0_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_15_0_MASK) >> CAM_CR2_FRMCNT_15_0_SHIFT) 339 340 /* 341 * FRMCNT_RST (RW) 342 * 343 * Frame Count Reset. Resets the Frame Counter. 344 * 0 Do not reset 345 * 1 Reset frame counter immediately 346 */ 347 #define CAM_CR2_FRMCNT_RST_MASK (0x8000U) 348 #define CAM_CR2_FRMCNT_RST_SHIFT (15U) 349 #define CAM_CR2_FRMCNT_RST_SET(x) (((uint32_t)(x) << CAM_CR2_FRMCNT_RST_SHIFT) & CAM_CR2_FRMCNT_RST_MASK) 350 #define CAM_CR2_FRMCNT_RST_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_RST_MASK) >> CAM_CR2_FRMCNT_RST_SHIFT) 351 352 /* 353 * RXFF_LEVEL (RW) 354 * 355 * RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. 356 * 000 4 Double words 357 * 001 8 Double words 358 * 010 16 Double words 359 * 011 24 Double words 360 * 100 32 Double words 361 * 101 48 Double words 362 * 110 64 Double words 363 * 111 96 Double words 364 */ 365 #define CAM_CR2_RXFF_LEVEL_MASK (0xE00U) 366 #define CAM_CR2_RXFF_LEVEL_SHIFT (9U) 367 #define CAM_CR2_RXFF_LEVEL_SET(x) (((uint32_t)(x) << CAM_CR2_RXFF_LEVEL_SHIFT) & CAM_CR2_RXFF_LEVEL_MASK) 368 #define CAM_CR2_RXFF_LEVEL_GET(x) (((uint32_t)(x) & CAM_CR2_RXFF_LEVEL_MASK) >> CAM_CR2_RXFF_LEVEL_SHIFT) 369 370 /* 371 * DMA_REQ_EN_RFF (RW) 372 * 373 * DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. 374 * 0 Disable the dma request 375 * 1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. 376 */ 377 #define CAM_CR2_DMA_REQ_EN_RFF_MASK (0x20U) 378 #define CAM_CR2_DMA_REQ_EN_RFF_SHIFT (5U) 379 #define CAM_CR2_DMA_REQ_EN_RFF_SET(x) (((uint32_t)(x) << CAM_CR2_DMA_REQ_EN_RFF_SHIFT) & CAM_CR2_DMA_REQ_EN_RFF_MASK) 380 #define CAM_CR2_DMA_REQ_EN_RFF_GET(x) (((uint32_t)(x) & CAM_CR2_DMA_REQ_EN_RFF_MASK) >> CAM_CR2_DMA_REQ_EN_RFF_SHIFT) 381 382 /* 383 * CLRBITFORMAT (RW) 384 * 385 * Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. 386 */ 387 #define CAM_CR2_CLRBITFORMAT_MASK (0xFU) 388 #define CAM_CR2_CLRBITFORMAT_SHIFT (0U) 389 #define CAM_CR2_CLRBITFORMAT_SET(x) (((uint32_t)(x) << CAM_CR2_CLRBITFORMAT_SHIFT) & CAM_CR2_CLRBITFORMAT_MASK) 390 #define CAM_CR2_CLRBITFORMAT_GET(x) (((uint32_t)(x) & CAM_CR2_CLRBITFORMAT_MASK) >> CAM_CR2_CLRBITFORMAT_SHIFT) 391 392 /* Bitfield definition for register: STA */ 393 /* 394 * ERR_CL_BWID_CFG (W1C) 395 * 396 * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found 397 */ 398 #define CAM_STA_ERR_CL_BWID_CFG_MASK (0x80000UL) 399 #define CAM_STA_ERR_CL_BWID_CFG_SHIFT (19U) 400 #define CAM_STA_ERR_CL_BWID_CFG_SET(x) (((uint32_t)(x) << CAM_STA_ERR_CL_BWID_CFG_SHIFT) & CAM_STA_ERR_CL_BWID_CFG_MASK) 401 #define CAM_STA_ERR_CL_BWID_CFG_GET(x) (((uint32_t)(x) & CAM_STA_ERR_CL_BWID_CFG_MASK) >> CAM_STA_ERR_CL_BWID_CFG_SHIFT) 402 403 /* 404 * HIST_DONE (W1C) 405 * 406 * hist cal done 407 */ 408 #define CAM_STA_HIST_DONE_MASK (0x40000UL) 409 #define CAM_STA_HIST_DONE_SHIFT (18U) 410 #define CAM_STA_HIST_DONE_SET(x) (((uint32_t)(x) << CAM_STA_HIST_DONE_SHIFT) & CAM_STA_HIST_DONE_MASK) 411 #define CAM_STA_HIST_DONE_GET(x) (((uint32_t)(x) & CAM_STA_HIST_DONE_MASK) >> CAM_STA_HIST_DONE_SHIFT) 412 413 /* 414 * RF_OR_INT (W1C) 415 * 416 * RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing 417 * 1) 418 * 0 RXFIFO has not overflowed. 419 * 1 RXFIFO has overflowed. 420 */ 421 #define CAM_STA_RF_OR_INT_MASK (0x2000U) 422 #define CAM_STA_RF_OR_INT_SHIFT (13U) 423 #define CAM_STA_RF_OR_INT_SET(x) (((uint32_t)(x) << CAM_STA_RF_OR_INT_SHIFT) & CAM_STA_RF_OR_INT_MASK) 424 #define CAM_STA_RF_OR_INT_GET(x) (((uint32_t)(x) & CAM_STA_RF_OR_INT_MASK) >> CAM_STA_RF_OR_INT_SHIFT) 425 426 /* 427 * DMA_TSF_DONE_FB2 (W1C) 428 * 429 * DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) 430 * 0 DMA transfer is not completed. 431 * 1 DMA transfer is completed. 432 */ 433 #define CAM_STA_DMA_TSF_DONE_FB2_MASK (0x400U) 434 #define CAM_STA_DMA_TSF_DONE_FB2_SHIFT (10U) 435 #define CAM_STA_DMA_TSF_DONE_FB2_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB2_SHIFT) & CAM_STA_DMA_TSF_DONE_FB2_MASK) 436 #define CAM_STA_DMA_TSF_DONE_FB2_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB2_MASK) >> CAM_STA_DMA_TSF_DONE_FB2_SHIFT) 437 438 /* 439 * DMA_TSF_DONE_FB1 (W1C) 440 * 441 * DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) 442 * 0 DMA transfer is not completed. 443 * 1 DMA transfer is completed. 444 */ 445 #define CAM_STA_DMA_TSF_DONE_FB1_MASK (0x200U) 446 #define CAM_STA_DMA_TSF_DONE_FB1_SHIFT (9U) 447 #define CAM_STA_DMA_TSF_DONE_FB1_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB1_SHIFT) & CAM_STA_DMA_TSF_DONE_FB1_MASK) 448 #define CAM_STA_DMA_TSF_DONE_FB1_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB1_MASK) >> CAM_STA_DMA_TSF_DONE_FB1_SHIFT) 449 450 /* 451 * EOF_INT (W1C) 452 * 453 * End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) 454 * 0 EOF is not detected. 455 * 1 EOF is detected. 456 */ 457 #define CAM_STA_EOF_INT_MASK (0x80U) 458 #define CAM_STA_EOF_INT_SHIFT (7U) 459 #define CAM_STA_EOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_EOF_INT_SHIFT) & CAM_STA_EOF_INT_MASK) 460 #define CAM_STA_EOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_EOF_INT_MASK) >> CAM_STA_EOF_INT_SHIFT) 461 462 /* 463 * SOF_INT (W1C) 464 * 465 * Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) 466 * 0 SOF is not detected. 467 * 1 SOF is detected. 468 */ 469 #define CAM_STA_SOF_INT_MASK (0x40U) 470 #define CAM_STA_SOF_INT_SHIFT (6U) 471 #define CAM_STA_SOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_SOF_INT_SHIFT) & CAM_STA_SOF_INT_MASK) 472 #define CAM_STA_SOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_SOF_INT_MASK) >> CAM_STA_SOF_INT_SHIFT) 473 474 /* 475 * HRESP_ERR_INT (W1C) 476 * 477 * Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing 478 * 1) 479 * 0 No hresponse error. 480 * 1 Hresponse error is detected. 481 */ 482 #define CAM_STA_HRESP_ERR_INT_MASK (0x4U) 483 #define CAM_STA_HRESP_ERR_INT_SHIFT (2U) 484 #define CAM_STA_HRESP_ERR_INT_SET(x) (((uint32_t)(x) << CAM_STA_HRESP_ERR_INT_SHIFT) & CAM_STA_HRESP_ERR_INT_MASK) 485 #define CAM_STA_HRESP_ERR_INT_GET(x) (((uint32_t)(x) & CAM_STA_HRESP_ERR_INT_MASK) >> CAM_STA_HRESP_ERR_INT_SHIFT) 486 487 /* Bitfield definition for register: DMASA_FB1 */ 488 /* 489 * PTR (RW) 490 * 491 * DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. 492 * In Two-Plane Mode, Y buffer1 493 */ 494 #define CAM_DMASA_FB1_PTR_MASK (0xFFFFFFFCUL) 495 #define CAM_DMASA_FB1_PTR_SHIFT (2U) 496 #define CAM_DMASA_FB1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB1_PTR_SHIFT) & CAM_DMASA_FB1_PTR_MASK) 497 #define CAM_DMASA_FB1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB1_PTR_MASK) >> CAM_DMASA_FB1_PTR_SHIFT) 498 499 /* Bitfield definition for register: DMASA_FB2 */ 500 /* 501 * PTR (RW) 502 * 503 * DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. 504 * In Two-Plane Mode, Y buffer2 505 */ 506 #define CAM_DMASA_FB2_PTR_MASK (0xFFFFFFFCUL) 507 #define CAM_DMASA_FB2_PTR_SHIFT (2U) 508 #define CAM_DMASA_FB2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB2_PTR_SHIFT) & CAM_DMASA_FB2_PTR_MASK) 509 #define CAM_DMASA_FB2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB2_PTR_MASK) >> CAM_DMASA_FB2_PTR_SHIFT) 510 511 /* Bitfield definition for register: BUF_PARA */ 512 /* 513 * LINEBSP_STRIDE (RW) 514 * 515 * Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. 516 * The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. 517 */ 518 #define CAM_BUF_PARA_LINEBSP_STRIDE_MASK (0xFFFFU) 519 #define CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT (0U) 520 #define CAM_BUF_PARA_LINEBSP_STRIDE_SET(x) (((uint32_t)(x) << CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) 521 #define CAM_BUF_PARA_LINEBSP_STRIDE_GET(x) (((uint32_t)(x) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) >> CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) 522 523 /* Bitfield definition for register: IDEAL_WN_SIZE */ 524 /* 525 * HEIGHT (RW) 526 * 527 * Image Height. Indicates how many active pixels in a column of the image from the sensor. 528 */ 529 #define CAM_IDEAL_WN_SIZE_HEIGHT_MASK (0xFFFF0000UL) 530 #define CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT (16U) 531 #define CAM_IDEAL_WN_SIZE_HEIGHT_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) 532 #define CAM_IDEAL_WN_SIZE_HEIGHT_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) >> CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) 533 534 /* 535 * WIDTH (RW) 536 * 537 * Image Width. Indicates how many active pixels in a line of the image from the sensor. 538 * The number of bytes to be transfered is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. 539 * As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. 540 */ 541 #define CAM_IDEAL_WN_SIZE_WIDTH_MASK (0xFFFFU) 542 #define CAM_IDEAL_WN_SIZE_WIDTH_SHIFT (0U) 543 #define CAM_IDEAL_WN_SIZE_WIDTH_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) 544 #define CAM_IDEAL_WN_SIZE_WIDTH_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) >> CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) 545 546 /* Bitfield definition for register: CR18 */ 547 /* 548 * CAM_ENABLE (RW) 549 * 550 * CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. 551 */ 552 #define CAM_CR18_CAM_ENABLE_MASK (0x80000000UL) 553 #define CAM_CR18_CAM_ENABLE_SHIFT (31U) 554 #define CAM_CR18_CAM_ENABLE_SET(x) (((uint32_t)(x) << CAM_CR18_CAM_ENABLE_SHIFT) & CAM_CR18_CAM_ENABLE_MASK) 555 #define CAM_CR18_CAM_ENABLE_GET(x) (((uint32_t)(x) & CAM_CR18_CAM_ENABLE_MASK) >> CAM_CR18_CAM_ENABLE_SHIFT) 556 557 /* 558 * AWQOS (RW) 559 * 560 * AWQOS for bus fabric arbitration 561 */ 562 #define CAM_CR18_AWQOS_MASK (0x780U) 563 #define CAM_CR18_AWQOS_SHIFT (7U) 564 #define CAM_CR18_AWQOS_SET(x) (((uint32_t)(x) << CAM_CR18_AWQOS_SHIFT) & CAM_CR18_AWQOS_MASK) 565 #define CAM_CR18_AWQOS_GET(x) (((uint32_t)(x) & CAM_CR18_AWQOS_MASK) >> CAM_CR18_AWQOS_SHIFT) 566 567 /* Bitfield definition for register: DMASA_UV1 */ 568 /* 569 * PTR (RW) 570 * 571 * Two Plane UV Buffer Start Address 1 572 */ 573 #define CAM_DMASA_UV1_PTR_MASK (0xFFFFFFFCUL) 574 #define CAM_DMASA_UV1_PTR_SHIFT (2U) 575 #define CAM_DMASA_UV1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV1_PTR_SHIFT) & CAM_DMASA_UV1_PTR_MASK) 576 #define CAM_DMASA_UV1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV1_PTR_MASK) >> CAM_DMASA_UV1_PTR_SHIFT) 577 578 /* Bitfield definition for register: DMASA_UV2 */ 579 /* 580 * PTR (RW) 581 * 582 * Two Plane UV Buffer Start Address 2 583 */ 584 #define CAM_DMASA_UV2_PTR_MASK (0xFFFFFFFCUL) 585 #define CAM_DMASA_UV2_PTR_SHIFT (2U) 586 #define CAM_DMASA_UV2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV2_PTR_SHIFT) & CAM_DMASA_UV2_PTR_MASK) 587 #define CAM_DMASA_UV2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV2_PTR_MASK) >> CAM_DMASA_UV2_PTR_SHIFT) 588 589 /* Bitfield definition for register: CR20 */ 590 /* 591 * BINARY_EN (RW) 592 * 593 * binary picture output enable 594 */ 595 #define CAM_CR20_BINARY_EN_MASK (0x80000000UL) 596 #define CAM_CR20_BINARY_EN_SHIFT (31U) 597 #define CAM_CR20_BINARY_EN_SET(x) (((uint32_t)(x) << CAM_CR20_BINARY_EN_SHIFT) & CAM_CR20_BINARY_EN_MASK) 598 #define CAM_CR20_BINARY_EN_GET(x) (((uint32_t)(x) & CAM_CR20_BINARY_EN_MASK) >> CAM_CR20_BINARY_EN_SHIFT) 599 600 /* 601 * HISTOGRAM_EN (RW) 602 * 603 * histogarm enable 604 */ 605 #define CAM_CR20_HISTOGRAM_EN_MASK (0x40000000UL) 606 #define CAM_CR20_HISTOGRAM_EN_SHIFT (30U) 607 #define CAM_CR20_HISTOGRAM_EN_SET(x) (((uint32_t)(x) << CAM_CR20_HISTOGRAM_EN_SHIFT) & CAM_CR20_HISTOGRAM_EN_MASK) 608 #define CAM_CR20_HISTOGRAM_EN_GET(x) (((uint32_t)(x) & CAM_CR20_HISTOGRAM_EN_MASK) >> CAM_CR20_HISTOGRAM_EN_SHIFT) 609 610 /* 611 * BIG_END (RW) 612 * 613 * Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. 614 */ 615 #define CAM_CR20_BIG_END_MASK (0x100U) 616 #define CAM_CR20_BIG_END_SHIFT (8U) 617 #define CAM_CR20_BIG_END_SET(x) (((uint32_t)(x) << CAM_CR20_BIG_END_SHIFT) & CAM_CR20_BIG_END_MASK) 618 #define CAM_CR20_BIG_END_GET(x) (((uint32_t)(x) & CAM_CR20_BIG_END_MASK) >> CAM_CR20_BIG_END_SHIFT) 619 620 /* 621 * THRESHOLD (RW) 622 * 623 * Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. 624 */ 625 #define CAM_CR20_THRESHOLD_MASK (0xFFU) 626 #define CAM_CR20_THRESHOLD_SHIFT (0U) 627 #define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) 628 #define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) 629 630 /* Bitfield definition for register: CSC_COEF0 */ 631 /* 632 * YCBCR_MODE (RW) 633 * 634 * This bit changes the behavior when performing U/V converting. 635 * 0b - Converting YUV to RGB data 636 * 1b - Converting YCbCr to RGB data 637 */ 638 #define CAM_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) 639 #define CAM_CSC_COEF0_YCBCR_MODE_SHIFT (31U) 640 #define CAM_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_YCBCR_MODE_SHIFT) & CAM_CSC_COEF0_YCBCR_MODE_MASK) 641 #define CAM_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_YCBCR_MODE_MASK) >> CAM_CSC_COEF0_YCBCR_MODE_SHIFT) 642 643 /* 644 * ENABLE (RW) 645 * 646 * Enable the CSC unit 647 * 0b - The CSC is bypassed and the input pixels are RGB data already 648 * 1b - The CSC is enabled and the pixels will be converted to RGB data 649 */ 650 #define CAM_CSC_COEF0_ENABLE_MASK (0x40000000UL) 651 #define CAM_CSC_COEF0_ENABLE_SHIFT (30U) 652 #define CAM_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_ENABLE_SHIFT) & CAM_CSC_COEF0_ENABLE_MASK) 653 #define CAM_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_ENABLE_MASK) >> CAM_CSC_COEF0_ENABLE_SHIFT) 654 655 /* 656 * C0 (RW) 657 * 658 * Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 659 */ 660 #define CAM_CSC_COEF0_C0_MASK (0x1FFC0000UL) 661 #define CAM_CSC_COEF0_C0_SHIFT (18U) 662 #define CAM_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_C0_SHIFT) & CAM_CSC_COEF0_C0_MASK) 663 #define CAM_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_C0_MASK) >> CAM_CSC_COEF0_C0_SHIFT) 664 665 /* 666 * UV_OFFSET (RW) 667 * 668 * Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. 669 * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). 670 */ 671 #define CAM_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) 672 #define CAM_CSC_COEF0_UV_OFFSET_SHIFT (9U) 673 #define CAM_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_UV_OFFSET_SHIFT) & CAM_CSC_COEF0_UV_OFFSET_MASK) 674 #define CAM_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_UV_OFFSET_MASK) >> CAM_CSC_COEF0_UV_OFFSET_SHIFT) 675 676 /* 677 * Y_OFFSET (RW) 678 * 679 * Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is 680 * typically -16 (0x1F0). 681 */ 682 #define CAM_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) 683 #define CAM_CSC_COEF0_Y_OFFSET_SHIFT (0U) 684 #define CAM_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_Y_OFFSET_SHIFT) & CAM_CSC_COEF0_Y_OFFSET_MASK) 685 #define CAM_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_Y_OFFSET_MASK) >> CAM_CSC_COEF0_Y_OFFSET_SHIFT) 686 687 /* Bitfield definition for register: CSC_COEF1 */ 688 /* 689 * C1 (RW) 690 * 691 * Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). 692 */ 693 #define CAM_CSC_COEF1_C1_MASK (0x7FF0000UL) 694 #define CAM_CSC_COEF1_C1_SHIFT (16U) 695 #define CAM_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C1_SHIFT) & CAM_CSC_COEF1_C1_MASK) 696 #define CAM_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C1_MASK) >> CAM_CSC_COEF1_C1_SHIFT) 697 698 /* 699 * C4 (RW) 700 * 701 * Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). 702 */ 703 #define CAM_CSC_COEF1_C4_MASK (0x7FFU) 704 #define CAM_CSC_COEF1_C4_SHIFT (0U) 705 #define CAM_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C4_SHIFT) & CAM_CSC_COEF1_C4_MASK) 706 #define CAM_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C4_MASK) >> CAM_CSC_COEF1_C4_SHIFT) 707 708 /* Bitfield definition for register: CSC_COEF2 */ 709 /* 710 * C2 (RW) 711 * 712 * Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). 713 */ 714 #define CAM_CSC_COEF2_C2_MASK (0x7FF0000UL) 715 #define CAM_CSC_COEF2_C2_SHIFT (16U) 716 #define CAM_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C2_SHIFT) & CAM_CSC_COEF2_C2_MASK) 717 #define CAM_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C2_MASK) >> CAM_CSC_COEF2_C2_SHIFT) 718 719 /* 720 * C3 (RW) 721 * 722 * Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). 723 */ 724 #define CAM_CSC_COEF2_C3_MASK (0x7FFU) 725 #define CAM_CSC_COEF2_C3_SHIFT (0U) 726 #define CAM_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C3_SHIFT) & CAM_CSC_COEF2_C3_MASK) 727 #define CAM_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C3_MASK) >> CAM_CSC_COEF2_C3_SHIFT) 728 729 /* Bitfield definition for register: CLRKEY_LOW */ 730 /* 731 * LIMIT (RW) 732 * 733 * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. 734 */ 735 #define CAM_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) 736 #define CAM_CLRKEY_LOW_LIMIT_SHIFT (0U) 737 #define CAM_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_LOW_LIMIT_SHIFT) & CAM_CLRKEY_LOW_LIMIT_MASK) 738 #define CAM_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_LOW_LIMIT_MASK) >> CAM_CLRKEY_LOW_LIMIT_SHIFT) 739 740 /* Bitfield definition for register: CLRKEY_HIGH */ 741 /* 742 * LIMIT (RW) 743 * 744 * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. 745 */ 746 #define CAM_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) 747 #define CAM_CLRKEY_HIGH_LIMIT_SHIFT (0U) 748 #define CAM_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_HIGH_LIMIT_SHIFT) & CAM_CLRKEY_HIGH_LIMIT_MASK) 749 #define CAM_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_HIGH_LIMIT_MASK) >> CAM_CLRKEY_HIGH_LIMIT_SHIFT) 750 751 /* Bitfield definition for register array: HISTOGRAM_FIFO */ 752 /* 753 * HIST_Y (RO) 754 * 755 * the appearance of bin x (x=(address-DATA0)/4) 756 */ 757 #define CAM_HISTOGRAM_FIFO_HIST_Y_MASK (0xFFFFFFUL) 758 #define CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT (0U) 759 #define CAM_HISTOGRAM_FIFO_HIST_Y_GET(x) (((uint32_t)(x) & CAM_HISTOGRAM_FIFO_HIST_Y_MASK) >> CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT) 760 761 /* Bitfield definition for register: ROI_WIDTH */ 762 /* 763 * ROI_WIDTH_END (RW) 764 * 765 * end address of width for roi 766 */ 767 #define CAM_ROI_WIDTH_ROI_WIDTH_END_MASK (0xFFFF0000UL) 768 #define CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT (16U) 769 #define CAM_ROI_WIDTH_ROI_WIDTH_END_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) 770 #define CAM_ROI_WIDTH_ROI_WIDTH_END_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) 771 772 /* 773 * ROI_WIDTH_START (RW) 774 * 775 * start address of width for roi 776 */ 777 #define CAM_ROI_WIDTH_ROI_WIDTH_START_MASK (0xFFFFU) 778 #define CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT (0U) 779 #define CAM_ROI_WIDTH_ROI_WIDTH_START_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) 780 #define CAM_ROI_WIDTH_ROI_WIDTH_START_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) 781 782 /* Bitfield definition for register: ROI_HEIGHT */ 783 /* 784 * ROI_HEIGHT_END (RW) 785 * 786 * end address of height for roi 787 */ 788 #define CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK (0xFFFF0000UL) 789 #define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT (16U) 790 #define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) 791 #define CAM_ROI_HEIGHT_ROI_HEIGHT_END_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) 792 793 /* 794 * ROI_HEIGHT_START (RW) 795 * 796 * start address of height for roi 797 */ 798 #define CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK (0xFFFFU) 799 #define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT (0U) 800 #define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) 801 #define CAM_ROI_HEIGHT_ROI_HEIGHT_START_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) 802 803 /* Bitfield definition for register: PRO_CTRL */ 804 /* 805 * ERR_INJECT (RW) 806 * 807 * 0 generate alarm in normal mode 808 * 1 force to generate fatal alarm 809 */ 810 #define CAM_PRO_CTRL_ERR_INJECT_MASK (0x4000U) 811 #define CAM_PRO_CTRL_ERR_INJECT_SHIFT (14U) 812 #define CAM_PRO_CTRL_ERR_INJECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ERR_INJECT_SHIFT) & CAM_PRO_CTRL_ERR_INJECT_MASK) 813 #define CAM_PRO_CTRL_ERR_INJECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ERR_INJECT_MASK) >> CAM_PRO_CTRL_ERR_INJECT_SHIFT) 814 815 /* 816 * ROI_UPDATE (RW) 817 * 818 * roi configration update 819 */ 820 #define CAM_PRO_CTRL_ROI_UPDATE_MASK (0x80U) 821 #define CAM_PRO_CTRL_ROI_UPDATE_SHIFT (7U) 822 #define CAM_PRO_CTRL_ROI_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ROI_UPDATE_SHIFT) & CAM_PRO_CTRL_ROI_UPDATE_MASK) 823 #define CAM_PRO_CTRL_ROI_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ROI_UPDATE_MASK) >> CAM_PRO_CTRL_ROI_UPDATE_SHIFT) 824 825 /* 826 * SCALE_UPDATE (RW) 827 * 828 * scale configration update 829 */ 830 #define CAM_PRO_CTRL_SCALE_UPDATE_MASK (0x40U) 831 #define CAM_PRO_CTRL_SCALE_UPDATE_SHIFT (6U) 832 #define CAM_PRO_CTRL_SCALE_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) 833 #define CAM_PRO_CTRL_SCALE_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) >> CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) 834 835 /* 836 * SCALE_HEIGHT_SELECT (RW) 837 * 838 * 000 keep all pixel for height 839 * 001 keep 1 for every 2 pixel for height 840 * 010 keep 1 for every 3 pixel for height 841 * 011 keep 1 for every 4 pixel for height 842 * 100 keep 1 for every 5 pixel for height 843 * 101 keep 1 for every 6 pixel for height 844 * 110 keep 1 for every 7 pixel for height 845 * 111 keep 1 for every 8 pixel for height 846 */ 847 #define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK (0x38U) 848 #define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT (3U) 849 #define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) 850 #define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) 851 852 /* 853 * SCALE_WIDTH_SELECT (RW) 854 * 855 * 000 keep all pixel for width 856 * 001 keep 1 for every 2 pixel for width 857 * 010 keep 1 for every 3 pixel for width 858 * 011 keep 1 for every 4 pixel for width 859 * 100 keep 1 for every 5 pixel for width 860 * 101 keep 1 for every 6 pixel for width 861 * 110 keep 1 for every 7 pixel for width 862 * 111 keep 1 for every 8 pixel for width 863 */ 864 #define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK (0x7U) 865 #define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT (0U) 866 #define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) 867 #define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) 868 869 /* Bitfield definition for register: ACT_SIZE */ 870 /* 871 * ACT_HEIGHT (RW) 872 * 873 * actual height after scale and/or roi 874 */ 875 #define CAM_ACT_SIZE_ACT_HEIGHT_MASK (0xFFFF0000UL) 876 #define CAM_ACT_SIZE_ACT_HEIGHT_SHIFT (16U) 877 #define CAM_ACT_SIZE_ACT_HEIGHT_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) 878 #define CAM_ACT_SIZE_ACT_HEIGHT_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) >> CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) 879 880 /* 881 * ACT_WIDTH (RW) 882 * 883 * actual width after scale and/or roi 884 */ 885 #define CAM_ACT_SIZE_ACT_WIDTH_MASK (0xFFFFU) 886 #define CAM_ACT_SIZE_ACT_WIDTH_SHIFT (0U) 887 #define CAM_ACT_SIZE_ACT_WIDTH_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_WIDTH_SHIFT) & CAM_ACT_SIZE_ACT_WIDTH_MASK) 888 #define CAM_ACT_SIZE_ACT_WIDTH_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_WIDTH_MASK) >> CAM_ACT_SIZE_ACT_WIDTH_SHIFT) 889 890 /* Bitfield definition for register: VSYNC_VALID_CNT */ 891 /* 892 * VSYNC_VALID_CNT (RW) 893 * 894 * vsync valid counter 895 */ 896 #define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) 897 #define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT (0U) 898 #define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) 899 #define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) >> CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) 900 901 /* Bitfield definition for register: HSYNC_VALID_CNT */ 902 /* 903 * HSYNC_VALID_CNT (RW) 904 * 905 * hsync valid counter 906 */ 907 #define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) 908 #define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT (0U) 909 #define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) 910 #define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) >> CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) 911 912 /* Bitfield definition for register: VALID_MARGIN */ 913 /* 914 * HSYNC_VALID_MARGIN (RW) 915 * 916 * hsync valid margin 917 */ 918 #define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK (0xFFFF0000UL) 919 #define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT (16U) 920 #define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) 921 #define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) 922 923 /* 924 * VSYNC_VALID_MARGIN (RW) 925 * 926 * vsync valid margin 927 */ 928 #define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK (0xFFFFU) 929 #define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT (0U) 930 #define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) 931 #define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) 932 933 /* Bitfield definition for register: ALARM_SET */ 934 /* 935 * SIG_NORMAL (RW) 936 * 937 * define signal duty cycles(base clock) 938 * 0x0: disable signal 939 * 0x1: high 1, low 15 940 * 0x2: high 2, low 14 941 * …... 942 * 0xF: high 15, low 1 943 */ 944 #define CAM_ALARM_SET_SIG_NORMAL_MASK (0xF00000UL) 945 #define CAM_ALARM_SET_SIG_NORMAL_SHIFT (20U) 946 #define CAM_ALARM_SET_SIG_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_SIG_NORMAL_SHIFT) & CAM_ALARM_SET_SIG_NORMAL_MASK) 947 #define CAM_ALARM_SET_SIG_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_SIG_NORMAL_MASK) >> CAM_ALARM_SET_SIG_NORMAL_SHIFT) 948 949 /* 950 * FATAL_NORMAL (RW) 951 * 952 * define signal duty cycles(base clock) 953 * 0x0: disable signal 954 * 0x1: high 1, low 15 955 * 0x2: high 2, low 14 956 * …... 957 * 0xF: high 15, low 1 958 */ 959 #define CAM_ALARM_SET_FATAL_NORMAL_MASK (0xF0000UL) 960 #define CAM_ALARM_SET_FATAL_NORMAL_SHIFT (16U) 961 #define CAM_ALARM_SET_FATAL_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_FATAL_NORMAL_SHIFT) & CAM_ALARM_SET_FATAL_NORMAL_MASK) 962 #define CAM_ALARM_SET_FATAL_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_FATAL_NORMAL_MASK) >> CAM_ALARM_SET_FATAL_NORMAL_SHIFT) 963 964 /* 965 * PRE_DIV (RW) 966 * 967 * frequency division 968 */ 969 #define CAM_ALARM_SET_PRE_DIV_MASK (0xFFFFU) 970 #define CAM_ALARM_SET_PRE_DIV_SHIFT (0U) 971 #define CAM_ALARM_SET_PRE_DIV_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_PRE_DIV_SHIFT) & CAM_ALARM_SET_PRE_DIV_MASK) 972 #define CAM_ALARM_SET_PRE_DIV_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_PRE_DIV_MASK) >> CAM_ALARM_SET_PRE_DIV_SHIFT) 973 974 975 976 /* HISTOGRAM_FIFO register group index macro definition */ 977 #define CAM_HISTOGRAM_FIFO_DATA0 (0UL) 978 #define CAM_HISTOGRAM_FIFO_DATA1 (1UL) 979 #define CAM_HISTOGRAM_FIFO_DATA2 (2UL) 980 #define CAM_HISTOGRAM_FIFO_DATA3 (3UL) 981 #define CAM_HISTOGRAM_FIFO_DATA4 (4UL) 982 #define CAM_HISTOGRAM_FIFO_DATA5 (5UL) 983 #define CAM_HISTOGRAM_FIFO_DATA6 (6UL) 984 #define CAM_HISTOGRAM_FIFO_DATA7 (7UL) 985 #define CAM_HISTOGRAM_FIFO_DATA8 (8UL) 986 #define CAM_HISTOGRAM_FIFO_DATA9 (9UL) 987 #define CAM_HISTOGRAM_FIFO_DATA10 (10UL) 988 #define CAM_HISTOGRAM_FIFO_DATA11 (11UL) 989 #define CAM_HISTOGRAM_FIFO_DATA12 (12UL) 990 #define CAM_HISTOGRAM_FIFO_DATA13 (13UL) 991 #define CAM_HISTOGRAM_FIFO_DATA14 (14UL) 992 #define CAM_HISTOGRAM_FIFO_DATA15 (15UL) 993 #define CAM_HISTOGRAM_FIFO_DATA16 (16UL) 994 #define CAM_HISTOGRAM_FIFO_DATA17 (17UL) 995 #define CAM_HISTOGRAM_FIFO_DATA18 (18UL) 996 #define CAM_HISTOGRAM_FIFO_DATA19 (19UL) 997 #define CAM_HISTOGRAM_FIFO_DATA20 (20UL) 998 #define CAM_HISTOGRAM_FIFO_DATA21 (21UL) 999 #define CAM_HISTOGRAM_FIFO_DATA22 (22UL) 1000 #define CAM_HISTOGRAM_FIFO_DATA23 (23UL) 1001 #define CAM_HISTOGRAM_FIFO_DATA24 (24UL) 1002 #define CAM_HISTOGRAM_FIFO_DATA25 (25UL) 1003 #define CAM_HISTOGRAM_FIFO_DATA26 (26UL) 1004 #define CAM_HISTOGRAM_FIFO_DATA27 (27UL) 1005 #define CAM_HISTOGRAM_FIFO_DATA28 (28UL) 1006 #define CAM_HISTOGRAM_FIFO_DATA29 (29UL) 1007 #define CAM_HISTOGRAM_FIFO_DATA30 (30UL) 1008 #define CAM_HISTOGRAM_FIFO_DATA31 (31UL) 1009 #define CAM_HISTOGRAM_FIFO_DATA32 (32UL) 1010 #define CAM_HISTOGRAM_FIFO_DATA33 (33UL) 1011 #define CAM_HISTOGRAM_FIFO_DATA34 (34UL) 1012 #define CAM_HISTOGRAM_FIFO_DATA35 (35UL) 1013 #define CAM_HISTOGRAM_FIFO_DATA36 (36UL) 1014 #define CAM_HISTOGRAM_FIFO_DATA37 (37UL) 1015 #define CAM_HISTOGRAM_FIFO_DATA38 (38UL) 1016 #define CAM_HISTOGRAM_FIFO_DATA39 (39UL) 1017 #define CAM_HISTOGRAM_FIFO_DATA40 (40UL) 1018 #define CAM_HISTOGRAM_FIFO_DATA41 (41UL) 1019 #define CAM_HISTOGRAM_FIFO_DATA42 (42UL) 1020 #define CAM_HISTOGRAM_FIFO_DATA43 (43UL) 1021 #define CAM_HISTOGRAM_FIFO_DATA44 (44UL) 1022 #define CAM_HISTOGRAM_FIFO_DATA45 (45UL) 1023 #define CAM_HISTOGRAM_FIFO_DATA46 (46UL) 1024 #define CAM_HISTOGRAM_FIFO_DATA47 (47UL) 1025 #define CAM_HISTOGRAM_FIFO_DATA48 (48UL) 1026 #define CAM_HISTOGRAM_FIFO_DATA49 (49UL) 1027 #define CAM_HISTOGRAM_FIFO_DATA50 (50UL) 1028 #define CAM_HISTOGRAM_FIFO_DATA51 (51UL) 1029 #define CAM_HISTOGRAM_FIFO_DATA52 (52UL) 1030 #define CAM_HISTOGRAM_FIFO_DATA53 (53UL) 1031 #define CAM_HISTOGRAM_FIFO_DATA54 (54UL) 1032 #define CAM_HISTOGRAM_FIFO_DATA55 (55UL) 1033 #define CAM_HISTOGRAM_FIFO_DATA56 (56UL) 1034 #define CAM_HISTOGRAM_FIFO_DATA57 (57UL) 1035 #define CAM_HISTOGRAM_FIFO_DATA58 (58UL) 1036 #define CAM_HISTOGRAM_FIFO_DATA59 (59UL) 1037 #define CAM_HISTOGRAM_FIFO_DATA60 (60UL) 1038 #define CAM_HISTOGRAM_FIFO_DATA61 (61UL) 1039 #define CAM_HISTOGRAM_FIFO_DATA62 (62UL) 1040 #define CAM_HISTOGRAM_FIFO_DATA63 (63UL) 1041 #define CAM_HISTOGRAM_FIFO_DATA64 (64UL) 1042 #define CAM_HISTOGRAM_FIFO_DATA65 (65UL) 1043 #define CAM_HISTOGRAM_FIFO_DATA66 (66UL) 1044 #define CAM_HISTOGRAM_FIFO_DATA67 (67UL) 1045 #define CAM_HISTOGRAM_FIFO_DATA68 (68UL) 1046 #define CAM_HISTOGRAM_FIFO_DATA69 (69UL) 1047 #define CAM_HISTOGRAM_FIFO_DATA70 (70UL) 1048 #define CAM_HISTOGRAM_FIFO_DATA71 (71UL) 1049 #define CAM_HISTOGRAM_FIFO_DATA72 (72UL) 1050 #define CAM_HISTOGRAM_FIFO_DATA73 (73UL) 1051 #define CAM_HISTOGRAM_FIFO_DATA74 (74UL) 1052 #define CAM_HISTOGRAM_FIFO_DATA75 (75UL) 1053 #define CAM_HISTOGRAM_FIFO_DATA76 (76UL) 1054 #define CAM_HISTOGRAM_FIFO_DATA77 (77UL) 1055 #define CAM_HISTOGRAM_FIFO_DATA78 (78UL) 1056 #define CAM_HISTOGRAM_FIFO_DATA79 (79UL) 1057 #define CAM_HISTOGRAM_FIFO_DATA80 (80UL) 1058 #define CAM_HISTOGRAM_FIFO_DATA81 (81UL) 1059 #define CAM_HISTOGRAM_FIFO_DATA82 (82UL) 1060 #define CAM_HISTOGRAM_FIFO_DATA83 (83UL) 1061 #define CAM_HISTOGRAM_FIFO_DATA84 (84UL) 1062 #define CAM_HISTOGRAM_FIFO_DATA85 (85UL) 1063 #define CAM_HISTOGRAM_FIFO_DATA86 (86UL) 1064 #define CAM_HISTOGRAM_FIFO_DATA87 (87UL) 1065 #define CAM_HISTOGRAM_FIFO_DATA88 (88UL) 1066 #define CAM_HISTOGRAM_FIFO_DATA89 (89UL) 1067 #define CAM_HISTOGRAM_FIFO_DATA90 (90UL) 1068 #define CAM_HISTOGRAM_FIFO_DATA91 (91UL) 1069 #define CAM_HISTOGRAM_FIFO_DATA92 (92UL) 1070 #define CAM_HISTOGRAM_FIFO_DATA93 (93UL) 1071 #define CAM_HISTOGRAM_FIFO_DATA94 (94UL) 1072 #define CAM_HISTOGRAM_FIFO_DATA95 (95UL) 1073 #define CAM_HISTOGRAM_FIFO_DATA96 (96UL) 1074 #define CAM_HISTOGRAM_FIFO_DATA97 (97UL) 1075 #define CAM_HISTOGRAM_FIFO_DATA98 (98UL) 1076 #define CAM_HISTOGRAM_FIFO_DATA99 (99UL) 1077 #define CAM_HISTOGRAM_FIFO_DATA100 (100UL) 1078 #define CAM_HISTOGRAM_FIFO_DATA101 (101UL) 1079 #define CAM_HISTOGRAM_FIFO_DATA102 (102UL) 1080 #define CAM_HISTOGRAM_FIFO_DATA103 (103UL) 1081 #define CAM_HISTOGRAM_FIFO_DATA104 (104UL) 1082 #define CAM_HISTOGRAM_FIFO_DATA105 (105UL) 1083 #define CAM_HISTOGRAM_FIFO_DATA106 (106UL) 1084 #define CAM_HISTOGRAM_FIFO_DATA107 (107UL) 1085 #define CAM_HISTOGRAM_FIFO_DATA108 (108UL) 1086 #define CAM_HISTOGRAM_FIFO_DATA109 (109UL) 1087 #define CAM_HISTOGRAM_FIFO_DATA110 (110UL) 1088 #define CAM_HISTOGRAM_FIFO_DATA111 (111UL) 1089 #define CAM_HISTOGRAM_FIFO_DATA112 (112UL) 1090 #define CAM_HISTOGRAM_FIFO_DATA113 (113UL) 1091 #define CAM_HISTOGRAM_FIFO_DATA114 (114UL) 1092 #define CAM_HISTOGRAM_FIFO_DATA115 (115UL) 1093 #define CAM_HISTOGRAM_FIFO_DATA116 (116UL) 1094 #define CAM_HISTOGRAM_FIFO_DATA117 (117UL) 1095 #define CAM_HISTOGRAM_FIFO_DATA118 (118UL) 1096 #define CAM_HISTOGRAM_FIFO_DATA119 (119UL) 1097 #define CAM_HISTOGRAM_FIFO_DATA120 (120UL) 1098 #define CAM_HISTOGRAM_FIFO_DATA121 (121UL) 1099 #define CAM_HISTOGRAM_FIFO_DATA122 (122UL) 1100 #define CAM_HISTOGRAM_FIFO_DATA123 (123UL) 1101 #define CAM_HISTOGRAM_FIFO_DATA124 (124UL) 1102 #define CAM_HISTOGRAM_FIFO_DATA125 (125UL) 1103 #define CAM_HISTOGRAM_FIFO_DATA126 (126UL) 1104 #define CAM_HISTOGRAM_FIFO_DATA127 (127UL) 1105 #define CAM_HISTOGRAM_FIFO_DATA128 (128UL) 1106 #define CAM_HISTOGRAM_FIFO_DATA129 (129UL) 1107 #define CAM_HISTOGRAM_FIFO_DATA130 (130UL) 1108 #define CAM_HISTOGRAM_FIFO_DATA131 (131UL) 1109 #define CAM_HISTOGRAM_FIFO_DATA132 (132UL) 1110 #define CAM_HISTOGRAM_FIFO_DATA133 (133UL) 1111 #define CAM_HISTOGRAM_FIFO_DATA134 (134UL) 1112 #define CAM_HISTOGRAM_FIFO_DATA135 (135UL) 1113 #define CAM_HISTOGRAM_FIFO_DATA136 (136UL) 1114 #define CAM_HISTOGRAM_FIFO_DATA137 (137UL) 1115 #define CAM_HISTOGRAM_FIFO_DATA138 (138UL) 1116 #define CAM_HISTOGRAM_FIFO_DATA139 (139UL) 1117 #define CAM_HISTOGRAM_FIFO_DATA140 (140UL) 1118 #define CAM_HISTOGRAM_FIFO_DATA141 (141UL) 1119 #define CAM_HISTOGRAM_FIFO_DATA142 (142UL) 1120 #define CAM_HISTOGRAM_FIFO_DATA143 (143UL) 1121 #define CAM_HISTOGRAM_FIFO_DATA144 (144UL) 1122 #define CAM_HISTOGRAM_FIFO_DATA145 (145UL) 1123 #define CAM_HISTOGRAM_FIFO_DATA146 (146UL) 1124 #define CAM_HISTOGRAM_FIFO_DATA147 (147UL) 1125 #define CAM_HISTOGRAM_FIFO_DATA148 (148UL) 1126 #define CAM_HISTOGRAM_FIFO_DATA149 (149UL) 1127 #define CAM_HISTOGRAM_FIFO_DATA150 (150UL) 1128 #define CAM_HISTOGRAM_FIFO_DATA151 (151UL) 1129 #define CAM_HISTOGRAM_FIFO_DATA152 (152UL) 1130 #define CAM_HISTOGRAM_FIFO_DATA153 (153UL) 1131 #define CAM_HISTOGRAM_FIFO_DATA154 (154UL) 1132 #define CAM_HISTOGRAM_FIFO_DATA155 (155UL) 1133 #define CAM_HISTOGRAM_FIFO_DATA156 (156UL) 1134 #define CAM_HISTOGRAM_FIFO_DATA157 (157UL) 1135 #define CAM_HISTOGRAM_FIFO_DATA158 (158UL) 1136 #define CAM_HISTOGRAM_FIFO_DATA159 (159UL) 1137 #define CAM_HISTOGRAM_FIFO_DATA160 (160UL) 1138 #define CAM_HISTOGRAM_FIFO_DATA161 (161UL) 1139 #define CAM_HISTOGRAM_FIFO_DATA162 (162UL) 1140 #define CAM_HISTOGRAM_FIFO_DATA163 (163UL) 1141 #define CAM_HISTOGRAM_FIFO_DATA164 (164UL) 1142 #define CAM_HISTOGRAM_FIFO_DATA165 (165UL) 1143 #define CAM_HISTOGRAM_FIFO_DATA166 (166UL) 1144 #define CAM_HISTOGRAM_FIFO_DATA167 (167UL) 1145 #define CAM_HISTOGRAM_FIFO_DATA168 (168UL) 1146 #define CAM_HISTOGRAM_FIFO_DATA169 (169UL) 1147 #define CAM_HISTOGRAM_FIFO_DATA170 (170UL) 1148 #define CAM_HISTOGRAM_FIFO_DATA171 (171UL) 1149 #define CAM_HISTOGRAM_FIFO_DATA172 (172UL) 1150 #define CAM_HISTOGRAM_FIFO_DATA173 (173UL) 1151 #define CAM_HISTOGRAM_FIFO_DATA174 (174UL) 1152 #define CAM_HISTOGRAM_FIFO_DATA175 (175UL) 1153 #define CAM_HISTOGRAM_FIFO_DATA176 (176UL) 1154 #define CAM_HISTOGRAM_FIFO_DATA177 (177UL) 1155 #define CAM_HISTOGRAM_FIFO_DATA178 (178UL) 1156 #define CAM_HISTOGRAM_FIFO_DATA179 (179UL) 1157 #define CAM_HISTOGRAM_FIFO_DATA180 (180UL) 1158 #define CAM_HISTOGRAM_FIFO_DATA181 (181UL) 1159 #define CAM_HISTOGRAM_FIFO_DATA182 (182UL) 1160 #define CAM_HISTOGRAM_FIFO_DATA183 (183UL) 1161 #define CAM_HISTOGRAM_FIFO_DATA184 (184UL) 1162 #define CAM_HISTOGRAM_FIFO_DATA185 (185UL) 1163 #define CAM_HISTOGRAM_FIFO_DATA186 (186UL) 1164 #define CAM_HISTOGRAM_FIFO_DATA187 (187UL) 1165 #define CAM_HISTOGRAM_FIFO_DATA188 (188UL) 1166 #define CAM_HISTOGRAM_FIFO_DATA189 (189UL) 1167 #define CAM_HISTOGRAM_FIFO_DATA190 (190UL) 1168 #define CAM_HISTOGRAM_FIFO_DATA191 (191UL) 1169 #define CAM_HISTOGRAM_FIFO_DATA192 (192UL) 1170 #define CAM_HISTOGRAM_FIFO_DATA193 (193UL) 1171 #define CAM_HISTOGRAM_FIFO_DATA194 (194UL) 1172 #define CAM_HISTOGRAM_FIFO_DATA195 (195UL) 1173 #define CAM_HISTOGRAM_FIFO_DATA196 (196UL) 1174 #define CAM_HISTOGRAM_FIFO_DATA197 (197UL) 1175 #define CAM_HISTOGRAM_FIFO_DATA198 (198UL) 1176 #define CAM_HISTOGRAM_FIFO_DATA199 (199UL) 1177 #define CAM_HISTOGRAM_FIFO_DATA200 (200UL) 1178 #define CAM_HISTOGRAM_FIFO_DATA201 (201UL) 1179 #define CAM_HISTOGRAM_FIFO_DATA202 (202UL) 1180 #define CAM_HISTOGRAM_FIFO_DATA203 (203UL) 1181 #define CAM_HISTOGRAM_FIFO_DATA204 (204UL) 1182 #define CAM_HISTOGRAM_FIFO_DATA205 (205UL) 1183 #define CAM_HISTOGRAM_FIFO_DATA206 (206UL) 1184 #define CAM_HISTOGRAM_FIFO_DATA207 (207UL) 1185 #define CAM_HISTOGRAM_FIFO_DATA208 (208UL) 1186 #define CAM_HISTOGRAM_FIFO_DATA209 (209UL) 1187 #define CAM_HISTOGRAM_FIFO_DATA210 (210UL) 1188 #define CAM_HISTOGRAM_FIFO_DATA211 (211UL) 1189 #define CAM_HISTOGRAM_FIFO_DATA212 (212UL) 1190 #define CAM_HISTOGRAM_FIFO_DATA213 (213UL) 1191 #define CAM_HISTOGRAM_FIFO_DATA214 (214UL) 1192 #define CAM_HISTOGRAM_FIFO_DATA215 (215UL) 1193 #define CAM_HISTOGRAM_FIFO_DATA216 (216UL) 1194 #define CAM_HISTOGRAM_FIFO_DATA217 (217UL) 1195 #define CAM_HISTOGRAM_FIFO_DATA218 (218UL) 1196 #define CAM_HISTOGRAM_FIFO_DATA219 (219UL) 1197 #define CAM_HISTOGRAM_FIFO_DATA220 (220UL) 1198 #define CAM_HISTOGRAM_FIFO_DATA221 (221UL) 1199 #define CAM_HISTOGRAM_FIFO_DATA222 (222UL) 1200 #define CAM_HISTOGRAM_FIFO_DATA223 (223UL) 1201 #define CAM_HISTOGRAM_FIFO_DATA224 (224UL) 1202 #define CAM_HISTOGRAM_FIFO_DATA225 (225UL) 1203 #define CAM_HISTOGRAM_FIFO_DATA226 (226UL) 1204 #define CAM_HISTOGRAM_FIFO_DATA227 (227UL) 1205 #define CAM_HISTOGRAM_FIFO_DATA228 (228UL) 1206 #define CAM_HISTOGRAM_FIFO_DATA229 (229UL) 1207 #define CAM_HISTOGRAM_FIFO_DATA230 (230UL) 1208 #define CAM_HISTOGRAM_FIFO_DATA231 (231UL) 1209 #define CAM_HISTOGRAM_FIFO_DATA232 (232UL) 1210 #define CAM_HISTOGRAM_FIFO_DATA233 (233UL) 1211 #define CAM_HISTOGRAM_FIFO_DATA234 (234UL) 1212 #define CAM_HISTOGRAM_FIFO_DATA235 (235UL) 1213 #define CAM_HISTOGRAM_FIFO_DATA236 (236UL) 1214 #define CAM_HISTOGRAM_FIFO_DATA237 (237UL) 1215 #define CAM_HISTOGRAM_FIFO_DATA238 (238UL) 1216 #define CAM_HISTOGRAM_FIFO_DATA239 (239UL) 1217 #define CAM_HISTOGRAM_FIFO_DATA240 (240UL) 1218 #define CAM_HISTOGRAM_FIFO_DATA241 (241UL) 1219 #define CAM_HISTOGRAM_FIFO_DATA242 (242UL) 1220 #define CAM_HISTOGRAM_FIFO_DATA243 (243UL) 1221 #define CAM_HISTOGRAM_FIFO_DATA244 (244UL) 1222 #define CAM_HISTOGRAM_FIFO_DATA245 (245UL) 1223 #define CAM_HISTOGRAM_FIFO_DATA246 (246UL) 1224 #define CAM_HISTOGRAM_FIFO_DATA247 (247UL) 1225 #define CAM_HISTOGRAM_FIFO_DATA248 (248UL) 1226 #define CAM_HISTOGRAM_FIFO_DATA249 (249UL) 1227 #define CAM_HISTOGRAM_FIFO_DATA250 (250UL) 1228 #define CAM_HISTOGRAM_FIFO_DATA251 (251UL) 1229 #define CAM_HISTOGRAM_FIFO_DATA252 (252UL) 1230 #define CAM_HISTOGRAM_FIFO_DATA253 (253UL) 1231 #define CAM_HISTOGRAM_FIFO_DATA254 (254UL) 1232 #define CAM_HISTOGRAM_FIFO_DATA255 (255UL) 1233 1234 1235 #endif /* HPM_CAM_H */ 1236