1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_GPTMR_H 10 #define HPM_GPTMR_H 11 12 typedef struct { 13 struct { 14 __RW uint32_t CR; /* 0x0: Control Register */ 15 __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ 16 __RW uint32_t RLD; /* 0xC: Reload register */ 17 __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ 18 __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ 19 __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ 20 __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ 21 __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ 22 __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ 23 __R uint32_t CNT; /* 0x30: Counter */ 24 __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ 25 } CHANNEL[4]; 26 __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ 27 __RW uint32_t SR; /* 0x200: Status register */ 28 __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ 29 __RW uint32_t GCR; /* 0x208: Global control register */ 30 } GPTMR_Type; 31 32 33 /* Bitfield definition for register of struct array CHANNEL: CR */ 34 /* 35 * CNTUPT (WO) 36 * 37 * 1- update counter to new value as CNTUPTVAL 38 * This bit will be auto cleared after 1 cycle 39 */ 40 #define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) 41 #define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) 42 #define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) 43 #define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) 44 45 /* 46 * OPMODE (RW) 47 * 48 * 0: round mode 49 * 1: one-shot mode, timer will stopped at reload point. 50 * NOTE: reload irq will be always set at one-shot mode at end 51 */ 52 #define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) 53 #define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) 54 #define GPTMR_CHANNEL_CR_OPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) 55 #define GPTMR_CHANNEL_CR_OPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) 56 57 /* 58 * MONITOR_SEL (RW) 59 * 60 * set to monitor input signal high level time(chan_meas_high) 61 * clr to monitor input signal period(chan_meas_prd) 62 */ 63 #define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) 64 #define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) 65 #define GPTMR_CHANNEL_CR_MONITOR_SEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) 66 #define GPTMR_CHANNEL_CR_MONITOR_SEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) 67 68 /* 69 * MONITOR_EN (RW) 70 * 71 * set to monitor input signal period or high level time. 72 * When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts 73 * * only can be used when trig_mode is selected as measure mode(100) 74 * * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. 75 * if no posedge after reload for more than val_1, will also assert irq_capt 76 */ 77 #define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) 78 #define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) 79 #define GPTMR_CHANNEL_CR_MONITOR_EN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) 80 #define GPTMR_CHANNEL_CR_MONITOR_EN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) 81 82 /* 83 * CNTRST (RW) 84 * 85 * 1- reset counter 86 */ 87 #define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) 88 #define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) 89 #define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) 90 #define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) 91 92 /* 93 * SYNCFLW (RW) 94 * 95 * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. 96 * This bit is not valid for channel 0. 97 */ 98 #define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) 99 #define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) 100 #define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) 101 #define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) 102 103 /* 104 * SYNCIFEN (RW) 105 * 106 * 1- SYNCI is valid on its falling edge 107 */ 108 #define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) 109 #define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) 110 #define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) 111 #define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) 112 113 /* 114 * SYNCIREN (RW) 115 * 116 * 1- SYNCI is valid on its rising edge 117 */ 118 #define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) 119 #define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) 120 #define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) 121 #define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) 122 123 /* 124 * CEN (RW) 125 * 126 * 1- counter enable 127 */ 128 #define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) 129 #define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) 130 #define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) 131 #define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) 132 133 /* 134 * CMPINIT (RW) 135 * 136 * Output compare initial poliarity 137 * 1- The channel output initial level is high 138 * 0- The channel output initial level is low 139 * User should set this bit before set CMPEN to 1. 140 */ 141 #define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) 142 #define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) 143 #define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) 144 #define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) 145 146 /* 147 * CMPEN (RW) 148 * 149 * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. 150 */ 151 #define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) 152 #define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) 153 #define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) 154 #define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) 155 156 /* 157 * DMASEL (RW) 158 * 159 * select one of DMA request: 160 * 00- CMP0 flag 161 * 01- CMP1 flag 162 * 10- Input signal toggle captured 163 * 11- RLD flag, counter reload; 164 */ 165 #define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) 166 #define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) 167 #define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) 168 #define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) 169 170 /* 171 * DMAEN (RW) 172 * 173 * 1- enable dma 174 */ 175 #define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) 176 #define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) 177 #define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) 178 #define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) 179 180 /* 181 * SWSYNCIEN (RW) 182 * 183 * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set 184 */ 185 #define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) 186 #define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) 187 #define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) 188 #define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) 189 190 /* 191 * DBGPAUSE (RW) 192 * 193 * 1- counter will pause if chip is in debug mode 194 */ 195 #define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) 196 #define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) 197 #define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) 198 #define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) 199 200 /* 201 * CAPMODE (RW) 202 * 203 * This bitfield define the input capture mode 204 * 100: width measure mode, timer will calculate the input signal period and duty cycle 205 * 011: capture at both rising edge and falling edge 206 * 010: capture at falling edge 207 * 001: capture at rising edge 208 * 000: No capture 209 */ 210 #define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) 211 #define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) 212 #define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) 213 #define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) 214 215 /* Bitfield definition for register of struct array CHANNEL: CMP0 */ 216 /* 217 * CMP (RW) 218 * 219 * compare value 0 220 */ 221 #define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) 222 #define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) 223 #define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) 224 #define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) 225 226 /* Bitfield definition for register of struct array CHANNEL: RLD */ 227 /* 228 * RLD (RW) 229 * 230 * reload value 231 */ 232 #define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) 233 #define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) 234 #define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) 235 #define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) 236 237 /* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ 238 /* 239 * CNTUPTVAL (RW) 240 * 241 * counter will be set to this value when software write cntupt bit in CR 242 */ 243 #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) 244 #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) 245 #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) 246 #define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) 247 248 /* Bitfield definition for register of struct array CHANNEL: CAPPOS */ 249 /* 250 * CAPPOS (RO) 251 * 252 * This register contains the counter value captured at input signal rising edge 253 */ 254 #define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) 255 #define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) 256 #define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) 257 258 /* Bitfield definition for register of struct array CHANNEL: CAPNEG */ 259 /* 260 * CAPNEG (RO) 261 * 262 * This register contains the counter value captured at input signal falling edge 263 */ 264 #define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) 265 #define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) 266 #define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) 267 268 /* Bitfield definition for register of struct array CHANNEL: CAPPRD */ 269 /* 270 * CAPPRD (RO) 271 * 272 * This register contains the input signal period when channel is configured to input capture measure mode. 273 */ 274 #define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) 275 #define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) 276 #define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) 277 278 /* Bitfield definition for register of struct array CHANNEL: CAPDTY */ 279 /* 280 * MEAS_HIGH (RO) 281 * 282 * This register contains the input signal duty cycle when channel is configured to input capture measure mode. 283 */ 284 #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) 285 #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) 286 #define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) 287 288 /* Bitfield definition for register of struct array CHANNEL: CNT */ 289 /* 290 * COUNTER (RO) 291 * 292 * 32 bit counter value 293 */ 294 #define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) 295 #define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) 296 #define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) 297 298 /* Bitfield definition for register: SR */ 299 /* 300 * CH3CMP1F (W1C) 301 * 302 * channel 3 compare value 1 match flag 303 */ 304 #define GPTMR_SR_CH3CMP1F_MASK (0x8000U) 305 #define GPTMR_SR_CH3CMP1F_SHIFT (15U) 306 #define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) 307 #define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) 308 309 /* 310 * CH3CMP0F (W1C) 311 * 312 * channel 3 compare value 1 match flag 313 */ 314 #define GPTMR_SR_CH3CMP0F_MASK (0x4000U) 315 #define GPTMR_SR_CH3CMP0F_SHIFT (14U) 316 #define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) 317 #define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) 318 319 /* 320 * CH3CAPF (W1C) 321 * 322 * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 323 */ 324 #define GPTMR_SR_CH3CAPF_MASK (0x2000U) 325 #define GPTMR_SR_CH3CAPF_SHIFT (13U) 326 #define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) 327 #define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) 328 329 /* 330 * CH3RLDF (W1C) 331 * 332 * channel 3 counter reload flag 333 */ 334 #define GPTMR_SR_CH3RLDF_MASK (0x1000U) 335 #define GPTMR_SR_CH3RLDF_SHIFT (12U) 336 #define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) 337 #define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) 338 339 /* 340 * CH2CMP1F (W1C) 341 * 342 * channel 2 compare value 1 match flag 343 */ 344 #define GPTMR_SR_CH2CMP1F_MASK (0x800U) 345 #define GPTMR_SR_CH2CMP1F_SHIFT (11U) 346 #define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) 347 #define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) 348 349 /* 350 * CH2CMP0F (W1C) 351 * 352 * channel 2 compare value 1 match flag 353 */ 354 #define GPTMR_SR_CH2CMP0F_MASK (0x400U) 355 #define GPTMR_SR_CH2CMP0F_SHIFT (10U) 356 #define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) 357 #define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) 358 359 /* 360 * CH2CAPF (W1C) 361 * 362 * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 363 */ 364 #define GPTMR_SR_CH2CAPF_MASK (0x200U) 365 #define GPTMR_SR_CH2CAPF_SHIFT (9U) 366 #define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) 367 #define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) 368 369 /* 370 * CH2RLDF (W1C) 371 * 372 * channel 2 counter reload flag 373 */ 374 #define GPTMR_SR_CH2RLDF_MASK (0x100U) 375 #define GPTMR_SR_CH2RLDF_SHIFT (8U) 376 #define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) 377 #define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) 378 379 /* 380 * CH1CMP1F (W1C) 381 * 382 * channel 1 compare value 1 match flag 383 */ 384 #define GPTMR_SR_CH1CMP1F_MASK (0x80U) 385 #define GPTMR_SR_CH1CMP1F_SHIFT (7U) 386 #define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) 387 #define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) 388 389 /* 390 * CH1CMP0F (W1C) 391 * 392 * channel 1 compare value 1 match flag 393 */ 394 #define GPTMR_SR_CH1CMP0F_MASK (0x40U) 395 #define GPTMR_SR_CH1CMP0F_SHIFT (6U) 396 #define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) 397 #define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) 398 399 /* 400 * CH1CAPF (W1C) 401 * 402 * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 403 */ 404 #define GPTMR_SR_CH1CAPF_MASK (0x20U) 405 #define GPTMR_SR_CH1CAPF_SHIFT (5U) 406 #define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) 407 #define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) 408 409 /* 410 * CH1RLDF (W1C) 411 * 412 * channel 1 counter reload flag 413 */ 414 #define GPTMR_SR_CH1RLDF_MASK (0x10U) 415 #define GPTMR_SR_CH1RLDF_SHIFT (4U) 416 #define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) 417 #define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) 418 419 /* 420 * CH0CMP1F (W1C) 421 * 422 * channel 1 compare value 1 match flag 423 */ 424 #define GPTMR_SR_CH0CMP1F_MASK (0x8U) 425 #define GPTMR_SR_CH0CMP1F_SHIFT (3U) 426 #define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) 427 #define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) 428 429 /* 430 * CH0CMP0F (W1C) 431 * 432 * channel 1 compare value 1 match flag 433 */ 434 #define GPTMR_SR_CH0CMP0F_MASK (0x4U) 435 #define GPTMR_SR_CH0CMP0F_SHIFT (2U) 436 #define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) 437 #define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) 438 439 /* 440 * CH0CAPF (W1C) 441 * 442 * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. 443 */ 444 #define GPTMR_SR_CH0CAPF_MASK (0x2U) 445 #define GPTMR_SR_CH0CAPF_SHIFT (1U) 446 #define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) 447 #define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) 448 449 /* 450 * CH0RLDF (W1C) 451 * 452 * channel 1 counter reload flag 453 */ 454 #define GPTMR_SR_CH0RLDF_MASK (0x1U) 455 #define GPTMR_SR_CH0RLDF_SHIFT (0U) 456 #define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) 457 #define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) 458 459 /* Bitfield definition for register: IRQEN */ 460 /* 461 * CH3CMP1EN (RW) 462 * 463 * 1- generate interrupt request when ch3cmp1f flag is set 464 */ 465 #define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) 466 #define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) 467 #define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) 468 #define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) 469 470 /* 471 * CH3CMP0EN (RW) 472 * 473 * 1- generate interrupt request when ch3cmp0f flag is set 474 */ 475 #define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) 476 #define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) 477 #define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) 478 #define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) 479 480 /* 481 * CH3CAPEN (RW) 482 * 483 * 1- generate interrupt request when ch3capf flag is set 484 */ 485 #define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) 486 #define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) 487 #define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) 488 #define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) 489 490 /* 491 * CH3RLDEN (RW) 492 * 493 * 1- generate interrupt request when ch3rldf flag is set 494 */ 495 #define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) 496 #define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) 497 #define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) 498 #define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) 499 500 /* 501 * CH2CMP1EN (RW) 502 * 503 * 1- generate interrupt request when ch2cmp1f flag is set 504 */ 505 #define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) 506 #define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) 507 #define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) 508 #define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) 509 510 /* 511 * CH2CMP0EN (RW) 512 * 513 * 1- generate interrupt request when ch2cmp0f flag is set 514 */ 515 #define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) 516 #define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) 517 #define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) 518 #define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) 519 520 /* 521 * CH2CAPEN (RW) 522 * 523 * 1- generate interrupt request when ch2capf flag is set 524 */ 525 #define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) 526 #define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) 527 #define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) 528 #define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) 529 530 /* 531 * CH2RLDEN (RW) 532 * 533 * 1- generate interrupt request when ch2rldf flag is set 534 */ 535 #define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) 536 #define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) 537 #define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) 538 #define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) 539 540 /* 541 * CH1CMP1EN (RW) 542 * 543 * 1- generate interrupt request when ch1cmp1f flag is set 544 */ 545 #define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) 546 #define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) 547 #define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) 548 #define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) 549 550 /* 551 * CH1CMP0EN (RW) 552 * 553 * 1- generate interrupt request when ch1cmp0f flag is set 554 */ 555 #define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) 556 #define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) 557 #define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) 558 #define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) 559 560 /* 561 * CH1CAPEN (RW) 562 * 563 * 1- generate interrupt request when ch1capf flag is set 564 */ 565 #define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) 566 #define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) 567 #define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) 568 #define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) 569 570 /* 571 * CH1RLDEN (RW) 572 * 573 * 1- generate interrupt request when ch1rldf flag is set 574 */ 575 #define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) 576 #define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) 577 #define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) 578 #define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) 579 580 /* 581 * CH0CMP1EN (RW) 582 * 583 * 1- generate interrupt request when ch0cmp1f flag is set 584 */ 585 #define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) 586 #define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) 587 #define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) 588 #define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) 589 590 /* 591 * CH0CMP0EN (RW) 592 * 593 * 1- generate interrupt request when ch0cmp0f flag is set 594 */ 595 #define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) 596 #define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) 597 #define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) 598 #define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) 599 600 /* 601 * CH0CAPEN (RW) 602 * 603 * 1- generate interrupt request when ch0capf flag is set 604 */ 605 #define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) 606 #define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) 607 #define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) 608 #define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) 609 610 /* 611 * CH0RLDEN (RW) 612 * 613 * 1- generate interrupt request when ch0rldf flag is set 614 */ 615 #define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) 616 #define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) 617 #define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) 618 #define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) 619 620 /* Bitfield definition for register: GCR */ 621 /* 622 * SWSYNCT (RW) 623 * 624 * set this bitfield to trigger software coutner sync event 625 */ 626 #define GPTMR_GCR_SWSYNCT_MASK (0xFU) 627 #define GPTMR_GCR_SWSYNCT_SHIFT (0U) 628 #define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) 629 #define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) 630 631 632 633 /* CMP register group index macro definition */ 634 #define GPTMR_CHANNEL_CMP_CMP0 (0UL) 635 #define GPTMR_CHANNEL_CMP_CMP1 (1UL) 636 637 /* CHANNEL register group index macro definition */ 638 #define GPTMR_CHANNEL_CH0 (0UL) 639 #define GPTMR_CHANNEL_CH1 (1UL) 640 #define GPTMR_CHANNEL_CH2 (2UL) 641 #define GPTMR_CHANNEL_CH3 (3UL) 642 643 644 #endif /* HPM_GPTMR_H */ 645