1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _DUET_FLASH_ALG_H_ 17 #define _DUET_FLASH_ALG_H_ 18 19 typedef volatile unsigned char vu8; 20 typedef volatile unsigned long vu32; 21 typedef volatile unsigned short vu16; 22 23 #define M8(adr) (*((vu8 *) (adr))) 24 #define M16(adr) (*((vu16 *) (adr))) 25 #define M32(adr) (*((vu32 *) (adr))) 26 27 // Peripheral Memory Map 28 #define FLASH_BASE 0x40003000 29 30 #define PP 0x02 31 #define QPP 0x32 32 #define PP4 0x38 33 34 #define WREN 0x06 35 #define SE 0x20 36 #define BE 0xD8 37 #define BE32K 0x52 38 #define CE 0xC7 39 #define EQPI 0x35 40 #define RSTEN 0x66 41 #define RST 0x99 42 43 #define READ 0x03 44 #define F_RD 0x0B 45 #define DREAD 0x3B 46 #define QREAD 0x6B 47 #define READ2 0xBB 48 #define READ4 0xEB 49 50 #define RDID 0x9F 51 #define WRSR 0x01 52 #define RDSR 0x05 53 #define RDSR1 0x35 54 55 #define OSC (100) 56 #define OSC_D ((OSC*144)/8) 57 58 typedef struct { 59 vu32 QSPI_CR ; // offset 0x00 60 vu32 QSPI_DCR ; // offset 0x04 61 vu32 QSPI_SR ; // offset 0x08 62 vu32 QSPI_FCR ; // offset 0x0C 63 vu32 QSPI_DLR ; // offset 0x10 64 vu32 QSPI_CCR ; // offset 0x14 65 vu32 QSPI_AR ; // offset 0x18 66 vu32 QSPI_ABR ; // offset 0x1C 67 vu32 QSPI_DR ; // offset 0x20 68 vu32 QSPI_PSMKR ; // offset 0x24 69 vu32 QSPI_PSMAR ; // offset 0x28 70 vu32 QSPI_PIR ; // offset 0x2C 71 vu32 QSPI_TOR ; // offset 0x30 72 vu32 RESERVERD[19]; 73 vu32 QSPI_HIT0R ; // offset 0x80 74 vu32 QSPI_HIT1R ; // offset 0x84 75 vu32 QSPI_MIR ; // offset 0x88 76 vu32 QSPI_CFGR ; // offset 0x8C 77 vu32 SBUS_START ; // offset 0x90 78 } FLASH_TypeDef; 79 80 #define NVM_CTRL_WR_LOCK *((volatile unsigned int *)(0x40000A04)) 81 #define FLASH_ACCESS_CONTROL0 *((volatile unsigned int *)(0x40000A08)) 82 #define FLASH_ACCESS_CONTROL1 *((volatile unsigned int *)(0x40000A0C)) 83 #define FLASH_REMAPPING_REG *((volatile unsigned int *)(0x4000006C)) 84 #define FLASH_REMAPPING_BIT 0x1 85 86 #define FLASH_CACHE_CTRL *((volatile unsigned int *)(0x4001C000)) 87 88 #define CACHE_BYPASS (1 << 1) 89 #define CACHE_FLUSH (1) 90 91 #define FLASH ((FLASH_TypeDef*) FLASH_BASE) 92 #define VERS 1 // Interface Version 1.01 93 94 #define UNKNOWN 0 // Unknown 95 #define ONCHIP 1 // On-chip Flash Memory 96 #define EXT8BIT 2 // External Flash Device on 8-bit Bus 97 #define EXT16BIT 3 // External Flash Device on 16-bit Bus 98 #define EXT32BIT 4 // External Flash Device on 32-bit Bus 99 #define EXTSPI 5 // External Flash Device on SPI 100 101 #define SPI_FLASH_ADDR_START 0x10000000 102 #define SPI_FLASH_ADDR_END 0x17FFFFFF 103 #define SPI_FLASH_SEC_SIZE 0x1000 104 #define SPI_FLASH_BLOCK_32K_SIZE 0x8000 105 #define SPI_FLASH_BLOCK_64K_SIZE 0x10000 106 #define SPI_FLASH_PAGE_SIZE 0x100 107 #define SECTOR_NUM 512 // Max Number of Sector Items 108 #define PAGE_MAX 65536 // Max Page Size for Programming 109 #define CLK_FLASH_SEL 0x40000808 110 111 #define FLASH_52_CLK 0x0 // flash clk src 52MHz 112 #define FLASH_120_CLK 0x1 // flash clk src 120MHz 113 #define FLASH_240_CLK 0x2 // flash clk src 240MHz 114 115 #define FLASH_QSPI_DIV4 0x09004801 116 #define FLASH_QSPI_DIV3 0x89004801 117 #define FLASH_QSPI_DIV2 0x08004801 118 #define FLASH_QSPI_L1 0x2D1C250B 119 #define FLASH_QSPI_L2 0x4E1C253B 120 #define FLASH_QSPI_L4 0x6F0CEDEB 121 #define FLASH_QSPI_DCR_2M 0x00140000 122 #define FLASH_QSPI_DCR_4M 0x00150000 123 124 #define CHIP_ERASE_CMD 0x0000160 125 #define SECTOR_ERASE_CMD 0x0002520 126 #define BLOCK32_ERASE_CMD 0x0002552 127 #define BLOCK64_ERASE_CMD 0x00025D8 128 129 struct FlashSectors { 130 unsigned long szSector; // Sector Size in Bytes 131 unsigned long AddrSector; // Address of Sector 132 }; 133 134 #define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF 135 136 struct FlashDevice { 137 unsigned short Vers; // Version Number and Architecture 138 char DevName[128]; // Device Name and Description 139 unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... 140 unsigned long DevAdr; // Default Device Start Address 141 unsigned long szDev; // Total Size of Device 142 unsigned long szPage; // Programming Page Size 143 unsigned long szSector; 144 unsigned long Res; // Reserved for future Extension 145 unsigned char valEmpty; // Content of Erased Memory 146 147 unsigned long toProg; // Time Out of Program Page Function 148 unsigned long toErase; // Time Out of Erase Sector Function 149 150 struct FlashSectors sectors[SECTOR_NUM]; 151 }; 152 153 #define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify! 154 155 #define FLASH_DRIVER_SEG __attribute__((section("seg_flash_driver"))) 156 157 void duet_flash_alg_read_buf_clr(void); 158 // void duet_flash_alg_cache_bypass(void); 159 void duet_flash_alg_cache_enable(void); 160 // void duet_flash_alg_cache_flush(void); 161 int duet_flash_alg_init (void); 162 int duet_flash_alg_erase(unsigned int cmd, unsigned long adr); 163 int duet_flash_alg_programpage (unsigned long adr, // Program Page Function 164 unsigned long sz, 165 unsigned char *buf); 166 #ifdef _SPI_FLASH_240MHz_ 167 void duet_flash_alg_set_clk_240(unsigned char en_240m); 168 #elif defined _SPI_FLASH_120MHz_ 169 void duet_flash_alg_set_clk_120(unsigned char en_120m); 170 #endif 171 #endif // _LEGA_FLASH_ALG_H_