1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_AONCMU_BEST2003_H__ 16 #define __REG_AONCMU_BEST2003_H__ 17 18 #include "plat_types.h" 19 20 struct AONCMU_T { 21 __I uint32_t CHIP_ID; // 0x00 22 __IO uint32_t TOP_CLK_ENABLE; // 0x04 23 __IO uint32_t TOP_CLK_DISABLE; // 0x08 24 __IO uint32_t RESET_PULSE; // 0x0C 25 __IO uint32_t RESET_SET; // 0x10 26 __IO uint32_t RESET_CLR; // 0x14 27 __IO uint32_t CLK_SELECT; // 0x18 28 __IO uint32_t CLK_OUT; // 0x1C 29 __IO uint32_t WRITE_UNLOCK; // 0x20 30 __IO uint32_t MEMSC[4]; // 0x24 31 __I uint32_t MEMSC_STATUS; // 0x34 32 __IO uint32_t BOOTMODE; // 0x38 33 __IO uint32_t FLS_PSR_CLK; // 0x3C 34 __IO uint32_t MOD_CLK_ENABLE; // 0x40 35 __IO uint32_t MOD_CLK_DISABLE; // 0x44 36 __IO uint32_t MOD_CLK_MODE; // 0x48 37 __IO uint32_t CODEC_DIV; // 0x4C 38 __IO uint32_t TIMER_CLK; // 0x50 39 __IO uint32_t PWM01_CLK; // 0x54 40 __IO uint32_t PWM23_CLK; // 0x58 41 __IO uint32_t LNA_CFG; // 0x5C 42 __IO uint32_t RESERVED_060; // 0x60 43 __IO uint32_t PCM_I2S_CLK; // 0x64 44 __IO uint32_t SPDIF_CLK; // 0x68 45 __IO uint32_t SLEEP_TIMER_OSC; // 0x6C 46 __IO uint32_t SLEEP_TIMER_32K; // 0x70 47 __IO uint32_t STORE_GPIO_MASK; // 0x74 48 __IO uint32_t CODEC_IIR; // 0x78 49 __IO uint32_t SE_WLOCK; // 0x7C 50 __IO uint32_t SE_RLOCK; // 0x80 51 __IO uint32_t PD_STAB_TIMER; // 0x84 52 __IO uint32_t TIMER_WDT; // 0x88 53 __IO uint32_t PLL_ENABLE; // 0x8C 54 __IO uint32_t PLL_DISABLE; // 0x90 55 __IO uint32_t DSP_PLL_SELECT; // 0x94 56 __IO uint32_t DDR_CLK; // 0x98 57 __IO uint32_t MIPI_CLK; // 0x9C 58 __IO uint32_t SOFT_RSTN_PULSE; // 0xA0 59 __IO uint32_t SOFT_RSTN_SET; // 0xA4 60 __IO uint32_t SOFT_RSTN_CLR; // 0xA8 61 __IO uint32_t FLASH_IOCFG; // 0xAC 62 __IO uint32_t PWM45_CLK; // 0xB0 63 __IO uint32_t PWM67_CLK; // 0xB4 64 __IO uint32_t RESERVED_0B8[0xC];// 0xB8 65 __IO uint32_t RESERVED_0E8; // 0xE8 66 __IO uint32_t RESERVED_0EC; // 0xEC 67 __IO uint32_t WAKEUP_PC; // 0xF0 68 __IO uint32_t DEBUG_RES[2]; // 0xF4 69 __IO uint32_t CHIP_FEATURE; // 0xFC 70 }; 71 72 // reg_00 73 #define AON_CMU_CHIP_ID(n) (((n) & 0xFFFF) << 0) 74 #define AON_CMU_CHIP_ID_MASK (0xFFFF << 0) 75 #define AON_CMU_CHIP_ID_SHIFT (0) 76 #define AON_CMU_REVISION_ID(n) (((n) & 0xFFFF) << 16) 77 #define AON_CMU_REVISION_ID_MASK (0xFFFF << 16) 78 #define AON_CMU_REVISION_ID_SHIFT (16) 79 80 // reg_04 81 #define AON_CMU_EN_CLK_TOP_OSC_ENABLE (1 << 0) 82 #define AON_CMU_EN_CLK_TOP_OSCX2_ENABLE (1 << 1) 83 #define AON_CMU_EN_CLK_TOP_OSCX4_ENABLE (1 << 2) 84 #define AON_CMU_EN_CLK_TOP_PLLBB_ENABLE (1 << 3) 85 #define AON_CMU_EN_CLK_TOP_PLLA7_ENABLE (1 << 4) 86 #define AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE (1 << 5) 87 #define AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE (1 << 6) 88 #define AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE (1 << 7) 89 #define AON_CMU_EN_CLK_TOP_PLLBB_WF_ENABLE (1 << 8) 90 #define AON_CMU_EN_CLK_TOP_PHY_PS_ENABLE (1 << 9) 91 #define AON_CMU_EN_CLK_TOP_JTAG_ENABLE (1 << 10) 92 #define AON_CMU_EN_CLK_USB_PLL_ENABLE (1 << 11) 93 #define AON_CMU_EN_CLK_BT_ENABLE (1 << 12) 94 #define AON_CMU_EN_CLK_WF_ENABLE (1 << 13) 95 #define AON_CMU_EN_CLK_CODEC_ENABLE (1 << 14) 96 #define AON_CMU_EN_CLK_CODECIIR_ENABLE (1 << 15) 97 #define AON_CMU_EN_CLK_CODECRS0_ENABLE (1 << 16) 98 #define AON_CMU_EN_CLK_CODECRS1_ENABLE (1 << 17) 99 #define AON_CMU_EN_CLK_CODECHCLK_ENABLE (1 << 18) 100 #define AON_CMU_EN_CLK_VAD32K_ENABLE (1 << 19) 101 #define AON_CMU_EN_CLK_MCU_32K_ENABLE (1 << 20) 102 #define AON_CMU_EN_CLK_MCU_OSC_ENABLE (1 << 21) 103 #define AON_CMU_EN_CLK_MCU_OSCX2_ENABLE (1 << 22) 104 #define AON_CMU_EN_X2_DIG_ENABLE (1 << 23) 105 #define AON_CMU_EN_X4_DIG_ENABLE (1 << 24) 106 #define AON_CMU_EN_BT_CLK_SYS_ENABLE (1 << 25) 107 #define AON_CMU_EN_CLK_PSRAMX2_ENABLE (1 << 26) 108 109 // reg_08 110 #define AON_CMU_EN_CLK_TOP_OSC_DISABLE (1 << 0) 111 #define AON_CMU_EN_CLK_TOP_OSCX2_DISABLE (1 << 1) 112 #define AON_CMU_EN_CLK_TOP_OSCX4_DISABLE (1 << 2) 113 #define AON_CMU_EN_CLK_TOP_PLLBB_DISABLE (1 << 3) 114 #define AON_CMU_EN_CLK_TOP_PLLA7_DISABLE (1 << 4) 115 #define AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE (1 << 5) 116 #define AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE (1 << 6) 117 #define AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE (1 << 7) 118 #define AON_CMU_EN_CLK_TOP_PLLBB_WF_DISABLE (1 << 8) 119 #define AON_CMU_EN_CLK_TOP_PHY_PS_DISABLE (1 << 9) 120 #define AON_CMU_EN_CLK_TOP_JTAG_DISABLE (1 << 10) 121 #define AON_CMU_EN_CLK_USB_PLL_DISABLE (1 << 11) 122 #define AON_CMU_EN_CLK_BT_DISABLE (1 << 12) 123 #define AON_CMU_EN_CLK_WF_DISABLE (1 << 13) 124 #define AON_CMU_EN_CLK_CODEC_DISABLE (1 << 14) 125 #define AON_CMU_EN_CLK_CODECIIR_DISABLE (1 << 15) 126 #define AON_CMU_EN_CLK_CODECRS0_DISABLE (1 << 16) 127 #define AON_CMU_EN_CLK_CODECRS1_DISABLE (1 << 17) 128 #define AON_CMU_EN_CLK_CODECHCLK_DISABLE (1 << 18) 129 #define AON_CMU_EN_CLK_VAD32K_DISABLE (1 << 19) 130 #define AON_CMU_EN_CLK_MCU_32K_DISABLE (1 << 20) 131 #define AON_CMU_EN_CLK_MCU_OSC_DISABLE (1 << 21) 132 #define AON_CMU_EN_CLK_MCU_OSCX2_DISABLE (1 << 22) 133 #define AON_CMU_EN_X2_DIG_DISABLE (1 << 23) 134 #define AON_CMU_EN_X4_DIG_DISABLE (1 << 24) 135 #define AON_CMU_EN_BT_CLK_SYS_DISABLE (1 << 25) 136 #define AON_CMU_EN_CLK_PSRAMX2_DISABLE (1 << 26) 137 138 #define AON_ARST_NUM 13 139 #define AON_ORST_NUM 18 140 #define AON_ACLK_NUM AON_ARST_NUM 141 #define AON_OCLK_NUM AON_ORST_NUM 142 143 // reg_0c 144 #define AON_CMU_ARESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) 145 #define AON_CMU_ARESETN_PULSE_MASK (0xFFFFFFFF << 0) 146 #define AON_CMU_ARESETN_PULSE_SHIFT (0) 147 #define AON_CMU_ORESETN_PULSE(n) (((n) & 0xFFFFFFFF) << AON_ARST_NUM) 148 #define AON_CMU_ORESETN_PULSE_MASK (0xFFFFFFFF << AON_ARST_NUM) 149 #define AON_CMU_ORESETN_PULSE_SHIFT (AON_ARST_NUM) 150 151 // reg_10 152 #define AON_CMU_ARESETN_SET(n) (((n) & 0xFFFFFFFF) << 0) 153 #define AON_CMU_ARESETN_SET_MASK (0xFFFFFFFF << 0) 154 #define AON_CMU_ARESETN_SET_SHIFT (0) 155 #define AON_CMU_ORESETN_SET(n) (((n) & 0xFFFFFFFF) << AON_ARST_NUM) 156 #define AON_CMU_ORESETN_SET_MASK (0xFFFFFFFF << AON_ARST_NUM) 157 #define AON_CMU_ORESETN_SET_SHIFT (AON_ARST_NUM) 158 159 // reg_14 160 #define AON_CMU_ARESETN_CLR(n) (((n) & 0xFFFFFFFF) << 0) 161 #define AON_CMU_ARESETN_CLR_MASK (0xFFFFFFFF << 0) 162 #define AON_CMU_ARESETN_CLR_SHIFT (0) 163 #define AON_CMU_ORESETN_CLR(n) (((n) & 0xFFFFFFFF) << AON_ARST_NUM) 164 #define AON_CMU_ORESETN_CLR_MASK (0xFFFFFFFF << AON_ARST_NUM) 165 #define AON_CMU_ORESETN_CLR_SHIFT (AON_ARST_NUM) 166 167 // reg_18 168 #define AON_CMU_BYPASS_DIV_BTSYS (1 << 0) 169 #define AON_CMU_CFG_DIV_BTSYS(n) (((n) & 0x3) << 1) 170 #define AON_CMU_CFG_DIV_BTSYS_MASK (0x3 << 1) 171 #define AON_CMU_CFG_DIV_BTSYS_SHIFT (1) 172 #define AON_CMU_SEL_BT_PLL (1 << 3) 173 #define AON_CMU_EN_BT_2M (1 << 4) 174 #define AON_CMU_SEL_USB_PLLUSB (1 << 5) 175 #define AON_CMU_CFG_DIV_USB(n) (((n) & 0x7) << 6) 176 #define AON_CMU_CFG_DIV_USB_MASK (0x7 << 6) 177 #define AON_CMU_CFG_DIV_USB_SHIFT (6) 178 #define AON_CMU_SEL_USB_OSCX2 (1 << 9) 179 #define AON_CMU_CFG_DIV_PER(n) (((n) & 0x3) << 10) 180 #define AON_CMU_CFG_DIV_PER_MASK (0x3 << 10) 181 #define AON_CMU_CFG_DIV_PER_SHIFT (10) 182 #define AON_CMU_BYPASS_DIV_PER (1 << 12) 183 #define AON_CMU_RSTN_DIV_PER (1 << 13) 184 #define AON_CMU_SEL_OSCX2_DIG (1 << 14) 185 #define AON_CMU_SEL_X2_PHASE(n) (((n) & 0x1F) << 15) 186 #define AON_CMU_SEL_X2_PHASE_MASK (0x1F << 15) 187 #define AON_CMU_SEL_X2_PHASE_SHIFT (15) 188 #define AON_CMU_SEL_OSCX4_DIG (1 << 20) 189 #define AON_CMU_SEL_X4_PHASE(n) (((n) & 0x1F) << 21) 190 #define AON_CMU_SEL_X4_PHASE_MASK (0x1F << 21) 191 #define AON_CMU_SEL_X4_PHASE_SHIFT (21) 192 #define AON_CMU_PU_MCU_PLLBB_MASK (1 << 26) 193 #define AON_CMU_PU_MCU_PLLUSB_MASK (1 << 27) 194 #define AON_CMU_PU_MCU_PLLA7_MASK (1 << 28) 195 #define AON_CMU_PU_MCU_PLLDSI_MASK (1 << 29) 196 197 // reg_1c 198 #define AON_CMU_EN_CLK_OUT (1 << 0) 199 #define AON_CMU_SEL_CLK_OUT(n) (((n) & 0x7) << 1) 200 #define AON_CMU_SEL_CLK_OUT_MASK (0x7 << 1) 201 #define AON_CMU_SEL_CLK_OUT_SHIFT (1) 202 #define AON_CMU_CFG_CLK_OUT(n) (((n) & 0x1F) << 4) 203 #define AON_CMU_CFG_CLK_OUT_MASK (0x1F << 4) 204 #define AON_CMU_CFG_CLK_OUT_SHIFT (4) 205 #define AON_CMU_CFG_DIV_DCDC(n) (((n) & 0xF) << 9) 206 #define AON_CMU_CFG_DIV_DCDC_MASK (0xF << 9) 207 #define AON_CMU_CFG_DIV_DCDC_SHIFT (9) 208 #define AON_CMU_BYPASS_DIV_DCDC (1 << 13) 209 #define AON_CMU_SEL_DCDC_OSC (1 << 14) 210 #define AON_CMU_SEL_DCDC_PLL (1 << 15) 211 #define AON_CMU_CLK_DCDC_DRV(n) (((n) & 0x3) << 16) 212 #define AON_CMU_CLK_DCDC_DRV_MASK (0x3 << 16) 213 #define AON_CMU_CLK_DCDC_DRV_SHIFT (16) 214 #define AON_CMU_SEL_DCDC_PHASE0(n) (((n) & 0x1F) << 18) 215 #define AON_CMU_SEL_DCDC_PHASE0_MASK (0x1F << 18) 216 #define AON_CMU_SEL_DCDC_PHASE0_SHIFT (18) 217 #define AON_CMU_SEL_DCDC_PHASE1(n) (((n) & 0x1F) << 23) 218 #define AON_CMU_SEL_DCDC_PHASE1_MASK (0x1F << 23) 219 #define AON_CMU_SEL_DCDC_PHASE1_SHIFT (23) 220 #define AON_CMU_EN_CLK_DCDC0 (1 << 28) 221 #define AON_CMU_EN_CLK_DCDC1 (1 << 29) 222 #define AON_CMU_EN_CLK_DCDC2 (1 << 30) 223 224 // reg_20 225 #define AON_CMU_WRITE_UNLOCK_H (1 << 0) 226 #define AON_CMU_WRITE_UNLOCK_STATUS (1 << 1) 227 228 // reg_24 229 #define AON_CMU_MEMSC0 (1 << 0) 230 231 // reg_28 232 #define AON_CMU_MEMSC1 (1 << 0) 233 234 // reg_2c 235 #define AON_CMU_MEMSC2 (1 << 0) 236 237 // reg_30 238 #define AON_CMU_MEMSC3 (1 << 0) 239 240 // reg_34 241 #define AON_CMU_MEMSC_STATUS0 (1 << 0) 242 #define AON_CMU_MEMSC_STATUS1 (1 << 1) 243 #define AON_CMU_MEMSC_STATUS2 (1 << 2) 244 #define AON_CMU_MEMSC_STATUS3 (1 << 3) 245 246 // reg_38 247 #define AON_CMU_WATCHDOG_RESET (1 << 0) 248 #define AON_CMU_SOFT_GLOBLE_RESET (1 << 1) 249 #define AON_CMU_RTC_INTR_H (1 << 2) 250 #define AON_CMU_CHG_INTR_H (1 << 3) 251 #define AON_CMU_SOFT_BOOT_MODE(n) (((n) & 0xFFFFFFF) << 4) 252 #define AON_CMU_SOFT_BOOT_MODE_MASK (0xFFFFFFF << 4) 253 #define AON_CMU_SOFT_BOOT_MODE_SHIFT (4) 254 255 // reg_3c 256 #define AON_CMU_SEL_MCU_PLLBB_PS (1 << 0) 257 #define AON_CMU_SEL_MCU_PLLUSB (1 << 1) 258 #define AON_CMU_SEL_MCU_PLLA7USB (1 << 2) 259 #define AON_CMU_RSTN_DIV_FLS (1 << 3) 260 #define AON_CMU_CFG_DIV_FLS(n) (((n) & 0x7) << 4) 261 #define AON_CMU_CFG_DIV_FLS_MASK (0x7 << 4) 262 #define AON_CMU_CFG_DIV_FLS_SHIFT (4) 263 #define AON_CMU_BYPASS_DIV_FLS (1 << 7) 264 #define AON_CMU_SEL_FLS_OSCX2 (1 << 8) 265 #define AON_CMU_SEL_FLS_OSCX4 (1 << 9) 266 #define AON_CMU_SEL_FLS_PLL (1 << 10) 267 #define AON_CMU_RSTN_DIV_PSR (1 << 11) 268 #define AON_CMU_CFG_DIV_PSR(n) (((n) & 0x3) << 12) 269 #define AON_CMU_CFG_DIV_PSR_MASK (0x3 << 12) 270 #define AON_CMU_CFG_DIV_PSR_SHIFT (12) 271 #define AON_CMU_BYPASS_DIV_PSR (1 << 14) 272 #define AON_CMU_SEL_PSR_OSCX2 (1 << 15) 273 #define AON_CMU_SEL_PSR_OSCX4 (1 << 16) 274 #define AON_CMU_SEL_PSR_PLL (1 << 17) 275 #define AON_CMU_SEL_PSR_INT (1 << 18) 276 #define AON_CMU_SEL_FLS_PLLPS (1 << 19) 277 #define AON_CMU_SEL_MCU_PLLDSI (1 << 20) 278 #define AON_CMU_SEL_PSR_PLLDSI (1 << 21) 279 #define AON_CMU_SEL_DCDC_PHASE2(n) (((n) & 0x1F) << 22) 280 #define AON_CMU_SEL_DCDC_PHASE2_MASK (0x1F << 22) 281 #define AON_CMU_SEL_DCDC_PHASE2_SHIFT (22) 282 283 // reg_40 284 #define AON_CMU_MANUAL_ACLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) 285 #define AON_CMU_MANUAL_ACLK_ENABLE_MASK (0xFFFFFFFF << 0) 286 #define AON_CMU_MANUAL_ACLK_ENABLE_SHIFT (0) 287 #define AON_CMU_MANUAL_OCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << AON_ACLK_NUM) 288 #define AON_CMU_MANUAL_OCLK_ENABLE_MASK (0xFFFFFFFF << AON_ACLK_NUM) 289 #define AON_CMU_MANUAL_OCLK_ENABLE_SHIFT (AON_ACLK_NUM) 290 291 // reg_44 292 #define AON_CMU_MANUAL_ACLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) 293 #define AON_CMU_MANUAL_ACLK_DISABLE_MASK (0xFFFFFFFF << 0) 294 #define AON_CMU_MANUAL_ACLK_DISABLE_SHIFT (0) 295 #define AON_CMU_MANUAL_OCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << AON_ACLK_NUM) 296 #define AON_CMU_MANUAL_OCLK_DISABLE_MASK (0xFFFFFFFF << AON_ACLK_NUM) 297 #define AON_CMU_MANUAL_OCLK_DISABLE_SHIFT (AON_ACLK_NUM) 298 299 // reg_48 300 #define AON_CMU_MODE_ACLK(n) (((n) & 0xFFFFFFFF) << 0) 301 #define AON_CMU_MODE_ACLK_MASK (0xFFFFFFFF << 0) 302 #define AON_CMU_MODE_ACLK_SHIFT (0) 303 #define AON_CMU_MODE_OCLK(n) (((n) & 0xFFFFFFFF) << AON_ACLK_NUM) 304 #define AON_CMU_MODE_OCLK_MASK (0xFFFFFFFF << AON_ACLK_NUM) 305 #define AON_CMU_MODE_OCLK_SHIFT (AON_ACLK_NUM) 306 307 // reg_4c 308 #define AON_CMU_SEL_AON_OSC (1 << 0) 309 #define AON_CMU_SEL_AON_OSCX2 (1 << 1) 310 #define AON_CMU_SEL_AON_SPI_OSCX2 (1 << 2) 311 #define AON_CMU_SEL_CODEC_ANA_2 (1 << 3) 312 #define AON_CMU_SEL_CODEC_OSC_2 (1 << 4) 313 #define AON_CMU_SEL_CODEC_OSC (1 << 5) 314 #define AON_CMU_SEL_CODECHCLK_OSCX2 (1 << 6) 315 #define AON_CMU_SEL_CODECHCLK_PLL (1 << 7) 316 #define AON_CMU_SEL_CODECHCLK_MCU (1 << 8) 317 #define AON_CMU_EN_I2S_MCLK (1 << 9) 318 #define AON_CMU_SEL_I2S_MCLK(n) (((n) & 0xF) << 10) 319 #define AON_CMU_SEL_I2S_MCLK_MASK (0xF << 10) 320 #define AON_CMU_SEL_I2S_MCLK_SHIFT (10) 321 #define AON_CMU_POL_SPI_CS(n) (((n) & 0x7) << 14) 322 #define AON_CMU_POL_SPI_CS_MASK (0x7 << 14) 323 #define AON_CMU_POL_SPI_CS_SHIFT (14) 324 #define AON_CMU_CFG_SPI_ARB(n) (((n) & 0x7) << 17) 325 #define AON_CMU_CFG_SPI_ARB_MASK (0x7 << 17) 326 #define AON_CMU_CFG_SPI_ARB_SHIFT (17) 327 #define AON_CMU_PU_FLASH0_IO (1 << 20) 328 #define AON_CMU_EN_VAD_IIR (1 << 21) 329 #define AON_CMU_EN_VAD_RS (1 << 22) 330 #define AON_CMU_EN_MCU_PLLBB_MASK (1 << 23) 331 #define AON_CMU_EN_MCU_PLLUSB_MASK (1 << 24) 332 #define AON_CMU_EN_MCU_PLLPS_MASK (1 << 25) 333 #define AON_CMU_EN_MCU_PLLA7_MASK (1 << 26) 334 #define AON_CMU_LPU_AUTO_SWITCH26 (1 << 27) 335 #define AON_CMU_POR_SLEEP_MODE (1 << 28) 336 337 // reg_50 338 #define AON_CMU_CFG_DIV_TIMER0(n) (((n) & 0xFFFF) << 0) 339 #define AON_CMU_CFG_DIV_TIMER0_MASK (0xFFFF << 0) 340 #define AON_CMU_CFG_DIV_TIMER0_SHIFT (0) 341 #define AON_CMU_CFG_DIV_TIMER1(n) (((n) & 0xFFFF) << 16) 342 #define AON_CMU_CFG_DIV_TIMER1_MASK (0xFFFF << 16) 343 #define AON_CMU_CFG_DIV_TIMER1_SHIFT (16) 344 345 // reg_54 346 #define AON_CMU_CFG_DIV_PWM0(n) (((n) & 0xFFF) << 0) 347 #define AON_CMU_CFG_DIV_PWM0_MASK (0xFFF << 0) 348 #define AON_CMU_CFG_DIV_PWM0_SHIFT (0) 349 #define AON_CMU_SEL_PWM0_OSC (1 << 12) 350 #define AON_CMU_EN_CLK_PWM0_OSC (1 << 13) 351 #define AON_CMU_CFG_DIV_PWM1(n) (((n) & 0xFFF) << 16) 352 #define AON_CMU_CFG_DIV_PWM1_MASK (0xFFF << 16) 353 #define AON_CMU_CFG_DIV_PWM1_SHIFT (16) 354 #define AON_CMU_SEL_PWM1_OSC (1 << 28) 355 #define AON_CMU_EN_CLK_PWM1_OSC (1 << 29) 356 357 // reg_58 358 #define AON_CMU_CFG_DIV_PWM2(n) (((n) & 0xFFF) << 0) 359 #define AON_CMU_CFG_DIV_PWM2_MASK (0xFFF << 0) 360 #define AON_CMU_CFG_DIV_PWM2_SHIFT (0) 361 #define AON_CMU_SEL_PWM2_OSC (1 << 12) 362 #define AON_CMU_EN_CLK_PWM2_OSC (1 << 13) 363 #define AON_CMU_CFG_DIV_PWM3(n) (((n) & 0xFFF) << 16) 364 #define AON_CMU_CFG_DIV_PWM3_MASK (0xFFF << 16) 365 #define AON_CMU_CFG_DIV_PWM3_SHIFT (16) 366 #define AON_CMU_SEL_PWM3_OSC (1 << 28) 367 #define AON_CMU_EN_CLK_PWM3_OSC (1 << 29) 368 369 // reg_5c 370 #define AON_CMU_EXT_LNA_AT_GAIN_STEP0(n) (((n) & 0x7) << 0) 371 #define AON_CMU_EXT_LNA_AT_GAIN_STEP0_MASK (0x7 << 0) 372 #define AON_CMU_EXT_LNA_AT_GAIN_STEP0_SHIFT (0) 373 #define AON_CMU_EXT_LNA_AT_GAIN_STEP1(n) (((n) & 0x7) << 3) 374 #define AON_CMU_EXT_LNA_AT_GAIN_STEP1_MASK (0x7 << 3) 375 #define AON_CMU_EXT_LNA_AT_GAIN_STEP1_SHIFT (3) 376 #define AON_CMU_EXT_LNA_AT_GAIN_STEP2(n) (((n) & 0x7) << 6) 377 #define AON_CMU_EXT_LNA_AT_GAIN_STEP2_MASK (0x7 << 6) 378 #define AON_CMU_EXT_LNA_AT_GAIN_STEP2_SHIFT (6) 379 #define AON_CMU_EXT_LNA_AT_GAIN_STEP3(n) (((n) & 0x7) << 9) 380 #define AON_CMU_EXT_LNA_AT_GAIN_STEP3_MASK (0x7 << 9) 381 #define AON_CMU_EXT_LNA_AT_GAIN_STEP3_SHIFT (9) 382 #define AON_CMU_EXT_LNA_ENABLE (1 << 12) 383 #define AON_CMU_EXT_LNA_ENABLE_DR (1 << 13) 384 #define AON_CMU_EXT_LNA_EN_BYPASS_RXON (1 << 14) 385 #define AON_CMU_FEM_SWTCH_WF_MUX_CFG(n) (((n) & 0x3) << 15) 386 #define AON_CMU_FEM_SWTCH_WF_MUX_CFG_MASK (0x3 << 15) 387 #define AON_CMU_FEM_SWTCH_WF_MUX_CFG_SHIFT (15) 388 389 // reg_64 390 #define AON_CMU_CFG_DIV_PCM(n) (((n) & 0x1FFF) << 0) 391 #define AON_CMU_CFG_DIV_PCM_MASK (0x1FFF << 0) 392 #define AON_CMU_CFG_DIV_PCM_SHIFT (0) 393 #define AON_CMU_EN_CLK_PLL_PCM (1 << 13) 394 #define AON_CMU_CFG_DIV_I2S0(n) (((n) & 0x1FFF) << 16) 395 #define AON_CMU_CFG_DIV_I2S0_MASK (0x1FFF << 16) 396 #define AON_CMU_CFG_DIV_I2S0_SHIFT (16) 397 #define AON_CMU_EN_CLK_PLL_I2S0 (1 << 29) 398 #define AON_CMU_SEL_AUD_PLLUSB (1 << 30) 399 #define AON_CMU_SEL_AUD_X4 (1 << 31) 400 401 // reg_68 402 #define AON_CMU_CFG_DIV_SPDIF0(n) (((n) & 0x1FFF) << 0) 403 #define AON_CMU_CFG_DIV_SPDIF0_MASK (0x1FFF << 0) 404 #define AON_CMU_CFG_DIV_SPDIF0_SHIFT (0) 405 #define AON_CMU_EN_CLK_PLL_SPDIF0 (1 << 13) 406 #define AON_CMU_CFG_DIV_I2S1(n) (((n) & 0x1FFF) << 16) 407 #define AON_CMU_CFG_DIV_I2S1_MASK (0x1FFF << 16) 408 #define AON_CMU_CFG_DIV_I2S1_SHIFT (16) 409 #define AON_CMU_EN_CLK_PLL_I2S1 (1 << 29) 410 411 // reg_6c 412 #define AON_CMU_SLEEP_TIMER_OSC(n) (((n) & 0x7FF) << 0) 413 #define AON_CMU_SLEEP_TIMER_OSC_MASK (0x7FF << 0) 414 #define AON_CMU_SLEEP_TIMER_OSC_SHIFT (0) 415 #define AON_CMU_STORE_GPIO_EN (1 << 30) 416 #define AON_CMU_STORE_TIMER (1 << 31) 417 418 // reg_70 419 #define AON_CMU_SLEEP_TIMER_32K(n) (((n) & 0xFFFFFF) << 0) 420 #define AON_CMU_SLEEP_TIMER_32K_MASK (0xFFFFFF << 0) 421 #define AON_CMU_SLEEP_TIMER_32K_SHIFT (0) 422 423 // reg_74 424 #define AON_CMU_STORE_GPIO_MASK(n) (((n) & 0xFFFFFFFF) << 0) 425 #define AON_CMU_STORE_GPIO_MASK_MASK (0xFFFFFFFF << 0) 426 #define AON_CMU_STORE_GPIO_MASK_SHIFT (0) 427 428 // reg_78 429 #define AON_CMU_CFG_DIV_CODECIIR(n) (((n) & 0xF) << 0) 430 #define AON_CMU_CFG_DIV_CODECIIR_MASK (0xF << 0) 431 #define AON_CMU_CFG_DIV_CODECIIR_SHIFT (0) 432 #define AON_CMU_SEL_CODECIIR_OSC (1 << 4) 433 #define AON_CMU_SEL_CODECIIR_OSCX2 (1 << 5) 434 #define AON_CMU_BYPASS_DIV_CODECIIR (1 << 6) 435 #define AON_CMU_CFG_DIV_CODECRS0(n) (((n) & 0xF) << 8) 436 #define AON_CMU_CFG_DIV_CODECRS0_MASK (0xF << 8) 437 #define AON_CMU_CFG_DIV_CODECRS0_SHIFT (8) 438 #define AON_CMU_SEL_CODECRS0_OSC (1 << 12) 439 #define AON_CMU_SEL_CODECRS0_OSCX2 (1 << 13) 440 #define AON_CMU_BYPASS_DIV_CODECRS0 (1 << 14) 441 #define AON_CMU_CFG_DIV_CODECRS1(n) (((n) & 0xF) << 16) 442 #define AON_CMU_CFG_DIV_CODECRS1_MASK (0xF << 16) 443 #define AON_CMU_CFG_DIV_CODECRS1_SHIFT (16) 444 #define AON_CMU_SEL_CODECRS1_OSC (1 << 20) 445 #define AON_CMU_SEL_CODECRS1_OSCX2 (1 << 21) 446 #define AON_CMU_BYPASS_DIV_CODECRS1 (1 << 22) 447 448 // reg_7c 449 #define AON_CMU_OTP_WR_LOCK(n) (((n) & 0xFFFF) << 0) 450 #define AON_CMU_OTP_WR_LOCK_MASK (0xFFFF << 0) 451 #define AON_CMU_OTP_WR_LOCK_SHIFT (0) 452 #define AON_CMU_OTP_WR_UNLOCK (1 << 31) 453 454 // reg_80 455 #define AON_CMU_OTP_RD_LOCK(n) (((n) & 0xFFFF) << 0) 456 #define AON_CMU_OTP_RD_LOCK_MASK (0xFFFF << 0) 457 #define AON_CMU_OTP_RD_LOCK_SHIFT (0) 458 #define AON_CMU_OTP_RD_UNLOCK (1 << 31) 459 460 // reg_84 461 #define AON_CMU_CFG_PD_STAB_TIMER(n) (((n) & 0xF) << 0) 462 #define AON_CMU_CFG_PD_STAB_TIMER_MASK (0xF << 0) 463 #define AON_CMU_CFG_PD_STAB_TIMER_SHIFT (0) 464 465 // reg_88 466 #define AON_CMU_SEL_32K_TIMER (1 << 0) 467 #define AON_CMU_SEL_32K_WDT (1 << 1) 468 #define AON_CMU_SEL_TIMER_FAST (1 << 2) 469 #define AON_CMU_EN_MCU_WDG_RESET (1 << 3) 470 #define AON_CMU_SEL_32K_WF (1 << 4) 471 #define AON_CMU_SEL_OSC_WF (1 << 5) 472 #define AON_CMU_SEL_BBPLL_WF_320M (1 << 6) 473 474 // reg_8c 475 #define AON_CMU_PU_PLLBB_ENABLE (1 << 0) 476 #define AON_CMU_PU_PLLUSB_ENABLE (1 << 1) //unused 477 #define AON_CMU_PU_PLLDDR_ENABLE (1 << 2) 478 #define AON_CMU_PU_PLLA7_ENABLE (1 << 3) 479 #define AON_CMU_PU_PLLBB_DIV_WF_ENABLE (1 << 4) 480 #define AON_CMU_PU_PLLBB_DIV_PS_ENABLE (1 << 5) 481 #define AON_CMU_PU_PLLBB_DIV_MCU_ENABLE (1 << 6) 482 #define AON_CMU_PU_OSC_ENABLE (1 << 7) 483 #define AON_CMU_PU_OSCX2_ENABLE (1 << 8) 484 #define AON_CMU_PU_OSCX4_ENABLE (1 << 9) 485 #define AON_CMU_PU_PLLDSI_ENABLE (1 << 10) 486 #define AON_CMU_PU_PLLCSI_ENABLE (1 << 11) //unused 487 #define AON_CMU_PU_PLLDSI_DIV_PS_ENABLE (1 << 12) 488 #define AON_CMU_PU_PLLDSI_DIV_MCU_ENABLE (1 << 13) 489 490 // reg_90 491 #define AON_CMU_PU_PLLBB_DISABLE (1 << 0) 492 #define AON_CMU_PU_PLLUSB_DISABLE (1 << 1) 493 #define AON_CMU_PU_PLLDDR_DISABLE (1 << 2) 494 #define AON_CMU_PU_PLLA7_DISABLE (1 << 3) 495 #define AON_CMU_PU_PLLBB_DIV_WF_DISABLE (1 << 4) 496 #define AON_CMU_PU_PLLBB_DIV_PS_DISABLE (1 << 5) 497 #define AON_CMU_PU_PLLBB_DIV_MCU_DISABLE (1 << 6) 498 #define AON_CMU_PU_OSC_DISABLE (1 << 7) 499 #define AON_CMU_PU_OSCX2_DISABLE (1 << 8) 500 #define AON_CMU_PU_OSCX4_DISABLE (1 << 9) 501 #define AON_CMU_PU_PLLDSI_DISABLE (1 << 10) 502 #define AON_CMU_PU_PLLCSI_DISABLE (1 << 11) 503 #define AON_CMU_PU_PLLDSI_DIV_PS_DISABLE (1 << 12) 504 #define AON_CMU_PU_PLLDSI_DIV_MCU_DISABLE (1 << 13) 505 506 // reg_94 507 #define AON_CMU_SEL_A7_PLLUSB (1 << 0) 508 #define AON_CMU_SEL_A7_PLLBB (1 << 1) 509 #define AON_CMU_EN_A7_PLLBB_MASK (1 << 2) 510 #define AON_CMU_EN_A7_PLLUSB_MASK (1 << 3) 511 #define AON_CMU_EN_A7_PLLA7_MASK (1 << 4) 512 #define AON_CMU_PU_A7_PLLBB_MASK (1 << 5) 513 #define AON_CMU_PU_A7_PLLUSB_MASK (1 << 6) 514 #define AON_CMU_PU_A7_PLLA7_MASK (1 << 7) 515 516 // reg_98 517 #define AON_CMU_RSTN_DIV_DDR (1 << 0) 518 #define AON_CMU_CFG_DIV_DDR(n) (((n) & 0x3) << 1) 519 #define AON_CMU_CFG_DIV_DDR_MASK (0x3 << 1) 520 #define AON_CMU_CFG_DIV_DDR_SHIFT (1) 521 #define AON_CMU_BYPASS_DIV_DDR (1 << 3) 522 #define AON_CMU_SEL_DDR_OSCX2 (1 << 4) 523 #define AON_CMU_SEL_DDR_OSCX4 (1 << 5) 524 #define AON_CMU_SEL_DDR_PLL (1 << 6) 525 #define AON_CMU_CFG_DIV_PSRAMX2(n) (((n) & 0x1F) << 7) 526 #define AON_CMU_CFG_DIV_PSRAMX2_MASK (0x1F << 7) 527 #define AON_CMU_CFG_DIV_PSRAMX2_SHIFT (7) 528 529 // reg_9c 530 #define AON_CMU_EN_CLK_PIX_DSI (1 << 0) 531 #define AON_CMU_EN_CLK_PIX_CSI (1 << 1) 532 #define AON_CMU_POL_CLK_DSI_IN (1 << 2) 533 #define AON_CMU_POL_CLK_CSI_IN (1 << 3) 534 #define AON_CMU_CFG_DIV_PIX_DSI(n) (((n) & 0x1F) << 4) 535 #define AON_CMU_CFG_DIV_PIX_DSI_MASK (0x1F << 4) 536 #define AON_CMU_CFG_DIV_PIX_DSI_SHIFT (4) 537 #define AON_CMU_CFG_DIV_PIX_CSI(n) (((n) & 0x1F) << 9) 538 #define AON_CMU_CFG_DIV_PIX_CSI_MASK (0x1F << 9) 539 #define AON_CMU_CFG_DIV_PIX_CSI_SHIFT (9) 540 541 // reg_a0 542 #define AON_CMU_SOFT_RSTN_A7_PULSE (1 << 0) 543 #define AON_CMU_SOFT_RSTN_A7CPU_PULSE (1 << 1) 544 #define AON_CMU_SOFT_RSTN_MCU_PULSE (1 << 2) 545 #define AON_CMU_SOFT_RSTN_CODEC_PULSE (1 << 3) 546 #define AON_CMU_SOFT_RSTN_WF_PULSE (1 << 4) 547 #define AON_CMU_SOFT_RSTN_BT_PULSE (1 << 5) 548 #define AON_CMU_SOFT_RSTN_MCUCPU_PULSE (1 << 6) 549 #define AON_CMU_SOFT_RSTN_WFCPU_PULSE (1 << 7) 550 #define AON_CMU_SOFT_RSTN_BTCPU_PULSE (1 << 8) 551 #define AON_CMU_GLOBAL_RESETN_PULSE (1 << 9) 552 553 // reg_a4 554 #define AON_CMU_SOFT_RSTN_A7_SET (1 << 0) 555 #define AON_CMU_SOFT_RSTN_A7CPU_SET (1 << 1) 556 #define AON_CMU_SOFT_RSTN_MCU_SET (1 << 2) 557 #define AON_CMU_SOFT_RSTN_CODEC_SET (1 << 3) 558 #define AON_CMU_SOFT_RSTN_WF_SET (1 << 4) 559 #define AON_CMU_SOFT_RSTN_BT_SET (1 << 5) 560 #define AON_CMU_SOFT_RSTN_MCUCPU_SET (1 << 6) 561 #define AON_CMU_SOFT_RSTN_WFCPU_SET (1 << 7) 562 #define AON_CMU_SOFT_RSTN_BTCPU_SET (1 << 8) 563 #define AON_CMU_GLOBAL_RESETN_SET (1 << 9) 564 565 // reg_a8 566 #define AON_CMU_SOFT_RSTN_A7_CLR (1 << 0) 567 #define AON_CMU_SOFT_RSTN_A7CPU_CLR (1 << 1) 568 #define AON_CMU_SOFT_RSTN_MCU_CLR (1 << 2) 569 #define AON_CMU_SOFT_RSTN_CODEC_CLR (1 << 3) 570 #define AON_CMU_SOFT_RSTN_WF_CLR (1 << 4) 571 #define AON_CMU_SOFT_RSTN_BT_CLR (1 << 5) 572 #define AON_CMU_SOFT_RSTN_MCUCPU_CLR (1 << 6) 573 #define AON_CMU_SOFT_RSTN_WFCPU_CLR (1 << 7) 574 #define AON_CMU_SOFT_RSTN_BTCPU_CLR (1 << 8) 575 #define AON_CMU_GLOBAL_RESETN_CLR (1 << 9) 576 577 // reg_ac 578 #define AON_CMU_FLASH0_IODRV(n) (((n) & 0x7) << 0) 579 #define AON_CMU_FLASH0_IODRV_MASK (0x7 << 0) 580 #define AON_CMU_FLASH0_IODRV_SHIFT (0) 581 #define AON_CMU_FLASH0_IORES(n) (((n) & 0xF) << 3) 582 #define AON_CMU_FLASH0_IORES_MASK (0xF << 3) 583 #define AON_CMU_FLASH0_IORES_SHIFT (3) 584 #define AON_CMU_PU_FLASH1_IO (1 << 7) 585 #define AON_CMU_FLASH1_IODRV(n) (((n) & 0x7) << 8) 586 #define AON_CMU_FLASH1_IODRV_MASK (0x7 << 8) 587 #define AON_CMU_FLASH1_IODRV_SHIFT (8) 588 #define AON_CMU_FLASH1_IORES(n) (((n) & 0xF) << 11) 589 #define AON_CMU_FLASH1_IORES_MASK (0xF << 11) 590 #define AON_CMU_FLASH1_IORES_SHIFT (11) 591 592 // reg_b0 593 #define AON_CMU_CFG_DIV_PWM4(n) (((n) & 0xFFF) << 0) 594 #define AON_CMU_CFG_DIV_PWM4_MASK (0xFFF << 0) 595 #define AON_CMU_CFG_DIV_PWM4_SHIFT (0) 596 #define AON_CMU_SEL_PWM4_OSC (1 << 12) 597 #define AON_CMU_EN_CLK_PWM4_OSC (1 << 13) 598 #define AON_CMU_CFG_DIV_PWM5(n) (((n) & 0xFFF) << 16) 599 #define AON_CMU_CFG_DIV_PWM5_MASK (0xFFF << 16) 600 #define AON_CMU_CFG_DIV_PWM5_SHIFT (16) 601 #define AON_CMU_SEL_PWM5_OSC (1 << 28) 602 #define AON_CMU_EN_CLK_PWM5_OSC (1 << 29) 603 604 // reg_b4 605 #define AON_CMU_CFG_DIV_PWM6(n) (((n) & 0xFFF) << 0) 606 #define AON_CMU_CFG_DIV_PWM6_MASK (0xFFF << 0) 607 #define AON_CMU_CFG_DIV_PWM6_SHIFT (0) 608 #define AON_CMU_SEL_PWM6_OSC (1 << 12) 609 #define AON_CMU_EN_CLK_PWM6_OSC (1 << 13) 610 #define AON_CMU_CFG_DIV_PWM7(n) (((n) & 0xFFF) << 16) 611 #define AON_CMU_CFG_DIV_PWM7_MASK (0xFFF << 16) 612 #define AON_CMU_CFG_DIV_PWM7_SHIFT (16) 613 #define AON_CMU_SEL_PWM7_OSC (1 << 28) 614 #define AON_CMU_EN_CLK_PWM7_OSC (1 << 29) 615 616 // reg_e8 617 #define AON_CMU_RESERVED0(n) (((n) & 0xFFFFFFFF) << 0) 618 #define AON_CMU_RESERVED0_MASK (0xFFFFFFFF << 0) 619 #define AON_CMU_RESERVED0_SHIFT (0) 620 621 // reg_ec 622 #define AON_CMU_RESERVED1(n) (((n) & 0xFFFFFFFF) << 0) 623 #define AON_CMU_RESERVED1_MASK (0xFFFFFFFF << 0) 624 #define AON_CMU_RESERVED1_SHIFT (0) 625 626 // reg_f0 627 #define AON_CMU_DEBUG0(n) (((n) & 0xFFFFFFFF) << 0) 628 #define AON_CMU_DEBUG0_MASK (0xFFFFFFFF << 0) 629 #define AON_CMU_DEBUG0_SHIFT (0) 630 631 // reg_f4 632 #define AON_CMU_DEBUG1(n) (((n) & 0xFFFFFFFF) << 0) 633 #define AON_CMU_DEBUG1_MASK (0xFFFFFFFF << 0) 634 #define AON_CMU_DEBUG1_SHIFT (0) 635 636 // reg_f8 637 #define AON_CMU_DEBUG2(n) (((n) & 0xFFFFFFFF) << 0) 638 #define AON_CMU_DEBUG2_MASK (0xFFFFFFFF << 0) 639 #define AON_CMU_DEBUG2_SHIFT (0) 640 641 // reg_fc 642 #define AON_CMU_EFUSE(n) (((n) & 0xFFFF) << 0) 643 #define AON_CMU_EFUSE_MASK (0xFFFF << 0) 644 #define AON_CMU_EFUSE_SHIFT (0) 645 #define AON_CMU_EFUSE_LOCK (1 << 31) 646 647 // APB and AHB Clocks: 648 #define AON_ACLK_CMU (1 << 0) 649 #define AON_ARST_CMU (1 << 0) 650 #define AON_ACLK_GPIO (1 << 1) 651 #define AON_ARST_GPIO (1 << 1) 652 #define AON_ACLK_GPIO_INT (1 << 2) 653 #define AON_ARST_GPIO_INT (1 << 2) 654 #define AON_ACLK_WDT (1 << 3) 655 #define AON_ARST_WDT (1 << 3) 656 #define AON_ACLK_PWM (1 << 4) 657 #define AON_ARST_PWM (1 << 4) 658 #define AON_ACLK_TIMER (1 << 5) 659 #define AON_ARST_TIMER (1 << 5) 660 #define AON_ACLK_IOMUX (1 << 6) 661 #define AON_ARST_IOMUX (1 << 6) 662 #define AON_ACLK_SPIDPD (1 << 7) 663 #define AON_ARST_SPIDPD (1 << 7) 664 #define AON_ACLK_APBC (1 << 8) 665 #define AON_ARST_APBC (1 << 8) 666 #define AON_ACLK_H2H_MCU (1 << 9) 667 #define AON_ARST_H2H_MCU (1 << 9) 668 #define AON_ACLK_PSC (1 << 10) 669 #define AON_ARST_PSC (1 << 10) 670 #define AON_ACLK_PWM1 (1 << 11) 671 #define AON_ARST_PWM1 (1 << 11) 672 #define AON_ACLK_WLAN_SLEEP (1 << 12) 673 #define AON_ARST_WLAN_SLEEP (1 << 12) 674 675 // AON other Clocks: 676 #define AON_OCLK_WDT (1 << 0) 677 #define AON_ORST_WDT (1 << 0) 678 #define AON_OCLK_TIMER (1 << 1) 679 #define AON_ORST_TIMER (1 << 1) 680 #define AON_OCLK_GPIO (1 << 2) 681 #define AON_ORST_GPIO (1 << 2) 682 #define AON_OCLK_PWM0 (1 << 3) 683 #define AON_ORST_PWM0 (1 << 3) 684 #define AON_OCLK_PWM1 (1 << 4) 685 #define AON_ORST_PWM1 (1 << 4) 686 #define AON_OCLK_PWM2 (1 << 5) 687 #define AON_ORST_PWM2 (1 << 5) 688 #define AON_OCLK_PWM3 (1 << 6) 689 #define AON_ORST_PWM3 (1 << 6) 690 #define AON_OCLK_IOMUX (1 << 7) 691 #define AON_ORST_IOMUX (1 << 7) 692 #define AON_OCLK_SLP32K (1 << 8) 693 #define AON_ORST_SLP32K (1 << 8) 694 #define AON_OCLK_SLP26M (1 << 9) 695 #define AON_ORST_SLP26M (1 << 9) 696 #define AON_OCLK_SPIDPD (1 << 10) 697 #define AON_ORST_SPIDPD (1 << 10) 698 #define AON_OCLK_WLAN32K (1 << 11) 699 #define AON_ORST_WLAN32K (1 << 11) 700 #define AON_OCLK_WLAN26M (1 << 12) 701 #define AON_ORST_WLAN26M (1 << 12) 702 #define AON_OCLK_BTAON (1 << 13) 703 #define AON_ORST_BTAON (1 << 13) 704 #define AON_OCLK_PWM4 (1 << 14) 705 #define AON_ORST_PWM4 (1 << 14) 706 #define AON_OCLK_PWM5 (1 << 15) 707 #define AON_ORST_PWM5 (1 << 15) 708 #define AON_OCLK_PWM6 (1 << 16) 709 #define AON_ORST_PWM6 (1 << 16) 710 #define AON_OCLK_PWM7 (1 << 17) 711 #define AON_ORST_PWM7 (1 << 17) 712 713 #endif 714 715