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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Header file for Analogix DP (Display Port) core interface driver.
4  *
5  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6  * Author: Jingoo Han <jg1.han@samsung.com>
7  */
8 
9 #ifndef _ANALOGIX_DP_CORE_H
10 #define _ANALOGIX_DP_CORE_H
11 
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_bridge.h>
14 #include <drm/drm_dp_helper.h>
15 
16 #define DP_TIMEOUT_LOOP_COUNT 100
17 #define MAX_CR_LOOP 5
18 #define MAX_EQ_LOOP 5
19 #define MAX_PLL_LOCK_LOOP 5
20 
21 /* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
22 #define DP_TIMEOUT_TRAINING_US 22000
23 #define DP_TIMEOUT_PSR_LOOP_MS 300
24 
25 /* DP_MAX_LANE_COUNT */
26 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
27 #define DPCD_MAX_LANE_COUNT(x) ((x)&0x1f)
28 
29 /* DP_LANE_COUNT_SET */
30 #define DPCD_LANE_COUNT_SET(x) ((x)&0x1f)
31 
32 /* DP_TRAINING_LANE0_SET */
33 #define DPCD_PRE_EMPHASIS_SET(x) (((x)&0x3) << 3)
34 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
35 #define DPCD_VOLTAGE_SWING_SET(x) (((x)&0x3) << 0)
36 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
37 
38 struct gpio_desc;
39 
40 enum link_lane_count_type { LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4 };
41 
42 enum link_training_state { START, CLOCK_RECOVERY, EQUALIZER_TRAINING, FINISHED, FAILED };
43 
44 enum voltage_swing_level {
45     VOLTAGE_LEVEL_0,
46     VOLTAGE_LEVEL_1,
47     VOLTAGE_LEVEL_2,
48     VOLTAGE_LEVEL_3,
49 };
50 
51 enum pre_emphasis_level {
52     PRE_EMPHASIS_LEVEL_0,
53     PRE_EMPHASIS_LEVEL_1,
54     PRE_EMPHASIS_LEVEL_2,
55     PRE_EMPHASIS_LEVEL_3,
56 };
57 
58 enum pattern_set { PRBS7, D10_2, TRAINING_PTN1, TRAINING_PTN2, TRAINING_PTN3, DP_NONE };
59 
60 enum color_space { COLOR_RGB, COLOR_YCBCR422, COLOR_YCBCR444 };
61 
62 enum color_depth { COLOR_6, COLOR_8, COLOR_10, COLOR_12 };
63 
64 enum color_coefficient { COLOR_YCBCR601, COLOR_YCBCR709 };
65 
66 enum dynamic_range { VESA, CEA };
67 
68 enum pll_status { PLL_UNLOCKED, PLL_LOCKED };
69 
70 enum clock_recovery_m_value_type { CALCULATED_M, REGISTER_M };
71 
72 enum video_timing_recognition_type { VIDEO_TIMING_FROM_CAPTURE, VIDEO_TIMING_FROM_REGISTER };
73 
74 enum analog_power_block { AUX_BLOCK, CH0_BLOCK, CH1_BLOCK, CH2_BLOCK, CH3_BLOCK, ANALOG_TOTAL, POWER_ALL };
75 
76 enum dp_irq_type {
77     DP_IRQ_TYPE_HP_CABLE_IN = BIT(0),
78     DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
79     DP_IRQ_TYPE_HP_CHANGE = BIT(2),
80     DP_IRQ_TYPE_UNKNOWN = BIT(3),
81 };
82 
83 struct video_info {
84     char *name;
85     struct drm_display_mode mode;
86 
87     bool h_sync_polarity;
88     bool v_sync_polarity;
89     bool interlaced;
90 
91     enum color_space color_space;
92     enum dynamic_range dynamic_range;
93     enum color_coefficient ycbcr_coeff;
94     enum color_depth color_depth;
95 
96     int max_link_rate;
97     enum link_lane_count_type max_lane_count;
98 
99     bool video_bist_enable;
100 };
101 
102 struct link_train {
103     int eq_loop;
104     int cr_loop[4];
105 
106     u8 link_rate;
107     u8 lane_count;
108     u8 training_lane[4];
109     bool ssc;
110     bool enhanced_framing;
111 
112     enum link_training_state lt_state;
113 };
114 
115 struct analogix_dp_device {
116     struct drm_encoder *encoder;
117     struct device *dev;
118     struct drm_device *drm_dev;
119     struct drm_connector connector;
120     struct drm_bridge bridge;
121     struct drm_dp_aux aux;
122     struct clk_bulk_data *clks;
123     int nr_clks;
124     unsigned int irq;
125     void __iomem *reg_base;
126 
127     struct video_info video_info;
128     struct link_train link_train;
129     struct phy *phy;
130     bool phy_enabled;
131     int dpms_mode;
132     struct gpio_desc *hpd_gpiod;
133     bool force_hpd;
134     bool fast_train_enable;
135     bool psr_supported;
136 
137     struct mutex panel_lock;
138     bool panel_is_prepared;
139 
140     struct analogix_dp_plat_data *plat_data;
141 };
142 
143 /* analogix_dp_reg.c */
144 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
145 void analogix_dp_stop_video(struct analogix_dp_device *dp);
146 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
147 void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
148 void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
149 void analogix_dp_reset(struct analogix_dp_device *dp);
150 void analogix_dp_swreset(struct analogix_dp_device *dp);
151 void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
152 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
153 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
154 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
155 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
156 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, enum analog_power_block block, bool enable);
157 int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
158 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
159 void analogix_dp_force_hpd(struct analogix_dp_device *dp);
160 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
161 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
162 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
163 void analogix_dp_init_aux(struct analogix_dp_device *dp);
164 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
165 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
166 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
167 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
168 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
169 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
170 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
171 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, enum pattern_set pattern);
172 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp);
173 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane);
174 void analogix_dp_reset_macro(struct analogix_dp_device *dp);
175 void analogix_dp_init_video(struct analogix_dp_device *dp);
176 
177 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
178 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
179 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, enum clock_recovery_m_value_type type, u32 m_value,
180                                  u32 n_value);
181 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
182 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
183 void analogix_dp_start_video(struct analogix_dp_device *dp);
184 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
185 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
186 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
187 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
188 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
189 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, struct dp_sdp *vsc, bool blocking);
190 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, struct drm_dp_aux_msg *msg);
191 void analogix_dp_set_video_format(struct analogix_dp_device *dp);
192 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp);
193 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp);
194 void analogix_dp_phy_power_on(struct analogix_dp_device *dp);
195 void analogix_dp_phy_power_off(struct analogix_dp_device *dp);
196 void analogix_dp_audio_config_spdif(struct analogix_dp_device *dp);
197 void analogix_dp_audio_config_i2s(struct analogix_dp_device *dp);
198 void analogix_dp_audio_enable(struct analogix_dp_device *dp);
199 void analogix_dp_audio_disable(struct analogix_dp_device *dp);
200 
201 #endif /* _ANALOGIX_DP_CORE_H */
202