1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_MMC_H 10 #define HPM_MMC_H 11 12 typedef struct { 13 __RW uint32_t CR; /* 0x0: Control Register */ 14 __RW uint32_t STA; /* 0x4: Status Register */ 15 __RW uint32_t INT_EN; /* 0x8: Interrupt Enable Register */ 16 __RW uint32_t SYSCLK_FREQ; /* 0xC: System Clock Frequency Register */ 17 __RW uint32_t SYSCLK_PERIOD; /* 0x10: System Clock Period Register */ 18 __RW uint32_t OOSYNC_THETA_THR; /* 0x14: Position Out-Of-Sync Threshold Regster */ 19 __RW uint32_t DISCRETECFG0; /* 0x18: Discrete Mode Configuration 0 Register */ 20 __RW uint32_t DISCRETECFG1; /* 0x1C: Discrete Mode Configuration 1 Register */ 21 __RW uint32_t CONTCFG0; /* 0x20: Continuous Mode Configuration 0 Register */ 22 __RW uint32_t INI_POS_TIME; /* 0x24: The destined timestamp register for position initialization */ 23 __RW uint32_t INI_POS; /* 0x28: The destined position register for position initialization */ 24 __RW uint32_t INI_REV; /* 0x2C: The destined revolution register for position initialization */ 25 __RW uint32_t INI_SPEED; /* 0x30: The destined speed register for position initialization */ 26 __RW uint32_t INI_ACCEL; /* 0x34: The destined accelerator register for position initialization */ 27 __RW uint32_t INI_COEF_TIME; /* 0x38: The destined timestamp register for coefficients initialization */ 28 __RW uint32_t INI_PCOEF; /* 0x3C: The destined coefficient P register for coefficients initialization */ 29 __RW uint32_t INI_ICOEF; /* 0x40: The destined coefficient I register for coefficients initialization */ 30 __RW uint32_t INI_ACOEF; /* 0x44: The destined coefficient A register for coefficients initialization */ 31 __R uint32_t ESTM_TIM; /* 0x48: The timestamp register for internal estimation */ 32 __R uint32_t ESTM_POS; /* 0x4C: The position register for the internal estimation */ 33 __R uint32_t ESTM_REV; /* 0x50: The revolution register for the internal estimation */ 34 __R uint32_t ESTM_SPEED; /* 0x54: The speed register for the internal estimation */ 35 __R uint32_t ESTM_ACCEL; /* 0x58: The accelerator register for theinternal estimation */ 36 __R uint32_t CUR_PCOEF; /* 0x5C: The coefficient P register for the internal estimation */ 37 __R uint32_t CUR_ICOEF; /* 0x60: The coefficient I register for the internal estimation */ 38 __R uint32_t CUR_ACOEF; /* 0x64: The coefficient A register for the internal estimation */ 39 __RW uint32_t INI_DELTA_POS_TIME; /* 0x68: The destined timestamp register for delta position initialization */ 40 __RW uint32_t INI_DELTA_POS; /* 0x6C: The destined delta position register for delta position initialization */ 41 __RW uint32_t INI_DELTA_REV; /* 0x70: The destined delta revolution register for delta position initialization */ 42 __RW uint32_t INI_DELTA_SPEED; /* 0x74: The destined delta speed register for delta position initialization */ 43 __RW uint32_t INI_DELTA_ACCEL; /* 0x78: The destined delta accelerator register for delta position initialization */ 44 __R uint8_t RESERVED0[4]; /* 0x7C - 0x7F: Reserved */ 45 __RW uint32_t POS_TRG_CFG; /* 0x80: Tracking Configuration pos trigger cfg */ 46 __RW uint32_t POS_TRG_POS_THR; /* 0x84: Tracking Configuration position threshold */ 47 __RW uint32_t POS_TRG_REV_THR; /* 0x88: Tracking Configuration revolution threshold */ 48 __RW uint32_t SPEED_TRG_CFG; /* 0x8C: Tracking Configuration speed trigger cfg */ 49 __RW uint32_t SPEED_TRG_THR; /* 0x90: Tracking Configuration speed threshold */ 50 __R uint8_t RESERVED1[12]; /* 0x94 - 0x9F: Reserved */ 51 struct { 52 __RW uint32_t ERR_THR; /* 0xA0: Tracking Configuration coef trigger cfg */ 53 __RW uint32_t P; /* 0xA4: Tracking Configuration coef trigger cfg P */ 54 __RW uint32_t I; /* 0xA8: Tracking Configuration coef trigger cfg I */ 55 __RW uint32_t A; /* 0xAC: Tracking Configuration coef trigger cfg A */ 56 __RW uint32_t TIME; /* 0xB0: Tracking Configuration coef trigger cfg time */ 57 } COEF_TRG_CFG[3]; 58 __R uint8_t RESERVED2[36]; /* 0xDC - 0xFF: Reserved */ 59 struct { 60 __RW uint32_t BR_CTRL; /* 0x100: Prediction Control Register */ 61 __RW uint32_t BR_TIMEOFF; /* 0x104: Prediction Timing Offset Register */ 62 __RW uint32_t BR_TRG_PERIOD; /* 0x108: Prediction Triggering Period Offset Register */ 63 __RW uint32_t BR_TRG_F_TIME; /* 0x10C: Prediction Triggering First Offset Register */ 64 __RW uint32_t BR_ST; /* 0x110: Prediction Status Register */ 65 __R uint8_t RESERVED0[44]; /* 0x114 - 0x13F: Reserved */ 66 __RW uint32_t BR_TRG_POS_CFG; /* 0x140: Prediction Configuration postion trigger cfg */ 67 __RW uint32_t BR_TRG_POS_THR; /* 0x144: Prediction Configuration postion threshold */ 68 __RW uint32_t BR_TRG_REV_THR; /* 0x148: Prediction Configuration revolutiom threshold */ 69 __RW uint32_t BR_TRG_SPEED_CFG; /* 0x14C: Prediction Configuration speed trigger cfg */ 70 __RW uint32_t BR_TRG_SPEED_THR; /* 0x150: Prediction Configuration speed threshold */ 71 __R uint8_t RESERVED1[108]; /* 0x154 - 0x1BF: Reserved */ 72 __RW uint32_t BR_INI_POS_TIME; /* 0x1C0: Initialization timestamp for open-loop mode */ 73 __RW uint32_t BR_INI_POS; /* 0x1C4: Initialization position for open-loop mode */ 74 __RW uint32_t BR_INI_REV; /* 0x1C8: Initialization revolution for open-loop mode */ 75 __RW uint32_t BR_INI_SPEED; /* 0x1CC: Initialization speed for open-loop mode */ 76 __RW uint32_t BR_INI_ACCEL; /* 0x1D0: Initialization acceleration for open-loop mode */ 77 __RW uint32_t BR_INI_DELTA_POS_TIME; /* 0x1D4: Initialization timestamp for delta mode in prediction mode */ 78 __RW uint32_t BR_INI_DELTA_POS; /* 0x1D8: Initialization delta position for delta mode in prediction mode */ 79 __RW uint32_t BR_INI_DELTA_REV; /* 0x1DC: Initialization delta revolution for delta mode in prediction mode */ 80 __RW uint32_t BR_INI_DELTA_SPEED; /* 0x1E0: Initialization delta speed for delta mode in prediction mode */ 81 __RW uint32_t BR_INI_DELTA_ACCEL; /* 0x1E4: Initialization delta acceleration for delta mode in prediction mode */ 82 __R uint8_t RESERVED2[4]; /* 0x1E8 - 0x1EB: Reserved */ 83 __R uint32_t BR_CUR_POS_TIME; /* 0x1EC: Monitor of the output timestamp */ 84 __R uint32_t BR_CUR_POS; /* 0x1F0: Monitor of the output position */ 85 __R uint32_t BR_CUR_REV; /* 0x1F4: Monitor of the output revolution */ 86 __R uint32_t BR_CUR_SPEED; /* 0x1F8: Monitor of the output speed */ 87 __R uint32_t BR_CUR_ACCEL; /* 0x1FC: Monitor of the output acceleration */ 88 } BR[2]; 89 __R uint32_t BK0_TIMESTAMP; /* 0x300: Monitor of the just received input timestamp for tracing logic */ 90 __R uint32_t BK0_POSITION; /* 0x304: Monitor of the just received input position for tracing logic */ 91 __R uint32_t BK0_REVOLUTION; /* 0x308: Monitor of the just received input revolution for tracing logic */ 92 __R uint32_t BK0_SPEED; /* 0x30C: Monitor of the just received input speed for tracing logic */ 93 __R uint32_t BK0_ACCELERATOR; /* 0x310: Monitor of the just received input acceleration for tracing logic */ 94 __R uint8_t RESERVED3[12]; /* 0x314 - 0x31F: Reserved */ 95 __R uint32_t BK1_TIMESTAMP; /* 0x320: Monitor of the previous received input timestamp for tracing logic */ 96 __R uint32_t BK1_POSITION; /* 0x324: Monitor of the previous received input position for tracing logic */ 97 __R uint32_t BK1_REVOLUTION; /* 0x328: Monitor of the previous received input revolution for tracing logic */ 98 __R uint32_t BK1_SPEED; /* 0x32C: Monitor of the previous received input speed for tracing logic */ 99 __R uint32_t BK1_ACCELERATOR; /* 0x330: Monitor of the previous received input acceleration for tracing logic */ 100 } MMC_Type; 101 102 103 /* Bitfield definition for register: CR */ 104 /* 105 * SFTRST (RW) 106 * 107 * Software reset, high active. When write 1 ,all internal logical will be reset. 108 * 0b - No action 109 * 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. 110 */ 111 #define MMC_CR_SFTRST_MASK (0x80000000UL) 112 #define MMC_CR_SFTRST_SHIFT (31U) 113 #define MMC_CR_SFTRST_SET(x) (((uint32_t)(x) << MMC_CR_SFTRST_SHIFT) & MMC_CR_SFTRST_MASK) 114 #define MMC_CR_SFTRST_GET(x) (((uint32_t)(x) & MMC_CR_SFTRST_MASK) >> MMC_CR_SFTRST_SHIFT) 115 116 /* 117 * INI_BR0_POS_REQ (RW) 118 * 119 * Auto clear. Only effective in open_loop mode. 120 */ 121 #define MMC_CR_INI_BR0_POS_REQ_MASK (0x20000000UL) 122 #define MMC_CR_INI_BR0_POS_REQ_SHIFT (29U) 123 #define MMC_CR_INI_BR0_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR0_POS_REQ_SHIFT) & MMC_CR_INI_BR0_POS_REQ_MASK) 124 #define MMC_CR_INI_BR0_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR0_POS_REQ_MASK) >> MMC_CR_INI_BR0_POS_REQ_SHIFT) 125 126 /* 127 * INI_BR1_POS_REQ (RW) 128 * 129 * Auto clear. Only effective in open_loop mode. 130 */ 131 #define MMC_CR_INI_BR1_POS_REQ_MASK (0x10000000UL) 132 #define MMC_CR_INI_BR1_POS_REQ_SHIFT (28U) 133 #define MMC_CR_INI_BR1_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR1_POS_REQ_SHIFT) & MMC_CR_INI_BR1_POS_REQ_MASK) 134 #define MMC_CR_INI_BR1_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR1_POS_REQ_MASK) >> MMC_CR_INI_BR1_POS_REQ_SHIFT) 135 136 /* 137 * FRCACCELZERO (RW) 138 * 139 * Zeroise the accelerator calculation. 140 */ 141 #define MMC_CR_FRCACCELZERO_MASK (0x8000000UL) 142 #define MMC_CR_FRCACCELZERO_SHIFT (27U) 143 #define MMC_CR_FRCACCELZERO_SET(x) (((uint32_t)(x) << MMC_CR_FRCACCELZERO_SHIFT) & MMC_CR_FRCACCELZERO_MASK) 144 #define MMC_CR_FRCACCELZERO_GET(x) (((uint32_t)(x) & MMC_CR_FRCACCELZERO_MASK) >> MMC_CR_FRCACCELZERO_SHIFT) 145 146 /* 147 * MS_COEF_EN (RW) 148 * 149 * Multiple Coefficients Enable 150 */ 151 #define MMC_CR_MS_COEF_EN_MASK (0x4000000UL) 152 #define MMC_CR_MS_COEF_EN_SHIFT (26U) 153 #define MMC_CR_MS_COEF_EN_SET(x) (((uint32_t)(x) << MMC_CR_MS_COEF_EN_SHIFT) & MMC_CR_MS_COEF_EN_MASK) 154 #define MMC_CR_MS_COEF_EN_GET(x) (((uint32_t)(x) & MMC_CR_MS_COEF_EN_MASK) >> MMC_CR_MS_COEF_EN_SHIFT) 155 156 /* 157 * INI_DELTA_POS_TRG_TYPE (RW) 158 * 159 * 0: Time Stamp in the configuration 160 * 1: Risedge of In Trg[0] 161 * 2: Risedge of In Trg[1] 162 * 3: Risedge of out trg[0] 163 * 4: Risedge of out trg[1] 164 * 5: triggered by self position trigger 165 * 6: triggered by self speed trigger 166 * Otherser: no function 167 */ 168 #define MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK (0x3800000UL) 169 #define MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT (23U) 170 #define MMC_CR_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) 171 #define MMC_CR_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) 172 173 /* 174 * INI_POS_TRG_TYPE (RW) 175 * 176 * 0: Time Stamp in the configuration 177 * 1: Risedge of In Trg[0] 178 * 2: Risedge of In Trg[1] 179 * 3: Risedge of out trg[0] 180 * 4: Risedge of out trg[1] 181 * 5: triggered by self position trigger 182 * 6: triggered by self speed trigger 183 * Otherser: no function 184 */ 185 #define MMC_CR_INI_POS_TRG_TYPE_MASK (0x700000UL) 186 #define MMC_CR_INI_POS_TRG_TYPE_SHIFT (20U) 187 #define MMC_CR_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_POS_TRG_TYPE_MASK) 188 #define MMC_CR_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_TRG_TYPE_MASK) >> MMC_CR_INI_POS_TRG_TYPE_SHIFT) 189 190 /* 191 * INI_DELTA_POS_CMD_MSK (RW) 192 * 193 * 1: change 194 * 0: won't change 195 * bit 3: for delta accel 196 * bit 2: for delta speed 197 * bit 1: for delta revolution 198 * bit 0: for delta position 199 */ 200 #define MMC_CR_INI_DELTA_POS_CMD_MSK_MASK (0xF0000UL) 201 #define MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT (16U) 202 #define MMC_CR_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) 203 #define MMC_CR_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) 204 205 /* 206 * INI_DELTA_POS_REQ (RW) 207 * 208 * 1: Command to reload the delta pos. Auto clear 209 * 0: 210 */ 211 #define MMC_CR_INI_DELTA_POS_REQ_MASK (0x8000U) 212 #define MMC_CR_INI_DELTA_POS_REQ_SHIFT (15U) 213 #define MMC_CR_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_REQ_SHIFT) & MMC_CR_INI_DELTA_POS_REQ_MASK) 214 #define MMC_CR_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_REQ_MASK) >> MMC_CR_INI_DELTA_POS_REQ_SHIFT) 215 216 /* 217 * OPEN_LOOP_MODE (RW) 218 * 219 * 1: in open loop mode 220 * 0: not in open loop mode 221 */ 222 #define MMC_CR_OPEN_LOOP_MODE_MASK (0x4000U) 223 #define MMC_CR_OPEN_LOOP_MODE_SHIFT (14U) 224 #define MMC_CR_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_CR_OPEN_LOOP_MODE_SHIFT) & MMC_CR_OPEN_LOOP_MODE_MASK) 225 #define MMC_CR_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_CR_OPEN_LOOP_MODE_MASK) >> MMC_CR_OPEN_LOOP_MODE_SHIFT) 226 227 /* 228 * POS_TYPE (RW) 229 * 230 * 1: 32-bit for rev+pos, with each element occupying 16 bits 231 * 0: 32-bit for rev, and 32 bit for pos 232 * When CR[MANUAL_IO]==1, 233 * 1: means that the INI_POS is acting as INI_POS cmds 234 * 0: means that the INI_POS is simulating the input of iposition and itimestamp 235 */ 236 #define MMC_CR_POS_TYPE_MASK (0x2000U) 237 #define MMC_CR_POS_TYPE_SHIFT (13U) 238 #define MMC_CR_POS_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_POS_TYPE_SHIFT) & MMC_CR_POS_TYPE_MASK) 239 #define MMC_CR_POS_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_POS_TYPE_MASK) >> MMC_CR_POS_TYPE_SHIFT) 240 241 /* 242 * INI_POS_CMD_MSK (RW) 243 * 244 * 1: change 245 * 0: won't change 246 * bit 3: for accel 247 * bit 2: for speed 248 * bit 1: for revolution 249 * bit 0: for position 250 */ 251 #define MMC_CR_INI_POS_CMD_MSK_MASK (0x1E00U) 252 #define MMC_CR_INI_POS_CMD_MSK_SHIFT (9U) 253 #define MMC_CR_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_CMD_MSK_SHIFT) & MMC_CR_INI_POS_CMD_MSK_MASK) 254 #define MMC_CR_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_CMD_MSK_MASK) >> MMC_CR_INI_POS_CMD_MSK_SHIFT) 255 256 /* 257 * INI_POS_REQ (RW) 258 * 259 * 1: Command to reload the positions. Auto clear 260 * 0: 261 */ 262 #define MMC_CR_INI_POS_REQ_MASK (0x100U) 263 #define MMC_CR_INI_POS_REQ_SHIFT (8U) 264 #define MMC_CR_INI_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_REQ_SHIFT) & MMC_CR_INI_POS_REQ_MASK) 265 #define MMC_CR_INI_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_REQ_MASK) >> MMC_CR_INI_POS_REQ_SHIFT) 266 267 /* 268 * INI_COEFS_CMD_MSK (RW) 269 * 270 * 1: change 271 * 0: won't change 272 * bit 2: for ACOEF 273 * bit 1: for ICOEF 274 * bit 0: for PCOEF 275 */ 276 #define MMC_CR_INI_COEFS_CMD_MSK_MASK (0xE0U) 277 #define MMC_CR_INI_COEFS_CMD_MSK_SHIFT (5U) 278 #define MMC_CR_INI_COEFS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_MSK_SHIFT) & MMC_CR_INI_COEFS_CMD_MSK_MASK) 279 #define MMC_CR_INI_COEFS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MSK_MASK) >> MMC_CR_INI_COEFS_CMD_MSK_SHIFT) 280 281 /* 282 * INI_COEFS_CMD (RW) 283 * 284 * 1: Command to reload the coefs. Auto clear 285 * 0: 286 */ 287 #define MMC_CR_INI_COEFS_CMD_MASK (0x10U) 288 #define MMC_CR_INI_COEFS_CMD_SHIFT (4U) 289 #define MMC_CR_INI_COEFS_CMD_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_SHIFT) & MMC_CR_INI_COEFS_CMD_MASK) 290 #define MMC_CR_INI_COEFS_CMD_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MASK) >> MMC_CR_INI_COEFS_CMD_SHIFT) 291 292 /* 293 * SHADOW_RD_REQ (RW) 294 * 295 * 1: Shadow Request for read of tracking parameters. Auto clear 296 * 0: 297 */ 298 #define MMC_CR_SHADOW_RD_REQ_MASK (0x8U) 299 #define MMC_CR_SHADOW_RD_REQ_SHIFT (3U) 300 #define MMC_CR_SHADOW_RD_REQ_SET(x) (((uint32_t)(x) << MMC_CR_SHADOW_RD_REQ_SHIFT) & MMC_CR_SHADOW_RD_REQ_MASK) 301 #define MMC_CR_SHADOW_RD_REQ_GET(x) (((uint32_t)(x) & MMC_CR_SHADOW_RD_REQ_MASK) >> MMC_CR_SHADOW_RD_REQ_SHIFT) 302 303 /* 304 * ADJOP (RW) 305 * 306 * 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. 307 * 0: Continuous tracking mode, without any boundary check 308 */ 309 #define MMC_CR_ADJOP_MASK (0x4U) 310 #define MMC_CR_ADJOP_SHIFT (2U) 311 #define MMC_CR_ADJOP_SET(x) (((uint32_t)(x) << MMC_CR_ADJOP_SHIFT) & MMC_CR_ADJOP_MASK) 312 #define MMC_CR_ADJOP_GET(x) (((uint32_t)(x) & MMC_CR_ADJOP_MASK) >> MMC_CR_ADJOP_SHIFT) 313 314 /* 315 * DISCRETETRC (RW) 316 * 317 * 1: Discrete position input 318 * 0: Continuous position input 319 */ 320 #define MMC_CR_DISCRETETRC_MASK (0x2U) 321 #define MMC_CR_DISCRETETRC_SHIFT (1U) 322 #define MMC_CR_DISCRETETRC_SET(x) (((uint32_t)(x) << MMC_CR_DISCRETETRC_SHIFT) & MMC_CR_DISCRETETRC_MASK) 323 #define MMC_CR_DISCRETETRC_GET(x) (((uint32_t)(x) & MMC_CR_DISCRETETRC_MASK) >> MMC_CR_DISCRETETRC_SHIFT) 324 325 /* 326 * MOD_EN (RW) 327 * 328 * Module Enable 329 */ 330 #define MMC_CR_MOD_EN_MASK (0x1U) 331 #define MMC_CR_MOD_EN_SHIFT (0U) 332 #define MMC_CR_MOD_EN_SET(x) (((uint32_t)(x) << MMC_CR_MOD_EN_SHIFT) & MMC_CR_MOD_EN_MASK) 333 #define MMC_CR_MOD_EN_GET(x) (((uint32_t)(x) & MMC_CR_MOD_EN_MASK) >> MMC_CR_MOD_EN_SHIFT) 334 335 /* Bitfield definition for register: STA */ 336 /* 337 * ERR_ID (RO) 338 * 339 * Tracking ERR_ID 340 */ 341 #define MMC_STA_ERR_ID_MASK (0xF0000000UL) 342 #define MMC_STA_ERR_ID_SHIFT (28U) 343 #define MMC_STA_ERR_ID_GET(x) (((uint32_t)(x) & MMC_STA_ERR_ID_MASK) >> MMC_STA_ERR_ID_SHIFT) 344 345 /* 346 * SPEED_TRG_VALID (W1C) 347 * 348 * W1C 349 */ 350 #define MMC_STA_SPEED_TRG_VALID_MASK (0x400U) 351 #define MMC_STA_SPEED_TRG_VALID_SHIFT (10U) 352 #define MMC_STA_SPEED_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_SPEED_TRG_VALID_SHIFT) & MMC_STA_SPEED_TRG_VALID_MASK) 353 #define MMC_STA_SPEED_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_SPEED_TRG_VALID_MASK) >> MMC_STA_SPEED_TRG_VALID_SHIFT) 354 355 /* 356 * POS_TRG_VALID (W1C) 357 * 358 * W1C 359 */ 360 #define MMC_STA_POS_TRG_VALID_MASK (0x200U) 361 #define MMC_STA_POS_TRG_VALID_SHIFT (9U) 362 #define MMC_STA_POS_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_POS_TRG_VALID_SHIFT) & MMC_STA_POS_TRG_VALID_MASK) 363 #define MMC_STA_POS_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_POS_TRG_VALID_MASK) >> MMC_STA_POS_TRG_VALID_SHIFT) 364 365 /* 366 * INI_DELTA_POS_REQ_CMD_DONE (W1C) 367 * 368 * W1C 369 */ 370 #define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK (0x100U) 371 #define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT (8U) 372 #define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) 373 #define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) 374 375 /* 376 * INI_BR0_POS_REQ_CMD_DONE (W1C) 377 * 378 * W1C 379 */ 380 #define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK (0x80U) 381 #define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT (7U) 382 #define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) 383 #define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) 384 385 /* 386 * INI_BR1_POS_REQ_CMD_DONE (W1C) 387 * 388 * W1C 389 */ 390 #define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK (0x40U) 391 #define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT (6U) 392 #define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) 393 #define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) 394 395 /* 396 * IDLE (RO) 397 * 398 * Tracking Module in Idle status 399 */ 400 #define MMC_STA_IDLE_MASK (0x20U) 401 #define MMC_STA_IDLE_SHIFT (5U) 402 #define MMC_STA_IDLE_GET(x) (((uint32_t)(x) & MMC_STA_IDLE_MASK) >> MMC_STA_IDLE_SHIFT) 403 404 /* 405 * OOSYNC (W1C) 406 * 407 * Tracking module out-of sync. W1C 408 */ 409 #define MMC_STA_OOSYNC_MASK (0x10U) 410 #define MMC_STA_OOSYNC_SHIFT (4U) 411 #define MMC_STA_OOSYNC_SET(x) (((uint32_t)(x) << MMC_STA_OOSYNC_SHIFT) & MMC_STA_OOSYNC_MASK) 412 #define MMC_STA_OOSYNC_GET(x) (((uint32_t)(x) & MMC_STA_OOSYNC_MASK) >> MMC_STA_OOSYNC_SHIFT) 413 414 /* 415 * INI_POS_REQ_CMD_DONE (W1C) 416 * 417 * W1C 418 */ 419 #define MMC_STA_INI_POS_REQ_CMD_DONE_MASK (0x4U) 420 #define MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT (2U) 421 #define MMC_STA_INI_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) 422 #define MMC_STA_INI_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) 423 424 /* 425 * INI_COEFS_CMD_DONE (W1C) 426 * 427 * W1C 428 */ 429 #define MMC_STA_INI_COEFS_CMD_DONE_MASK (0x2U) 430 #define MMC_STA_INI_COEFS_CMD_DONE_SHIFT (1U) 431 #define MMC_STA_INI_COEFS_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_COEFS_CMD_DONE_SHIFT) & MMC_STA_INI_COEFS_CMD_DONE_MASK) 432 #define MMC_STA_INI_COEFS_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_COEFS_CMD_DONE_MASK) >> MMC_STA_INI_COEFS_CMD_DONE_SHIFT) 433 434 /* 435 * SHADOW_RD_DONE (RO) 436 * 437 * Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 438 */ 439 #define MMC_STA_SHADOW_RD_DONE_MASK (0x1U) 440 #define MMC_STA_SHADOW_RD_DONE_SHIFT (0U) 441 #define MMC_STA_SHADOW_RD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_SHADOW_RD_DONE_MASK) >> MMC_STA_SHADOW_RD_DONE_SHIFT) 442 443 /* Bitfield definition for register: INT_EN */ 444 /* 445 * SPEED_TRG_VLD_IE (RW) 446 * 447 * Interrupt Enable for SPEED_TRG_VALID 448 */ 449 #define MMC_INT_EN_SPEED_TRG_VLD_IE_MASK (0x400U) 450 #define MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT (10U) 451 #define MMC_INT_EN_SPEED_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) 452 #define MMC_INT_EN_SPEED_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) >> MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) 453 454 /* 455 * POS_TRG_VLD_IE (RW) 456 * 457 * Interrupt Enable for POS_TRG_VALID 458 */ 459 #define MMC_INT_EN_POS_TRG_VLD_IE_MASK (0x200U) 460 #define MMC_INT_EN_POS_TRG_VLD_IE_SHIFT (9U) 461 #define MMC_INT_EN_POS_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) 462 #define MMC_INT_EN_POS_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) >> MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) 463 464 /* 465 * INI_DELTA_POS_REQ_CMD_DONE_IE (RW) 466 * 467 * Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE 468 */ 469 #define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK (0x100U) 470 #define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT (8U) 471 #define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) 472 #define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) 473 474 /* 475 * INI_BR0_POS_REQ_CMD_DONE_IE (RW) 476 * 477 * Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE 478 */ 479 #define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK (0x80U) 480 #define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT (7U) 481 #define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) 482 #define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) 483 484 /* 485 * INI_BR1_POS_REQ_CMD_DONE_IE (RW) 486 * 487 * Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE 488 */ 489 #define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK (0x40U) 490 #define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT (6U) 491 #define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) 492 #define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) 493 494 /* 495 * OOSYNC_IE (RW) 496 * 497 * Interrupt Enable for OOSYNC 498 */ 499 #define MMC_INT_EN_OOSYNC_IE_MASK (0x10U) 500 #define MMC_INT_EN_OOSYNC_IE_SHIFT (4U) 501 #define MMC_INT_EN_OOSYNC_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_OOSYNC_IE_SHIFT) & MMC_INT_EN_OOSYNC_IE_MASK) 502 #define MMC_INT_EN_OOSYNC_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_OOSYNC_IE_MASK) >> MMC_INT_EN_OOSYNC_IE_SHIFT) 503 504 /* 505 * INI_POS_REQ_CMD_DONE_IE (RW) 506 * 507 * Interrupt Enable for INI_POS_REQ_CMD_DONE 508 */ 509 #define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK (0x4U) 510 #define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT (2U) 511 #define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) 512 #define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) 513 514 /* 515 * INI_COEFS_CMD_DONE_IE (RW) 516 * 517 * Interrupt Enable for INI_COEFS_CMD_DONE 518 */ 519 #define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK (0x2U) 520 #define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT (1U) 521 #define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) 522 #define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) 523 524 /* 525 * SHADOW_RD_DONE_IE (RW) 526 * 527 * Interrupt Enable for SHADOW_RD_DONE 528 */ 529 #define MMC_INT_EN_SHADOW_RD_DONE_IE_MASK (0x1U) 530 #define MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT (0U) 531 #define MMC_INT_EN_SHADOW_RD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) 532 #define MMC_INT_EN_SHADOW_RD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) >> MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) 533 534 /* Bitfield definition for register: SYSCLK_FREQ */ 535 /* 536 * VAL (RW) 537 * 538 * system clock frequency, ufix<32, 0> 539 */ 540 #define MMC_SYSCLK_FREQ_VAL_MASK (0xFFFFFFFFUL) 541 #define MMC_SYSCLK_FREQ_VAL_SHIFT (0U) 542 #define MMC_SYSCLK_FREQ_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_FREQ_VAL_SHIFT) & MMC_SYSCLK_FREQ_VAL_MASK) 543 #define MMC_SYSCLK_FREQ_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_FREQ_VAL_MASK) >> MMC_SYSCLK_FREQ_VAL_SHIFT) 544 545 /* Bitfield definition for register: SYSCLK_PERIOD */ 546 /* 547 * VAL (RW) 548 * 549 * round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> 550 */ 551 #define MMC_SYSCLK_PERIOD_VAL_MASK (0xFFFFFFFFUL) 552 #define MMC_SYSCLK_PERIOD_VAL_SHIFT (0U) 553 #define MMC_SYSCLK_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_PERIOD_VAL_SHIFT) & MMC_SYSCLK_PERIOD_VAL_MASK) 554 #define MMC_SYSCLK_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_PERIOD_VAL_MASK) >> MMC_SYSCLK_PERIOD_VAL_SHIFT) 555 556 /* Bitfield definition for register: OOSYNC_THETA_THR */ 557 /* 558 * VAL (RW) 559 * 560 * the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> 561 */ 562 #define MMC_OOSYNC_THETA_THR_VAL_MASK (0xFFFFFFFFUL) 563 #define MMC_OOSYNC_THETA_THR_VAL_SHIFT (0U) 564 #define MMC_OOSYNC_THETA_THR_VAL_SET(x) (((uint32_t)(x) << MMC_OOSYNC_THETA_THR_VAL_SHIFT) & MMC_OOSYNC_THETA_THR_VAL_MASK) 565 #define MMC_OOSYNC_THETA_THR_VAL_GET(x) (((uint32_t)(x) & MMC_OOSYNC_THETA_THR_VAL_MASK) >> MMC_OOSYNC_THETA_THR_VAL_SHIFT) 566 567 /* Bitfield definition for register: DISCRETECFG0 */ 568 /* 569 * POSMAX (RW) 570 * 571 * Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> 572 */ 573 #define MMC_DISCRETECFG0_POSMAX_MASK (0xFFFFFUL) 574 #define MMC_DISCRETECFG0_POSMAX_SHIFT (0U) 575 #define MMC_DISCRETECFG0_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG0_POSMAX_SHIFT) & MMC_DISCRETECFG0_POSMAX_MASK) 576 #define MMC_DISCRETECFG0_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG0_POSMAX_MASK) >> MMC_DISCRETECFG0_POSMAX_SHIFT) 577 578 /* Bitfield definition for register: DISCRETECFG1 */ 579 /* 580 * INV_POSMAX (RW) 581 * 582 * discrete mode: ufix<32, 0> of 1/(Number Of Lines) 583 * continuous mode: the max delta for tracking from the last received position, ufix<32, 32> 584 */ 585 #define MMC_DISCRETECFG1_INV_POSMAX_MASK (0xFFFFFFFFUL) 586 #define MMC_DISCRETECFG1_INV_POSMAX_SHIFT (0U) 587 #define MMC_DISCRETECFG1_INV_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG1_INV_POSMAX_SHIFT) & MMC_DISCRETECFG1_INV_POSMAX_MASK) 588 #define MMC_DISCRETECFG1_INV_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG1_INV_POSMAX_MASK) >> MMC_DISCRETECFG1_INV_POSMAX_SHIFT) 589 590 /* Bitfield definition for register: CONTCFG0 */ 591 /* 592 * HALF_CIRC_THETA (RW) 593 * 594 * the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> 595 */ 596 #define MMC_CONTCFG0_HALF_CIRC_THETA_MASK (0xFFFFFFFFUL) 597 #define MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT (0U) 598 #define MMC_CONTCFG0_HALF_CIRC_THETA_SET(x) (((uint32_t)(x) << MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) 599 #define MMC_CONTCFG0_HALF_CIRC_THETA_GET(x) (((uint32_t)(x) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) >> MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) 600 601 /* Bitfield definition for register: INI_POS_TIME */ 602 /* 603 * VAL (RW) 604 * 605 * indicate the time to change the values. 606 * 0: instant change 607 */ 608 #define MMC_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) 609 #define MMC_INI_POS_TIME_VAL_SHIFT (0U) 610 #define MMC_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_TIME_VAL_SHIFT) & MMC_INI_POS_TIME_VAL_MASK) 611 #define MMC_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_TIME_VAL_MASK) >> MMC_INI_POS_TIME_VAL_SHIFT) 612 613 /* Bitfield definition for register: INI_POS */ 614 /* 615 * VAL (RW) 616 * 617 * the value； 618 * continuous mode: ufix<32, 32> 619 */ 620 #define MMC_INI_POS_VAL_MASK (0xFFFFFFFFUL) 621 #define MMC_INI_POS_VAL_SHIFT (0U) 622 #define MMC_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_VAL_SHIFT) & MMC_INI_POS_VAL_MASK) 623 #define MMC_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_VAL_MASK) >> MMC_INI_POS_VAL_SHIFT) 624 625 /* Bitfield definition for register: INI_REV */ 626 /* 627 * VAL (RW) 628 * 629 * the value； 630 * continuous mode: ufix<32, 0> 631 */ 632 #define MMC_INI_REV_VAL_MASK (0xFFFFFFFFUL) 633 #define MMC_INI_REV_VAL_SHIFT (0U) 634 #define MMC_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_REV_VAL_SHIFT) & MMC_INI_REV_VAL_MASK) 635 #define MMC_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_REV_VAL_MASK) >> MMC_INI_REV_VAL_SHIFT) 636 637 /* Bitfield definition for register: INI_SPEED */ 638 /* 639 * VAL (RW) 640 * 641 * the value; 642 * continuous mode: fix<32, 19> 643 */ 644 #define MMC_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) 645 #define MMC_INI_SPEED_VAL_SHIFT (0U) 646 #define MMC_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_SPEED_VAL_SHIFT) & MMC_INI_SPEED_VAL_MASK) 647 #define MMC_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_SPEED_VAL_MASK) >> MMC_INI_SPEED_VAL_SHIFT) 648 649 /* Bitfield definition for register: INI_ACCEL */ 650 /* 651 * VAL (RW) 652 * 653 * the value 654 * continuous mode: fix<32, 19> 655 */ 656 #define MMC_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) 657 #define MMC_INI_ACCEL_VAL_SHIFT (0U) 658 #define MMC_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACCEL_VAL_SHIFT) & MMC_INI_ACCEL_VAL_MASK) 659 #define MMC_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACCEL_VAL_MASK) >> MMC_INI_ACCEL_VAL_SHIFT) 660 661 /* Bitfield definition for register: INI_COEF_TIME */ 662 /* 663 * VAL (RW) 664 * 665 * indicate the time to change the values. 666 * 0: instant change 667 */ 668 #define MMC_INI_COEF_TIME_VAL_MASK (0xFFFFFFFFUL) 669 #define MMC_INI_COEF_TIME_VAL_SHIFT (0U) 670 #define MMC_INI_COEF_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_COEF_TIME_VAL_SHIFT) & MMC_INI_COEF_TIME_VAL_MASK) 671 #define MMC_INI_COEF_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_COEF_TIME_VAL_MASK) >> MMC_INI_COEF_TIME_VAL_SHIFT) 672 673 /* Bitfield definition for register: INI_PCOEF */ 674 /* 675 * VAL (RW) 676 * 677 * the value, fix<32, 15> 678 */ 679 #define MMC_INI_PCOEF_VAL_MASK (0xFFFFFFFFUL) 680 #define MMC_INI_PCOEF_VAL_SHIFT (0U) 681 #define MMC_INI_PCOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_PCOEF_VAL_SHIFT) & MMC_INI_PCOEF_VAL_MASK) 682 #define MMC_INI_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_PCOEF_VAL_MASK) >> MMC_INI_PCOEF_VAL_SHIFT) 683 684 /* Bitfield definition for register: INI_ICOEF */ 685 /* 686 * VAL (RW) 687 * 688 * the value, fix<32, 21> 689 */ 690 #define MMC_INI_ICOEF_VAL_MASK (0xFFFFFFFFUL) 691 #define MMC_INI_ICOEF_VAL_SHIFT (0U) 692 #define MMC_INI_ICOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ICOEF_VAL_SHIFT) & MMC_INI_ICOEF_VAL_MASK) 693 #define MMC_INI_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ICOEF_VAL_MASK) >> MMC_INI_ICOEF_VAL_SHIFT) 694 695 /* Bitfield definition for register: INI_ACOEF */ 696 /* 697 * VAL (RW) 698 * 699 * the value, fix<32, 19> 700 */ 701 #define MMC_INI_ACOEF_VAL_MASK (0xFFFFFFFFUL) 702 #define MMC_INI_ACOEF_VAL_SHIFT (0U) 703 #define MMC_INI_ACOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACOEF_VAL_SHIFT) & MMC_INI_ACOEF_VAL_MASK) 704 #define MMC_INI_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACOEF_VAL_MASK) >> MMC_INI_ACOEF_VAL_SHIFT) 705 706 /* Bitfield definition for register: ESTM_TIM */ 707 /* 708 * VAL (RO) 709 * 710 * the value 711 */ 712 #define MMC_ESTM_TIM_VAL_MASK (0xFFFFFFFFUL) 713 #define MMC_ESTM_TIM_VAL_SHIFT (0U) 714 #define MMC_ESTM_TIM_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_TIM_VAL_MASK) >> MMC_ESTM_TIM_VAL_SHIFT) 715 716 /* Bitfield definition for register: ESTM_POS */ 717 /* 718 * VAL (RO) 719 * 720 * the value 721 */ 722 #define MMC_ESTM_POS_VAL_MASK (0xFFFFFFFFUL) 723 #define MMC_ESTM_POS_VAL_SHIFT (0U) 724 #define MMC_ESTM_POS_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_POS_VAL_MASK) >> MMC_ESTM_POS_VAL_SHIFT) 725 726 /* Bitfield definition for register: ESTM_REV */ 727 /* 728 * VAL (RO) 729 * 730 * the value 731 */ 732 #define MMC_ESTM_REV_VAL_MASK (0xFFFFFFFFUL) 733 #define MMC_ESTM_REV_VAL_SHIFT (0U) 734 #define MMC_ESTM_REV_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_REV_VAL_MASK) >> MMC_ESTM_REV_VAL_SHIFT) 735 736 /* Bitfield definition for register: ESTM_SPEED */ 737 /* 738 * VAL (RO) 739 * 740 * the value 741 */ 742 #define MMC_ESTM_SPEED_VAL_MASK (0xFFFFFFFFUL) 743 #define MMC_ESTM_SPEED_VAL_SHIFT (0U) 744 #define MMC_ESTM_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_SPEED_VAL_MASK) >> MMC_ESTM_SPEED_VAL_SHIFT) 745 746 /* Bitfield definition for register: ESTM_ACCEL */ 747 /* 748 * VAL (RO) 749 * 750 * the value 751 */ 752 #define MMC_ESTM_ACCEL_VAL_MASK (0xFFFFFFFFUL) 753 #define MMC_ESTM_ACCEL_VAL_SHIFT (0U) 754 #define MMC_ESTM_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_ACCEL_VAL_MASK) >> MMC_ESTM_ACCEL_VAL_SHIFT) 755 756 /* Bitfield definition for register: CUR_PCOEF */ 757 /* 758 * VAL (RO) 759 * 760 * the value 761 */ 762 #define MMC_CUR_PCOEF_VAL_MASK (0xFFFFFFFFUL) 763 #define MMC_CUR_PCOEF_VAL_SHIFT (0U) 764 #define MMC_CUR_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_PCOEF_VAL_MASK) >> MMC_CUR_PCOEF_VAL_SHIFT) 765 766 /* Bitfield definition for register: CUR_ICOEF */ 767 /* 768 * VAL (RO) 769 * 770 * the value 771 */ 772 #define MMC_CUR_ICOEF_VAL_MASK (0xFFFFFFFFUL) 773 #define MMC_CUR_ICOEF_VAL_SHIFT (0U) 774 #define MMC_CUR_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ICOEF_VAL_MASK) >> MMC_CUR_ICOEF_VAL_SHIFT) 775 776 /* Bitfield definition for register: CUR_ACOEF */ 777 /* 778 * VAL (RO) 779 * 780 * the value 781 */ 782 #define MMC_CUR_ACOEF_VAL_MASK (0xFFFFFFFFUL) 783 #define MMC_CUR_ACOEF_VAL_SHIFT (0U) 784 #define MMC_CUR_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ACOEF_VAL_MASK) >> MMC_CUR_ACOEF_VAL_SHIFT) 785 786 /* Bitfield definition for register: INI_DELTA_POS_TIME */ 787 /* 788 * VAL (RW) 789 * 790 * indicate the time to change the values. 791 * 0: instant change 792 */ 793 #define MMC_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) 794 #define MMC_INI_DELTA_POS_TIME_VAL_SHIFT (0U) 795 #define MMC_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_INI_DELTA_POS_TIME_VAL_MASK) 796 #define MMC_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_INI_DELTA_POS_TIME_VAL_SHIFT) 797 798 /* Bitfield definition for register: INI_DELTA_POS */ 799 /* 800 * VAL (RW) 801 * 802 * the value 803 * continuous mode: ufix <32, 32> 804 */ 805 #define MMC_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) 806 #define MMC_INI_DELTA_POS_VAL_SHIFT (0U) 807 #define MMC_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_VAL_SHIFT) & MMC_INI_DELTA_POS_VAL_MASK) 808 #define MMC_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_VAL_MASK) >> MMC_INI_DELTA_POS_VAL_SHIFT) 809 810 /* Bitfield definition for register: INI_DELTA_REV */ 811 /* 812 * VAL (RW) 813 * 814 * the value 815 * continuous mode: fix<32, 0> 816 */ 817 #define MMC_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) 818 #define MMC_INI_DELTA_REV_VAL_SHIFT (0U) 819 #define MMC_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_REV_VAL_SHIFT) & MMC_INI_DELTA_REV_VAL_MASK) 820 #define MMC_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_REV_VAL_MASK) >> MMC_INI_DELTA_REV_VAL_SHIFT) 821 822 /* Bitfield definition for register: INI_DELTA_SPEED */ 823 /* 824 * VAL (RW) 825 * 826 * the value； 827 * continuous mode: fix<32, 19> 828 */ 829 #define MMC_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) 830 #define MMC_INI_DELTA_SPEED_VAL_SHIFT (0U) 831 #define MMC_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_SPEED_VAL_SHIFT) & MMC_INI_DELTA_SPEED_VAL_MASK) 832 #define MMC_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_SPEED_VAL_MASK) >> MMC_INI_DELTA_SPEED_VAL_SHIFT) 833 834 /* Bitfield definition for register: INI_DELTA_ACCEL */ 835 /* 836 * VAL (RW) 837 * 838 * the value 839 * continuous mode: fix<32, 19> 840 */ 841 #define MMC_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) 842 #define MMC_INI_DELTA_ACCEL_VAL_SHIFT (0U) 843 #define MMC_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_INI_DELTA_ACCEL_VAL_MASK) 844 #define MMC_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_ACCEL_VAL_MASK) >> MMC_INI_DELTA_ACCEL_VAL_SHIFT) 845 846 /* Bitfield definition for register: POS_TRG_CFG */ 847 /* 848 * EDGE (RW) 849 * 850 * 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than 851 */ 852 #define MMC_POS_TRG_CFG_EDGE_MASK (0x2U) 853 #define MMC_POS_TRG_CFG_EDGE_SHIFT (1U) 854 #define MMC_POS_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EDGE_SHIFT) & MMC_POS_TRG_CFG_EDGE_MASK) 855 #define MMC_POS_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EDGE_MASK) >> MMC_POS_TRG_CFG_EDGE_SHIFT) 856 857 /* 858 * EN (RW) 859 * 860 * 1-trigger valid; 0-Trigger not valid" 861 */ 862 #define MMC_POS_TRG_CFG_EN_MASK (0x1U) 863 #define MMC_POS_TRG_CFG_EN_SHIFT (0U) 864 #define MMC_POS_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EN_SHIFT) & MMC_POS_TRG_CFG_EN_MASK) 865 #define MMC_POS_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EN_MASK) >> MMC_POS_TRG_CFG_EN_SHIFT) 866 867 /* Bitfield definition for register: POS_TRG_POS_THR */ 868 /* 869 * VAL (RW) 870 * 871 * For pos out trigger (pos). 872 * ufix<32, 32> 873 */ 874 #define MMC_POS_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) 875 #define MMC_POS_TRG_POS_THR_VAL_SHIFT (0U) 876 #define MMC_POS_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_POS_THR_VAL_SHIFT) & MMC_POS_TRG_POS_THR_VAL_MASK) 877 #define MMC_POS_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_POS_THR_VAL_MASK) >> MMC_POS_TRG_POS_THR_VAL_SHIFT) 878 879 /* Bitfield definition for register: POS_TRG_REV_THR */ 880 /* 881 * VAL (RW) 882 * 883 * For pos out trigger (rev) 884 * fix<32, 0> 885 */ 886 #define MMC_POS_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) 887 #define MMC_POS_TRG_REV_THR_VAL_SHIFT (0U) 888 #define MMC_POS_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_REV_THR_VAL_SHIFT) & MMC_POS_TRG_REV_THR_VAL_MASK) 889 #define MMC_POS_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_REV_THR_VAL_MASK) >> MMC_POS_TRG_REV_THR_VAL_SHIFT) 890 891 /* Bitfield definition for register: SPEED_TRG_CFG */ 892 /* 893 * COMP_TYPE (RW) 894 * 895 * 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) 896 */ 897 #define MMC_SPEED_TRG_CFG_COMP_TYPE_MASK (0x4U) 898 #define MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT (2U) 899 #define MMC_SPEED_TRG_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) 900 #define MMC_SPEED_TRG_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) >> MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) 901 902 /* 903 * EDGE (RW) 904 * 905 * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than 906 */ 907 #define MMC_SPEED_TRG_CFG_EDGE_MASK (0x2U) 908 #define MMC_SPEED_TRG_CFG_EDGE_SHIFT (1U) 909 #define MMC_SPEED_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EDGE_SHIFT) & MMC_SPEED_TRG_CFG_EDGE_MASK) 910 #define MMC_SPEED_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EDGE_MASK) >> MMC_SPEED_TRG_CFG_EDGE_SHIFT) 911 912 /* 913 * EN (RW) 914 * 915 * 1-trigger valid; 0-Trigger not valid 916 * Normally it means either the max pos speed, or the min negative speed. 917 */ 918 #define MMC_SPEED_TRG_CFG_EN_MASK (0x1U) 919 #define MMC_SPEED_TRG_CFG_EN_SHIFT (0U) 920 #define MMC_SPEED_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EN_SHIFT) & MMC_SPEED_TRG_CFG_EN_MASK) 921 #define MMC_SPEED_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EN_MASK) >> MMC_SPEED_TRG_CFG_EN_SHIFT) 922 923 /* Bitfield definition for register: SPEED_TRG_THR */ 924 /* 925 * VAL (RW) 926 * 927 * For speed trigger. 928 * continuous mode: fix<32, 19> 929 */ 930 #define MMC_SPEED_TRG_THR_VAL_MASK (0xFFFFFFFFUL) 931 #define MMC_SPEED_TRG_THR_VAL_SHIFT (0U) 932 #define MMC_SPEED_TRG_THR_VAL_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_THR_VAL_SHIFT) & MMC_SPEED_TRG_THR_VAL_MASK) 933 #define MMC_SPEED_TRG_THR_VAL_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_THR_VAL_MASK) >> MMC_SPEED_TRG_THR_VAL_SHIFT) 934 935 /* Bitfield definition for register of struct array COEF_TRG_CFG: ERR_THR */ 936 /* 937 * VAL (RW) 938 * 939 * ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) 940 * Note: ErrThr0>ErrThr1>ErrThr2 941 * ufix<31, 28> 942 */ 943 #define MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK (0xFFFFFFFFUL) 944 #define MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT (0U) 945 #define MMC_COEF_TRG_CFG_ERR_THR_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) 946 #define MMC_COEF_TRG_CFG_ERR_THR_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) >> MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) 947 948 /* Bitfield definition for register of struct array COEF_TRG_CFG: P */ 949 /* 950 * VAL (RW) 951 * 952 * P0_Coef, fix<32, 15> 953 */ 954 #define MMC_COEF_TRG_CFG_P_VAL_MASK (0xFFFFFFFFUL) 955 #define MMC_COEF_TRG_CFG_P_VAL_SHIFT (0U) 956 #define MMC_COEF_TRG_CFG_P_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_P_VAL_SHIFT) & MMC_COEF_TRG_CFG_P_VAL_MASK) 957 #define MMC_COEF_TRG_CFG_P_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_P_VAL_MASK) >> MMC_COEF_TRG_CFG_P_VAL_SHIFT) 958 959 /* Bitfield definition for register of struct array COEF_TRG_CFG: I */ 960 /* 961 * VAL (RW) 962 * 963 * I0_Coef, fix<32, 21> 964 */ 965 #define MMC_COEF_TRG_CFG_I_VAL_MASK (0xFFFFFFFFUL) 966 #define MMC_COEF_TRG_CFG_I_VAL_SHIFT (0U) 967 #define MMC_COEF_TRG_CFG_I_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_I_VAL_SHIFT) & MMC_COEF_TRG_CFG_I_VAL_MASK) 968 #define MMC_COEF_TRG_CFG_I_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_I_VAL_MASK) >> MMC_COEF_TRG_CFG_I_VAL_SHIFT) 969 970 /* Bitfield definition for register of struct array COEF_TRG_CFG: A */ 971 /* 972 * VAL (RW) 973 * 974 * A0_Coef，fix<32, 19> 975 */ 976 #define MMC_COEF_TRG_CFG_A_VAL_MASK (0xFFFFFFFFUL) 977 #define MMC_COEF_TRG_CFG_A_VAL_SHIFT (0U) 978 #define MMC_COEF_TRG_CFG_A_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_A_VAL_SHIFT) & MMC_COEF_TRG_CFG_A_VAL_MASK) 979 #define MMC_COEF_TRG_CFG_A_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_A_VAL_MASK) >> MMC_COEF_TRG_CFG_A_VAL_SHIFT) 980 981 /* Bitfield definition for register of struct array COEF_TRG_CFG: TIME */ 982 /* 983 * VAL (RW) 984 * 985 * CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> 986 */ 987 #define MMC_COEF_TRG_CFG_TIME_VAL_MASK (0xFFFFFFFFUL) 988 #define MMC_COEF_TRG_CFG_TIME_VAL_SHIFT (0U) 989 #define MMC_COEF_TRG_CFG_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) 990 #define MMC_COEF_TRG_CFG_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) >> MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) 991 992 /* Bitfield definition for register of struct array BR: BR_CTRL */ 993 /* 994 * SPEED_TRG_VALID_IE (RW) 995 * 996 * Interrupt Enable for SPEED_TRG_VALID 997 */ 998 #define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK (0x40000000UL) 999 #define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT (30U) 1000 #define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) 1001 #define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) 1002 1003 /* 1004 * POS_TRG_VALID_IE (RW) 1005 * 1006 * Interrupt Enable for POS_TRG_VALID 1007 */ 1008 #define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK (0x20000000UL) 1009 #define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT (29U) 1010 #define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) 1011 #define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) 1012 1013 /* 1014 * INI_POS_TRG_TYPE (RW) 1015 * 1016 * 0: Time Stamp in the configuration 1017 * 1: Risedge of In Trg[0] 1018 * 2: Risedge of In Trg[1] 1019 * 3: Risedge of out trg[0] 1020 * 4: Risedge of out trg[1] 1021 * 5: Risedge of self pos trigger 1022 * 6: Risedge of self speed trigger 1023 * Others: no function 1024 */ 1025 #define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK (0x3800000UL) 1026 #define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT (23U) 1027 #define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) 1028 #define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) 1029 1030 /* 1031 * INI_POS_CMD_MSK (RW) 1032 * 1033 * 1: change 1034 * 0: won't change 1035 * bit 3: for accel 1036 * bit 2: for speed 1037 * bit 1: for revolution 1038 * bit 0: for position 1039 */ 1040 #define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK (0x3C0000UL) 1041 #define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT (18U) 1042 #define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) 1043 #define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) 1044 1045 /* 1046 * INI_DELTA_POS_TRG_TYPE (RW) 1047 * 1048 * 0: Time Stamp in the configuration 1049 * 1: Risedge of In Trg[0] 1050 * 2: Risedge of In Trg[1] 1051 * 3: Risedge of out trg[0] 1052 * 4: Risedge of out trg[1] 1053 * 5: Risedge of self pos trigger 1054 * 6: Risedge of self speed trigger 1055 * Others: no function 1056 */ 1057 #define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK (0x1C000UL) 1058 #define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT (14U) 1059 #define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) 1060 #define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) 1061 1062 /* 1063 * INI_DELTA_POS_DONE_IE (RW) 1064 * 1065 * Interrupt Enable for INI_DELTA_POS_DONE 1066 */ 1067 #define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK (0x2000U) 1068 #define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT (13U) 1069 #define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) 1070 #define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) 1071 1072 /* 1073 * INI_DELTA_POS_CMD_MSK (RW) 1074 * 1075 * 1: change 1076 * 0: won't change 1077 * bit 3: for delta accel 1078 * bit 2: for delta speed 1079 * bit 1: for delta revolution 1080 * bit 0: for delta position 1081 */ 1082 #define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK (0x1E00U) 1083 #define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT (9U) 1084 #define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) 1085 #define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) 1086 1087 /* 1088 * INI_DELTA_POS_REQ (RW) 1089 * 1090 * 1: Command to reload the delta pos. Auto clear 1091 * 0: 1092 */ 1093 #define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK (0x100U) 1094 #define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT (8U) 1095 #define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) 1096 #define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) 1097 1098 /* 1099 * OPEN_LOOP_MODE (RW) 1100 * 1101 * 1: in open loop mode 1102 * 0: not in open loop mode 1103 */ 1104 #define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK (0x80U) 1105 #define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT (7U) 1106 #define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) 1107 #define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) >> MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) 1108 1109 /* 1110 * PRED_MODE (RW) 1111 * 1112 * 1:continuously repeat pred, 1113 * 0:cal the pred based on a definite time-stamp offset, 1114 * 2:programed one-shot prediction mode 1115 */ 1116 #define MMC_BR_BR_CTRL_PRED_MODE_MASK (0x30U) 1117 #define MMC_BR_BR_CTRL_PRED_MODE_SHIFT (4U) 1118 #define MMC_BR_BR_CTRL_PRED_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_PRED_MODE_SHIFT) & MMC_BR_BR_CTRL_PRED_MODE_MASK) 1119 #define MMC_BR_BR_CTRL_PRED_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_PRED_MODE_MASK) >> MMC_BR_BR_CTRL_PRED_MODE_SHIFT) 1120 1121 /* 1122 * NF_TRG_TYPE (RW) 1123 * 1124 * 1. Each non-first trigger by external trigger pin 1125 * 0. Each non-first trigger by the timer 1126 */ 1127 #define MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK (0x4U) 1128 #define MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT (2U) 1129 #define MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) 1130 #define MMC_BR_BR_CTRL_NF_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) 1131 1132 /* 1133 * F_TRG_TYPE (RW) 1134 * 1135 * 1. First trigger by external trigger pin 1136 * 0. First trigger by the timer 1137 * When in CR[MANUAL_IO]=1 mode, it is the prediction trigger 1138 */ 1139 #define MMC_BR_BR_CTRL_F_TRG_TYPE_MASK (0x2U) 1140 #define MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT (1U) 1141 #define MMC_BR_BR_CTRL_F_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) 1142 #define MMC_BR_BR_CTRL_F_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) 1143 1144 /* 1145 * BR_EN (RW) 1146 * 1147 * Branch Enable 1148 */ 1149 #define MMC_BR_BR_CTRL_BR_EN_MASK (0x1U) 1150 #define MMC_BR_BR_CTRL_BR_EN_SHIFT (0U) 1151 #define MMC_BR_BR_CTRL_BR_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_BR_EN_SHIFT) & MMC_BR_BR_CTRL_BR_EN_MASK) 1152 #define MMC_BR_BR_CTRL_BR_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_BR_EN_MASK) >> MMC_BR_BR_CTRL_BR_EN_SHIFT) 1153 1154 /* Bitfield definition for register of struct array BR: BR_TIMEOFF */ 1155 /* 1156 * VAL (RW) 1157 * 1158 * ufix<32, 0> time offset incycles from the trigger time 1159 */ 1160 #define MMC_BR_BR_TIMEOFF_VAL_MASK (0xFFFFFFFFUL) 1161 #define MMC_BR_BR_TIMEOFF_VAL_SHIFT (0U) 1162 #define MMC_BR_BR_TIMEOFF_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TIMEOFF_VAL_SHIFT) & MMC_BR_BR_TIMEOFF_VAL_MASK) 1163 #define MMC_BR_BR_TIMEOFF_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TIMEOFF_VAL_MASK) >> MMC_BR_BR_TIMEOFF_VAL_SHIFT) 1164 1165 /* Bitfield definition for register of struct array BR: BR_TRG_PERIOD */ 1166 /* 1167 * VAL (RW) 1168 * 1169 * uifx<32, 0>, time offset incycles between each trigger time 1170 */ 1171 #define MMC_BR_BR_TRG_PERIOD_VAL_MASK (0xFFFFFFFFUL) 1172 #define MMC_BR_BR_TRG_PERIOD_VAL_SHIFT (0U) 1173 #define MMC_BR_BR_TRG_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) 1174 #define MMC_BR_BR_TRG_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) >> MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) 1175 1176 /* Bitfield definition for register of struct array BR: BR_TRG_F_TIME */ 1177 /* 1178 * VAL (RW) 1179 * 1180 * uifx<32, 0> the time for the first trigger 1181 */ 1182 #define MMC_BR_BR_TRG_F_TIME_VAL_MASK (0xFFFFFFFFUL) 1183 #define MMC_BR_BR_TRG_F_TIME_VAL_SHIFT (0U) 1184 #define MMC_BR_BR_TRG_F_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) 1185 #define MMC_BR_BR_TRG_F_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) >> MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) 1186 1187 /* Bitfield definition for register of struct array BR: BR_ST */ 1188 /* 1189 * OPEN_LOOP_ST (RO) 1190 * 1191 * 1：in open loop mode 1192 * 0：in closed loop mode 1193 */ 1194 #define MMC_BR_BR_ST_OPEN_LOOP_ST_MASK (0x400U) 1195 #define MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT (10U) 1196 #define MMC_BR_BR_ST_OPEN_LOOP_ST_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_OPEN_LOOP_ST_MASK) >> MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT) 1197 1198 /* 1199 * SPEED_TRG_VLD (W1C) 1200 * 1201 * 1：self speed trigger event found 1202 * 0：self speed trigger event not found yet 1203 */ 1204 #define MMC_BR_BR_ST_SPEED_TRG_VLD_MASK (0x200U) 1205 #define MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT (9U) 1206 #define MMC_BR_BR_ST_SPEED_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) 1207 #define MMC_BR_BR_ST_SPEED_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) >> MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) 1208 1209 /* 1210 * POS_TRG_VLD (W1C) 1211 * 1212 * 1：self position trigger event found 1213 * 0：self position trigger event not found yet 1214 */ 1215 #define MMC_BR_BR_ST_POS_TRG_VLD_MASK (0x100U) 1216 #define MMC_BR_BR_ST_POS_TRG_VLD_SHIFT (8U) 1217 #define MMC_BR_BR_ST_POS_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) 1218 #define MMC_BR_BR_ST_POS_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) >> MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) 1219 1220 /* 1221 * INI_DELTA_POS_DONE (W1C) 1222 * 1223 * 1: the initialization of delta position command is done 1224 * 0: the initialization of delta position command is not done 1225 */ 1226 #define MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK (0x40U) 1227 #define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT (6U) 1228 #define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) 1229 #define MMC_BR_BR_ST_INI_DELTA_POS_DONE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) >> MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) 1230 1231 /* 1232 * IDLE (RO) 1233 * 1234 * 1: The prediction module is idle. 1235 * 0: The prediction module is not idle. 1236 */ 1237 #define MMC_BR_BR_ST_IDLE_MASK (0x20U) 1238 #define MMC_BR_BR_ST_IDLE_SHIFT (5U) 1239 #define MMC_BR_BR_ST_IDLE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_IDLE_MASK) >> MMC_BR_BR_ST_IDLE_SHIFT) 1240 1241 /* 1242 * ERR_ID (RO) 1243 * 1244 * The module's error ID output 1245 */ 1246 #define MMC_BR_BR_ST_ERR_ID_MASK (0xFU) 1247 #define MMC_BR_BR_ST_ERR_ID_SHIFT (0U) 1248 #define MMC_BR_BR_ST_ERR_ID_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_ERR_ID_MASK) >> MMC_BR_BR_ST_ERR_ID_SHIFT) 1249 1250 /* Bitfield definition for register of struct array BR: BR_TRG_POS_CFG */ 1251 /* 1252 * EDGE (RW) 1253 * 1254 * bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than 1255 */ 1256 #define MMC_BR_BR_TRG_POS_CFG_EDGE_MASK (0x2U) 1257 #define MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT (1U) 1258 #define MMC_BR_BR_TRG_POS_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) 1259 #define MMC_BR_BR_TRG_POS_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) >> MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) 1260 1261 /* 1262 * EN (RW) 1263 * 1264 * 1-trigger valid; 0-Trigger not valid 1265 */ 1266 #define MMC_BR_BR_TRG_POS_CFG_EN_MASK (0x1U) 1267 #define MMC_BR_BR_TRG_POS_CFG_EN_SHIFT (0U) 1268 #define MMC_BR_BR_TRG_POS_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) 1269 #define MMC_BR_BR_TRG_POS_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) >> MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) 1270 1271 /* Bitfield definition for register of struct array BR: BR_TRG_POS_THR */ 1272 /* 1273 * VAL (RW) 1274 * 1275 * For pos out trigger (pos). 1276 * ufix<32, 32> 1277 */ 1278 #define MMC_BR_BR_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) 1279 #define MMC_BR_BR_TRG_POS_THR_VAL_SHIFT (0U) 1280 #define MMC_BR_BR_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) 1281 #define MMC_BR_BR_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) >> MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) 1282 1283 /* Bitfield definition for register of struct array BR: BR_TRG_REV_THR */ 1284 /* 1285 * VAL (RW) 1286 * 1287 * For pos out trigger (rev) 1288 * ufix<32, 0> 1289 */ 1290 #define MMC_BR_BR_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) 1291 #define MMC_BR_BR_TRG_REV_THR_VAL_SHIFT (0U) 1292 #define MMC_BR_BR_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) 1293 #define MMC_BR_BR_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) >> MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) 1294 1295 /* Bitfield definition for register of struct array BR: BR_TRG_SPEED_CFG */ 1296 /* 1297 * COMP_TYPE (RW) 1298 * 1299 * Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) 1300 */ 1301 #define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK (0x4U) 1302 #define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT (2U) 1303 #define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) 1304 #define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) 1305 1306 /* 1307 * EDGE_SEL (RW) 1308 * 1309 * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than 1310 */ 1311 #define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK (0x2U) 1312 #define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT (1U) 1313 #define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) 1314 #define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) 1315 1316 /* 1317 * EN (RW) 1318 * 1319 * 1-trigger valid; 0-Trigger not valid 1320 * Normally it means either the max pos speed, or the min negative speed. 1321 */ 1322 #define MMC_BR_BR_TRG_SPEED_CFG_EN_MASK (0x1U) 1323 #define MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT (0U) 1324 #define MMC_BR_BR_TRG_SPEED_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) 1325 #define MMC_BR_BR_TRG_SPEED_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) 1326 1327 /* Bitfield definition for register of struct array BR: BR_TRG_SPEED_THR */ 1328 /* 1329 * VAL (RW) 1330 * 1331 * For speed trigger. 1332 * continuous mode: fix<32, 19> 1333 */ 1334 #define MMC_BR_BR_TRG_SPEED_THR_VAL_MASK (0xFFFFFFFFUL) 1335 #define MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT (0U) 1336 #define MMC_BR_BR_TRG_SPEED_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) 1337 #define MMC_BR_BR_TRG_SPEED_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) >> MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) 1338 1339 /* Bitfield definition for register of struct array BR: BR_INI_POS_TIME */ 1340 /* 1341 * VAL (RW) 1342 * 1343 * indicate the time to change the values. 1344 * 0: instant change 1345 */ 1346 #define MMC_BR_BR_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) 1347 #define MMC_BR_BR_INI_POS_TIME_VAL_SHIFT (0U) 1348 #define MMC_BR_BR_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) 1349 #define MMC_BR_BR_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) 1350 1351 /* Bitfield definition for register of struct array BR: BR_INI_POS */ 1352 /* 1353 * VAL (RW) 1354 * 1355 * the value 1356 * ufix<32, 32> 1357 */ 1358 #define MMC_BR_BR_INI_POS_VAL_MASK (0xFFFFFFFFUL) 1359 #define MMC_BR_BR_INI_POS_VAL_SHIFT (0U) 1360 #define MMC_BR_BR_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_VAL_SHIFT) & MMC_BR_BR_INI_POS_VAL_MASK) 1361 #define MMC_BR_BR_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_VAL_MASK) >> MMC_BR_BR_INI_POS_VAL_SHIFT) 1362 1363 /* Bitfield definition for register of struct array BR: BR_INI_REV */ 1364 /* 1365 * VAL (RW) 1366 * 1367 * the value 1368 * ufix<32, 0> 1369 */ 1370 #define MMC_BR_BR_INI_REV_VAL_MASK (0xFFFFFFFFUL) 1371 #define MMC_BR_BR_INI_REV_VAL_SHIFT (0U) 1372 #define MMC_BR_BR_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_REV_VAL_SHIFT) & MMC_BR_BR_INI_REV_VAL_MASK) 1373 #define MMC_BR_BR_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_REV_VAL_MASK) >> MMC_BR_BR_INI_REV_VAL_SHIFT) 1374 1375 /* Bitfield definition for register of struct array BR: BR_INI_SPEED */ 1376 /* 1377 * VAL (RW) 1378 * 1379 * the value 1380 * fix<32, 19> 1381 */ 1382 #define MMC_BR_BR_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) 1383 #define MMC_BR_BR_INI_SPEED_VAL_SHIFT (0U) 1384 #define MMC_BR_BR_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_SPEED_VAL_MASK) 1385 #define MMC_BR_BR_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_SPEED_VAL_MASK) >> MMC_BR_BR_INI_SPEED_VAL_SHIFT) 1386 1387 /* Bitfield definition for register of struct array BR: BR_INI_ACCEL */ 1388 /* 1389 * VAL (RW) 1390 * 1391 * the value 1392 * continuous mode: fix<32, 19> 1393 */ 1394 #define MMC_BR_BR_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) 1395 #define MMC_BR_BR_INI_ACCEL_VAL_SHIFT (0U) 1396 #define MMC_BR_BR_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_ACCEL_VAL_MASK) 1397 #define MMC_BR_BR_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_ACCEL_VAL_SHIFT) 1398 1399 /* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS_TIME */ 1400 /* 1401 * VAL (RW) 1402 * 1403 * indicate the time to change the values. 1404 * 0: instant change 1405 */ 1406 #define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) 1407 #define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT (0U) 1408 #define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) 1409 #define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) 1410 1411 /* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS */ 1412 /* 1413 * VAL (RW) 1414 * 1415 * the value 1416 * continuous mode: ufix<32, 32> 1417 */ 1418 #define MMC_BR_BR_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) 1419 #define MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT (0U) 1420 #define MMC_BR_BR_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) 1421 #define MMC_BR_BR_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) 1422 1423 /* Bitfield definition for register of struct array BR: BR_INI_DELTA_REV */ 1424 /* 1425 * VAL (RW) 1426 * 1427 * the value 1428 * continuous mode: fix<32, 0> 1429 */ 1430 #define MMC_BR_BR_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) 1431 #define MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT (0U) 1432 #define MMC_BR_BR_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) 1433 #define MMC_BR_BR_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) >> MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) 1434 1435 /* Bitfield definition for register of struct array BR: BR_INI_DELTA_SPEED */ 1436 /* 1437 * VAL (RW) 1438 * 1439 * the value 1440 * continuous mode: fix<32, 19> 1441 */ 1442 #define MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) 1443 #define MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT (0U) 1444 #define MMC_BR_BR_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) 1445 #define MMC_BR_BR_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) >> MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) 1446 1447 /* Bitfield definition for register of struct array BR: BR_INI_DELTA_ACCEL */ 1448 /* 1449 * VAL (RW) 1450 * 1451 * the value 1452 * continuous mode: fix<32, 19> 1453 */ 1454 #define MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) 1455 #define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT (0U) 1456 #define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) 1457 #define MMC_BR_BR_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) 1458 1459 /* Bitfield definition for register of struct array BR: BR_CUR_POS_TIME */ 1460 /* 1461 * VAL (RO) 1462 * 1463 * the value 1464 */ 1465 #define MMC_BR_BR_CUR_POS_TIME_VAL_MASK (0xFFFFFFFFUL) 1466 #define MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT (0U) 1467 #define MMC_BR_BR_CUR_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_TIME_VAL_MASK) >> MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT) 1468 1469 /* Bitfield definition for register of struct array BR: BR_CUR_POS */ 1470 /* 1471 * VAL (RO) 1472 * 1473 * the value 1474 */ 1475 #define MMC_BR_BR_CUR_POS_VAL_MASK (0xFFFFFFFFUL) 1476 #define MMC_BR_BR_CUR_POS_VAL_SHIFT (0U) 1477 #define MMC_BR_BR_CUR_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_VAL_MASK) >> MMC_BR_BR_CUR_POS_VAL_SHIFT) 1478 1479 /* Bitfield definition for register of struct array BR: BR_CUR_REV */ 1480 /* 1481 * VAL (RO) 1482 * 1483 * the value 1484 */ 1485 #define MMC_BR_BR_CUR_REV_VAL_MASK (0xFFFFFFFFUL) 1486 #define MMC_BR_BR_CUR_REV_VAL_SHIFT (0U) 1487 #define MMC_BR_BR_CUR_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_REV_VAL_MASK) >> MMC_BR_BR_CUR_REV_VAL_SHIFT) 1488 1489 /* Bitfield definition for register of struct array BR: BR_CUR_SPEED */ 1490 /* 1491 * VAL (RO) 1492 * 1493 * the value 1494 */ 1495 #define MMC_BR_BR_CUR_SPEED_VAL_MASK (0xFFFFFFFFUL) 1496 #define MMC_BR_BR_CUR_SPEED_VAL_SHIFT (0U) 1497 #define MMC_BR_BR_CUR_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_SPEED_VAL_MASK) >> MMC_BR_BR_CUR_SPEED_VAL_SHIFT) 1498 1499 /* Bitfield definition for register of struct array BR: BR_CUR_ACCEL */ 1500 /* 1501 * VAL (RO) 1502 * 1503 * the value 1504 */ 1505 #define MMC_BR_BR_CUR_ACCEL_VAL_MASK (0xFFFFFFFFUL) 1506 #define MMC_BR_BR_CUR_ACCEL_VAL_SHIFT (0U) 1507 #define MMC_BR_BR_CUR_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_ACCEL_VAL_MASK) >> MMC_BR_BR_CUR_ACCEL_VAL_SHIFT) 1508 1509 /* Bitfield definition for register: BK0_TIMESTAMP */ 1510 /* 1511 * VAL (RO) 1512 * 1513 * the value 1514 */ 1515 #define MMC_BK0_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) 1516 #define MMC_BK0_TIMESTAMP_VAL_SHIFT (0U) 1517 #define MMC_BK0_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_TIMESTAMP_VAL_MASK) >> MMC_BK0_TIMESTAMP_VAL_SHIFT) 1518 1519 /* Bitfield definition for register: BK0_POSITION */ 1520 /* 1521 * VAL (RO) 1522 * 1523 * the value 1524 */ 1525 #define MMC_BK0_POSITION_VAL_MASK (0xFFFFFFFFUL) 1526 #define MMC_BK0_POSITION_VAL_SHIFT (0U) 1527 #define MMC_BK0_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_POSITION_VAL_MASK) >> MMC_BK0_POSITION_VAL_SHIFT) 1528 1529 /* Bitfield definition for register: BK0_REVOLUTION */ 1530 /* 1531 * VAL (RO) 1532 * 1533 * the value 1534 */ 1535 #define MMC_BK0_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) 1536 #define MMC_BK0_REVOLUTION_VAL_SHIFT (0U) 1537 #define MMC_BK0_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_REVOLUTION_VAL_MASK) >> MMC_BK0_REVOLUTION_VAL_SHIFT) 1538 1539 /* Bitfield definition for register: BK0_SPEED */ 1540 /* 1541 * VAL (RO) 1542 * 1543 * the value 1544 */ 1545 #define MMC_BK0_SPEED_VAL_MASK (0xFFFFFFFFUL) 1546 #define MMC_BK0_SPEED_VAL_SHIFT (0U) 1547 #define MMC_BK0_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_SPEED_VAL_MASK) >> MMC_BK0_SPEED_VAL_SHIFT) 1548 1549 /* Bitfield definition for register: BK0_ACCELERATOR */ 1550 /* 1551 * VAL (RO) 1552 * 1553 * the value 1554 */ 1555 #define MMC_BK0_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) 1556 #define MMC_BK0_ACCELERATOR_VAL_SHIFT (0U) 1557 #define MMC_BK0_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_ACCELERATOR_VAL_MASK) >> MMC_BK0_ACCELERATOR_VAL_SHIFT) 1558 1559 /* Bitfield definition for register: BK1_TIMESTAMP */ 1560 /* 1561 * VAL (RO) 1562 * 1563 * the value 1564 */ 1565 #define MMC_BK1_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) 1566 #define MMC_BK1_TIMESTAMP_VAL_SHIFT (0U) 1567 #define MMC_BK1_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_TIMESTAMP_VAL_MASK) >> MMC_BK1_TIMESTAMP_VAL_SHIFT) 1568 1569 /* Bitfield definition for register: BK1_POSITION */ 1570 /* 1571 * VAL (RO) 1572 * 1573 * the value 1574 */ 1575 #define MMC_BK1_POSITION_VAL_MASK (0xFFFFFFFFUL) 1576 #define MMC_BK1_POSITION_VAL_SHIFT (0U) 1577 #define MMC_BK1_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_POSITION_VAL_MASK) >> MMC_BK1_POSITION_VAL_SHIFT) 1578 1579 /* Bitfield definition for register: BK1_REVOLUTION */ 1580 /* 1581 * VAL (RO) 1582 * 1583 * the value 1584 */ 1585 #define MMC_BK1_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) 1586 #define MMC_BK1_REVOLUTION_VAL_SHIFT (0U) 1587 #define MMC_BK1_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_REVOLUTION_VAL_MASK) >> MMC_BK1_REVOLUTION_VAL_SHIFT) 1588 1589 /* Bitfield definition for register: BK1_SPEED */ 1590 /* 1591 * VAL (RO) 1592 * 1593 * the value 1594 */ 1595 #define MMC_BK1_SPEED_VAL_MASK (0xFFFFFFFFUL) 1596 #define MMC_BK1_SPEED_VAL_SHIFT (0U) 1597 #define MMC_BK1_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_SPEED_VAL_MASK) >> MMC_BK1_SPEED_VAL_SHIFT) 1598 1599 /* Bitfield definition for register: BK1_ACCELERATOR */ 1600 /* 1601 * VAL (RO) 1602 * 1603 * the value 1604 */ 1605 #define MMC_BK1_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) 1606 #define MMC_BK1_ACCELERATOR_VAL_SHIFT (0U) 1607 #define MMC_BK1_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_ACCELERATOR_VAL_MASK) >> MMC_BK1_ACCELERATOR_VAL_SHIFT) 1608 1609 1610 1611 /* COEF_TRG_CFG register group index macro definition */ 1612 #define MMC_COEF_TRG_CFG_0 (0UL) 1613 #define MMC_COEF_TRG_CFG_1 (1UL) 1614 #define MMC_COEF_TRG_CFG_2 (2UL) 1615 1616 /* BR register group index macro definition */ 1617 #define MMC_BR_0 (0UL) 1618 #define MMC_BR_1 (1UL) 1619 1620 1621 #endif /* HPM_MMC_H */ 1622