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Searched defs:CONTROL (Results 1 – 23 of 23) sorted by relevance

/device/soc/hpmicro/sdk/hpm_sdk/soc/ip/
Dhpm_bmon_regs.h14 __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ member
Dhpm_pmon_regs.h14 __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ member
Dhpm_mon_regs.h14 __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ member
Dhpm_tamp_regs.h14 __RW uint32_t CONTROL; /* 0x0: Tamper n control */ member
Dhpm_lin_regs.h14 __RW uint32_t CONTROL; /* 0x20: control register */ member
/device/board/unionman/unionpi_tiger/kernel/drivers/media/drivers/stream_input/amports/
Dstreambuf_reg.h30 #define CONTROL 4 macro
/device/soc/chipsea/cst85/liteos_m/sdk/bsp/arch/boot/
Dfault_handler.c69 uint32_t CONTROL; member
/device/soc/st/stm32f407zg/uniproton/board/common/STM32F4xx_StdPeriph_Driver/inc/
Dstm32f4xx_usart.h185 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
Dstm32f4xx_sdio.h178 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ argument
/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/
Dreg_dma.h33 __IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register member
Dhal_trace.c172 uint32_t CONTROL; member
193 uint8_t CONTROL; member
/device/soc/st/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/
Dstm32f4xx_hal_uart.h818 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ argument
Dstm32f4xx_ll_sdmmc.h382 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) |… argument
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM5301/
Dhpm_sysctl_regs.h45 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
60 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/
Dhpm_sysctl_regs.h44 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
60 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM5361/
Dhpm_sysctl_regs.h45 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
60 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6880/
Dhpm_sysctl_regs.h44 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
58 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6280/
Dhpm_sysctl_regs.h50 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
65 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/
Dhpm_sysctl_regs.h50 __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ member
64 __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ member
/device/soc/asrmicro/asr582x/liteos_m/sdk/drivers/driver/inc/
Dduet.h653 __IO uint32_t CONTROL; member
694 __IO uint32_t CONTROL; member
/device/soc/st/common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/
Dcore_ca.h823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register member
/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/inc/ca/
Dcore_ca.h900 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register member
/device/soc/rockchip/rk2206/hardware/lib/CMSIS/Device/RK2206/Include/
Drk2206.h928 __IO uint32_t CONTROL; /* Address Offset: 0x0000 */ member