1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_CRC_H 10 #define HPM_CRC_H 11 12 typedef struct { 13 struct { 14 __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ 15 __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ 16 __RW uint32_t POLY; /* 0x8: chn poly */ 17 __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ 18 __RW uint32_t XOROUT; /* 0x10: chn xorout */ 19 __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ 20 __RW uint32_t DATA; /* 0x18: chn data */ 21 __RW uint32_t RESULT; /* 0x1C: chn result */ 22 __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ 23 } CHN[8]; 24 } CRC_Type; 25 26 27 /* Bitfield definition for register of struct array CHN: PRE_SET */ 28 /* 29 * PRE_SET (RW) 30 * 31 * 0: no pre set 32 * 1: CRC32 33 * 2: CRC32-AUTOSAR 34 * 3: CRC16-CCITT 35 * 4: CRC16-XMODEM 36 * 5: CRC16-MODBUS 37 * 1: CRC32 38 * 2: CRC32-autosar 39 * 3: CRC16-ccitt 40 * 4: CRC16-xmodem 41 * 5: CRC16-modbus 42 * 6: crc16_dnp 43 * 7: crc16_x25 44 * 8: crc16_usb 45 * 9: crc16_maxim 46 * 10: crc16_ibm 47 * 11: crc8_maxim 48 * 12: crc8_rohc 49 * 13: crc8_itu 50 * 14: crc8 51 * 15: crc5_usb 52 */ 53 #define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) 54 #define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) 55 #define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) 56 #define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) 57 58 /* Bitfield definition for register of struct array CHN: CLR */ 59 /* 60 * CLR (RW) 61 * 62 * write 1 to clr crc setting and result for its channel. 63 * always read 0. 64 */ 65 #define CRC_CHN_CLR_CLR_MASK (0x1U) 66 #define CRC_CHN_CLR_CLR_SHIFT (0U) 67 #define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) 68 #define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) 69 70 /* Bitfield definition for register of struct array CHN: POLY */ 71 /* 72 * POLY (RW) 73 * 74 * poly setting 75 */ 76 #define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) 77 #define CRC_CHN_POLY_POLY_SHIFT (0U) 78 #define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) 79 #define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) 80 81 /* Bitfield definition for register of struct array CHN: INIT_DATA */ 82 /* 83 * INIT_DATA (RW) 84 * 85 * initial data of CRC 86 */ 87 #define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) 88 #define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) 89 #define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) 90 #define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) 91 92 /* Bitfield definition for register of struct array CHN: XOROUT */ 93 /* 94 * XOROUT (RW) 95 * 96 * XOR for CRC result 97 */ 98 #define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) 99 #define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) 100 #define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) 101 #define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) 102 103 /* Bitfield definition for register of struct array CHN: MISC_SETTING */ 104 /* 105 * BYTE_REV (RW) 106 * 107 * 0: no wrap input byte order 108 * 1: wrap input byte order 109 */ 110 #define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) 111 #define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) 112 #define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) 113 #define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) 114 115 /* 116 * REV_OUT (RW) 117 * 118 * 0: no wrap output bit order 119 * 1: wrap output bit order 120 */ 121 #define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) 122 #define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) 123 #define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) 124 #define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) 125 126 /* 127 * REV_IN (RW) 128 * 129 * 0: no wrap input bit order 130 * 1: wrap input bit order 131 */ 132 #define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) 133 #define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) 134 #define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) 135 #define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) 136 137 /* 138 * POLY_WIDTH (RW) 139 * 140 * crc data length 141 */ 142 #define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) 143 #define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) 144 #define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) 145 #define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) 146 147 /* Bitfield definition for register of struct array CHN: DATA */ 148 /* 149 * DATA (RW) 150 * 151 * data for crc 152 */ 153 #define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) 154 #define CRC_CHN_DATA_DATA_SHIFT (0U) 155 #define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) 156 #define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) 157 158 /* Bitfield definition for register of struct array CHN: RESULT */ 159 /* 160 * RESULT (RW) 161 * 162 * crc result 163 */ 164 #define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) 165 #define CRC_CHN_RESULT_RESULT_SHIFT (0U) 166 #define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) 167 #define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) 168 169 170 171 /* CHN register group index macro definition */ 172 #define CRC_CHN_0 (0UL) 173 #define CRC_CHN_1 (1UL) 174 #define CRC_CHN_2 (2UL) 175 #define CRC_CHN_3 (3UL) 176 #define CRC_CHN_4 (4UL) 177 #define CRC_CHN_5 (5UL) 178 #define CRC_CHN_6 (6UL) 179 #define CRC_CHN_7 (7UL) 180 181 182 #endif /* HPM_CRC_H */ 183