1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/top_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef __CSIC__TOP__REG__I__H__ 18 #define __CSIC__TOP__REG__I__H__ 19 20 /* 21 * Detail information of registers 22 */ 23 /* 24 *CSIC TOP registers 25 */ 26 #define CSIC_TOP_EN_REG_OFF 0X000 27 #define CSIC_TOP_EN 0 28 #define CSIC_TOP_EN_MASK (0X1 << CSIC_TOP_EN) 29 #define CSIC_BIST_MODE_EN 2 30 #define CSIC_BIST_MODE_EN_MASK (0X1 << CSIC_BIST_MODE_EN) 31 #define CSIC_ISP_BRIDGE_EN 3 32 #define CSIC_ISP_BRIDGE_EN_MASK (0X1 << CSIC_ISP_BRIDGE_EN) 33 #define CSIC_SRAM_PWDN 8 34 #define CSIC_SRAM_PWDN_MASK (0X1 << CSIC_SRAM_PWDN) 35 #define CSIC_VER_EN 31 36 #define CSIC_VER_EN_MASK (0X1 << CSIC_VER_EN) 37 38 #define CSIC_PTN_GEN_EN_REG_OFF 0X004 39 #define CSIC_PTN_GEN_EN 0 40 #define CSIC_PTN_GEN_EN_MASK (0X1 << CSIC_PTN_GEN_EN) 41 #define CSIC_PTN_GEN_START 4 42 #define CSIC_PTN_GEN_START_MASK (0X1 << CSIC_PTN_GEN_START) 43 #define CSIC_PTN_GEN_CYCLE 16 44 #define CSIC_PTN_GEN_CYCLE_MASK (0XFF << CSIC_PTN_GEN_CYCLE) 45 46 #define CSIC_PTN_CTRL_REG_OFF 0X008 47 #define CSIC_PTN_CLK_DIV 8 48 #define CSIC_PTN_CLK_DIV_MASK (0X3 << CSIC_PTN_CLK_DIV) 49 #define CSIC_PTN_MODE 16 50 #define CSIC_PTN_MODE_MASK (0XF << CSIC_PTN_MODE) 51 #define CSIC_PTN_DATA_WIDTH 20 52 #define CSIC_PTN_DATA_WIDTH_MASK (0X3 << CSIC_PTN_DATA_WIDTH) 53 #define CSIC_PTN_PORT_SEL 24 54 #define CSIC_PTN_PORT_SEL_MASK (0X7 << CSIC_PTN_PORT_SEL) 55 56 #define CSIC_PTN_LEN_REG_OFF 0X020 57 #define CSIC_PTN_ADDR_REG_OFF 0X024 58 #define CSIC_PTN_SIZE_REG_OFF 0X028 59 #define CSIC_PTN_WIDTH 0 60 #define CSIC_PTN_WIDTH_MASK (0X1FFF << CSIC_PTN_WIDTH) 61 #define CSIC_PTN_HEIGHT 16 62 #define CSIC_PTN_HEIGHT_MASK (0X1FFF << CSIC_PTN_HEIGHT) 63 64 #if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1) 65 #define CSIC_ISP0_IN0_REG_OFF 0X030 66 #define CSIC_ISP0_IN1_REG_OFF 0X034 67 #define CSIC_ISP0_IN2_REG_OFF 0X038 68 #define CSIC_ISP0_IN3_REG_OFF 0X03C 69 70 #define CSIC_ISP1_IN0_REG_OFF 0X040 71 #define CSIC_ISP1_IN1_REG_OFF 0X044 72 #define CSIC_ISP1_IN2_REG_OFF 0X048 73 #define CSIC_ISP1_IN3_REG_OFF 0X04C 74 75 #define CSIC_VIPP0_IN_REG_OFF 0X060 76 #define CSIC_VIPP1_IN_REG_OFF 0X064 77 #define CSIC_VIPP2_IN_REG_OFF 0X068 78 #define CSIC_VIPP3_IN_REG_OFF 0X06C 79 80 #define CSIC_FEATURE_REG_OFF 0X070 81 #define CSIC_VER_REG_OFF 0X074 82 83 #else 84 85 #define CSIC_ISP0_IN0_REG_OFF 0X030 86 #define CSIC_ISP0_IN1_REG_OFF 0X034 87 #define CSIC_ISP0_IN2_REG_OFF 0X038 88 #define CSIC_ISP0_IN3_REG_OFF 0X03C 89 90 #define CSIC_ISP1_IN0_REG_OFF 0X040 91 #define CSIC_ISP1_IN1_REG_OFF 0X044 92 #define CSIC_ISP1_IN2_REG_OFF 0X048 93 #define CSIC_ISP1_IN3_REG_OFF 0X04C 94 95 #define CSIC_ISP2_IN0_REG_OFF 0X050 96 #define CSIC_ISP2_IN1_REG_OFF 0X054 97 #define CSIC_ISP2_IN2_REG_OFF 0X058 98 #define CSIC_ISP2_IN3_REG_OFF 0X05C 99 100 #define CSIC_ISP3_IN0_REG_OFF 0X060 101 #define CSIC_ISP3_IN1_REG_OFF 0X064 102 #define CSIC_ISP3_IN2_REG_OFF 0X068 103 #define CSIC_ISP3_IN3_REG_OFF 0X06C 104 105 #define CSIC_VIPP0_IN_REG_OFF 0X0A0 106 #define CSIC_VIPP1_IN_REG_OFF 0X0A4 107 #define CSIC_VIPP2_IN_REG_OFF 0X0A8 108 #define CSIC_VIPP3_IN_REG_OFF 0X0AC 109 #define CSIC_VIPP4_IN_REG_OFF 0X0B0 110 #define CSIC_VIPP5_IN_REG_OFF 0X0B4 111 #define CSIC_VIPP6_IN_REG_OFF 0X0B8 112 #define CSIC_VIPP7_IN_REG_OFF 0X0BC 113 114 #if defined CONFIG_ARCH_SUN8IW15P1 || defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW17P1 || defined CONFIG_ARCH_SUN50IW9P1 115 #define CSIC_FEATURE_REG_OFF 0X0F0 116 #define CSIC_VER_REG_OFF 0X0F4 117 #else 118 #define CSIC_MBUS_REQ_MAX 0x0F0 119 #define MCSI_MEM_REQ_MAX 0 120 #define MCSI_MEM_REQ_MAX_MASK (0X1F << MCSI_MEM_REQ_MAX) 121 #define MCSI_MEM_1_REQ_MAX 8 122 #define MCSI_MEM_1_REQ_MAX_MASK (0X1F << MCSI_MEM_1_REQ_MAX) 123 #define MISP_MEM_REQ_MAX 16 124 #define MISP_MEM_REQ_MAX_MASK (0X1F << MISP_MEM_REQ_MAX) 125 126 #define CSIC_FEATURE_REG_OFF 0X1F0 127 #define CSIC_VER_REG_OFF 0X1F4 128 #endif 129 #endif 130 131 #define CSIC_FEATURE_RES0 0 132 #define CSIC_FEATURE_RES0_MASK (0XFF << CSIC_FEATURE_RES0) 133 #define CSIC_DMA_NUM 8 134 #define CSIC_DMA_NUM_MASK (0XF << CSIC_DMA_NUM) 135 #define CSIC_VIPP_NUM 12 136 #define CSIC_VIPP_NUM_MASK (0XF << CSIC_VIPP_NUM) 137 #define CSIC_ISP_NUM 16 138 #define CSIC_ISP_NUM_MASK (0XF << CSIC_ISP_NUM) 139 #define CSIC_NCSI_NUM 20 140 #define CSIC_NCSI_NUM_MASK (0XF << CSIC_NCSI_NUM) 141 #define CSIC_MCSI_NUM 24 142 #define CSIC_MCSI_NUM_MASK (0XF << CSIC_MCSI_NUM) 143 #define CSIC_PARSER_NUM 28 144 #define CSIC_PARSER_NUM_MASK (0XF << CSIC_PARSER_NUM) 145 146 #define CSIC_VER_SMALL 0 147 #define CSIC_VER_SMALL_MASK (0XFFF << CSIC_VER_SMALL) 148 #define CSIC_VER_BIG 12 149 #define CSIC_VER_BIG_MASK (0XFFF << CSIC_VER_BIG) 150 151 #define CSIC_MULP_MODE_REG_OFF 0X100 152 #define CSIC_MULP_EN 0 153 #define CSIC_MULP_EN_MASK (0X1 << CSIC_MULP_EN) 154 #define CSIC_MULP_CS 8 155 #define CSIC_MULP_CS_MASK (0XFF << CSIC_MULP_CS) 156 #define CSIC_MULP_STATUS 24 157 #define CSIC_MULP_STATUS_MASK (0XFF << CSIC_MULP_STATUS) 158 #define CSIC_MULP_INT_REG_OFF 0X104 159 #define CSIC_MULP_INT_EN 0 160 #define CSIC_MULP_INT_EN_MASK (0X3 << CSIC_MULP_INT_EN) 161 #define CSIC_MULP_DONE_PD 16 162 #define CSIC_MULP_DONE_PD_MASK (0X1 << CSIC_MULP_DONE_PD) 163 #define CSIC_MULP_ERR_PD 17 164 #define CSIC_MULP_ERR_PD_MASK (0X1 << CSIC_MULP_ERR_PD) 165 #define CSIC_MULP_INT_PD_MASK (0X3 << CSIC_MULP_DONE_PD) 166 167 /* 168 *CSIC CCU registers 169 */ 170 #define CSIC_CCU_MODE_REG_OFF 0x000 171 #define CSIC_MCSI_CLK_MODE 0 172 #define CSIC_MCSI_CLK_MODE_MASK (0X1 << CSIC_MCSI_CLK_MODE) 173 #define CSIC_MCSI_POST_CLK_MODE 1 174 #define CSIC_MCSI_POST_CLK_MODE_MASK (0X1 << CSIC_MCSI_POST_CLK_MODE) 175 #define CSIC_CCU_CLK_GATING_DISABLE 31 176 #define CSIC_CCU_CLK_GATING_DISABLE_MASK (0X1 << CSIC_CCU_CLK_GATING_DISABLE) 177 178 #define CSIC_CCU_PARSER_CLK_EN_REG_OFF 0x004 179 #define CSIC_MCSI_PARSER0_CLK_EN 0 180 #define CSIC_MCSI_PARSER0_CLK_EN_MASK (0X1 << CSIC_MCSI_PARSER0_CLK_EN) 181 #define CSIC_MCSI_PARSER1_CLK_EN 1 182 #define CSIC_MCSI_PARSER1_CLK_EN_MASK (0X1 << CSIC_MCSI_PARSER1_CLK_EN) 183 #define CSIC_MCSI_COMBO0_CLK_EN 8 184 #define CSIC_MCSI_COMBO0_CLK_EN_MASK (0X1 << CSIC_MCSI_COMBO0_CLK_EN) 185 #define CSIC_MCSI_MIPI0_CLK_EN 16 186 #define CSIC_MCSI_MIPI0_CLK_EN_MASK (0X1 << CSIC_MCSI_MIPI0_CLK_EN) 187 188 #define CSIC_CCU_ISP_CLK_EN_REG_OFF 0x008 189 #define CSIC_MISP0_CLK_EN 0 190 #define CSIC_MISP0_CLK_EN_MASK (0X1 << CSIC_MISP0_CLK_EN) 191 #define CSIC_MISP0_BRIDGE_CLK_EN 4 192 #define CSIC_MISP0_BRIDGE_CLK_EN_MASK (0X1 << CSIC_MISP0_BRIDGE_CLK_EN) 193 194 #define CSIC_CCU_POST0_CLK_EN_REG_OFF 0x00c 195 #define CSIC_MCSI_BK0_CLK_EN 0 196 #define CSIC_MCSI_BK0_CLK_EN_MASK (0X1 << CSIC_MCSI_BK0_CLK_EN) 197 #define CSIC_MCSI_BK1_CLK_EN 1 198 #define CSIC_MCSI_BK1_CLK_EN_MASK (0X1 << CSIC_MCSI_BK1_CLK_EN) 199 #define CSIC_MCSI_BK2_CLK_EN 2 200 #define CSIC_MCSI_BK2_CLK_EN_MASK (0X1 << CSIC_MCSI_BK2_CLK_EN) 201 #define CSIC_MCSI_BK3_CLK_EN 3 202 #define CSIC_MCSI_BK3_CLK_EN_MASK (0X1 << CSIC_MCSI_BK3_CLK_EN) 203 #define CSIC_MCSI_VIPP0_CLK_EN 8 204 #define CSIC_MCSI_VIPP0_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP0_CLK_EN) 205 #define CSIC_MCSI_VIPP1_CLK_EN 9 206 #define CSIC_MCSI_VIPP1_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP1_CLK_EN) 207 #define CSIC_MCSI_VIPP2_CLK_EN 10 208 #define CSIC_MCSI_VIPP2_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP2_CLK_EN) 209 #define CSIC_MCSI_VIPP3_CLK_EN 11 210 #define CSIC_MCSI_VIPP3_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP3_CLK_EN) 211 #define CSIC_MCSI_POST0_CLK_EN 16 212 #define CSIC_MCSI_POST0_CLK_EN_MASK (0X1 << CSIC_MCSI_POST0_CLK_EN) 213 214 #endif /*__CSIC__TOP__REG__I__H__*/ 215 216