1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_ADC_H 22 #define STM32MP1xx_HAL_ADC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /* Include low level driver */ 32 #include "stm32mp1xx_ll_adc.h" 33 34 /** @addtogroup STM32MP1xx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup ADC 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup ADC_Exported_Types ADC Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief ADC group regular oversampling structure definition 49 */ 50 typedef struct 51 { 52 uint32_t Ratio; /*!< Configures the oversampling ratio. 53 This parameter can be a value between 1 and 1024 */ 54 55 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 56 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 57 58 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 59 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 60 61 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 62 The oversampling is either temporary stopped or reset upon an injected 63 sequence interruption. 64 If oversampling is enabled on both regular and injected groups, this parameter 65 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 66 (the oversampling buffer is zeroed during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note Parameters of this structure are shared within 2 scopes: 74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 75 * ScanConvMode, EOCSelection, LowPowerAutoWait. 76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 78 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 79 * ADC state can be either: 80 * - For all parameters: ADC disabled 81 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 82 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 83 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 84 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 85 * (which fulfills the ADC state condition) on the fly). 86 */ 87 typedef struct 88 { 89 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 90 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 91 Note: The ADC clock configuration is common to all ADC instances. 92 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 93 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 94 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 95 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 96 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 97 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 98 Note: This parameter can be modified only if all ADC instances are disabled. */ 99 100 uint32_t Resolution; /*!< Configure the ADC resolution. 101 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 102 103 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 104 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 105 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 106 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 107 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 108 Scan direction is upward: from rank 1 to rank 'n'. 109 This parameter can be a value of @ref ADC_Scan_mode */ 110 111 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 112 This parameter can be a value of @ref ADC_EOCSelection. */ 113 114 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 115 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 116 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 117 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 118 for low frequency applications. 119 This parameter can be set to ENABLE or DISABLE. 120 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 121 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 122 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 123 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 124 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 125 126 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 127 after the first ADC conversion start trigger occurred (software start or external trigger). 128 This parameter can be set to ENABLE or DISABLE. */ 129 130 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 131 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 132 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 133 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 134 continuous mode or external trigger that could launch a conversion). */ 135 136 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 137 (main sequence subdivided in successive parts). 138 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 139 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 140 This parameter can be set to ENABLE or DISABLE. */ 141 142 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 143 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 144 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 145 146 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 147 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 148 This parameter can be a value of @ref ADC_regular_external_trigger_source. 149 Caution: external trigger source is common to all ADC instances. */ 150 151 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 152 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 153 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 154 155 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. 156 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 157 This parameter can be a value of @ref ADC_ConversionDataManagement. 158 Note: This parameter must be modified when no conversion is on going on both regular and injected groups 159 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 160 161 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 162 This parameter applies to ADC group regular only. 163 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 164 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 165 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 166 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 167 Note: Error reporting with respect to the conversion mode: 168 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 169 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 170 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 171 172 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 173 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 174 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 175 This parameter can be set to ENABLE or DISABLE. 176 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 177 178 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 179 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 180 181 } ADC_InitTypeDef; 182 183 /** 184 * @brief Structure definition of ADC channel for regular group 185 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 186 * ADC state can be either: 187 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 188 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 189 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 190 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 191 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 192 * on the fly). 193 */ 194 typedef struct 195 { 196 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 197 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 198 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 199 200 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 201 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 202 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 203 the new channel setting (or parameter number of conversions adjusted) */ 204 205 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 206 Unit: ADC clock cycles 207 Conversion time is the addition of sampling time and processing time 208 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 209 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 210 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 211 It overwrites the last setting. 212 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 213 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 214 Refer to device datasheet for timings values. */ 215 216 uint32_t SingleDiff; /*!< Select single-ended or differential input. 217 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 218 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 219 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 220 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 221 It overwrites the last setting. 222 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 223 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 224 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 225 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 226 of another parameter update on the fly) */ 227 228 uint32_t OffsetNumber; /*!< Select the offset number 229 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 230 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 231 232 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 233 Offset value must be a positive number. 234 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 235 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 236 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 237 without continuous mode or external trigger that could launch a conversion). */ 238 239 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. 240 This parameter is applied only for 16-bit or 8-bit resolution. 241 This parameter can be set to ENABLE or DISABLE.*/ 242 243 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 244 This parameter is applied only for 16-bit or 8-bit resolution. 245 This parameter can be set to ENABLE or DISABLE. */ 246 247 } ADC_ChannelConfTypeDef; 248 249 /** 250 * @brief Structure definition of ADC analog watchdog 251 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 252 * ADC state can be either: 253 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 254 */ 255 typedef struct 256 { 257 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 258 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 259 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 260 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 261 262 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 263 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 264 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 265 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 266 267 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 268 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 269 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 270 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 271 272 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 273 This parameter can be set to ENABLE or DISABLE */ 274 275 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 276 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 277 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 278 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 279 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 280 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 281 impacted: the comparison of analog watchdog thresholds is done 282 on oversampling intermediate computation (after ratio, before shift 283 application): intermediate register bitfield [32:7] (26 most significant bits). */ 284 285 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 286 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 287 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 288 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 289 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 290 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 291 impacted: the comparison of analog watchdog thresholds is done 292 on oversampling intermediate computation (after ratio, before shift 293 application): intermediate register bitfield [32:7] (26 most significant bits). */ 294 } ADC_AnalogWDGConfTypeDef; 295 296 /** 297 * @brief ADC group injected contexts queue configuration 298 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 299 */ 300 typedef struct 301 { 302 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 303 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 304 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 305 306 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 307 } ADC_InjectionConfigTypeDef; 308 309 /** @defgroup ADC_States ADC States 310 * @{ 311 */ 312 313 /** 314 * @brief HAL ADC state machine: ADC states definition (bitfields) 315 * @note ADC state machine is managed by bitfields, state must be compared 316 * with bit by bit. 317 * For example: 318 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 319 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 320 */ 321 /* States of ADC global scope */ 322 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 323 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 324 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 325 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 326 327 /* States of ADC errors */ 328 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 329 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 330 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 331 332 /* States of ADC group regular */ 333 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 334 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 335 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 336 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 337 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 338 339 /* States of ADC group injected */ 340 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 341 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 342 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 343 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 344 345 /* States of ADC analog watchdogs */ 346 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 347 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 348 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 349 350 /* States of ADC multi-mode */ 351 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 352 353 /** 354 * @} 355 */ 356 357 /** 358 * @brief ADC handle Structure definition 359 */ 360 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 361 typedef struct __ADC_HandleTypeDef 362 #else 363 typedef struct 364 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 365 { 366 ADC_TypeDef *Instance; /*!< Register base address */ 367 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 368 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 369 HAL_LockTypeDef Lock; /*!< ADC locking object */ 370 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 371 __IO uint32_t ErrorCode; /*!< ADC Error code */ 372 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 373 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 374 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 375 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 376 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 377 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 378 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 379 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 380 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 381 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 382 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 383 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 384 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 385 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 386 } ADC_HandleTypeDef; 387 388 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 389 /** 390 * @brief HAL ADC Callback ID enumeration definition 391 */ 392 typedef enum 393 { 394 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 395 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 396 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 397 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 398 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 399 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 400 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 401 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 402 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 403 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 404 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 405 } HAL_ADC_CallbackIDTypeDef; 406 407 /** 408 * @brief HAL ADC Callback pointer definition 409 */ 410 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 411 412 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 413 414 /** 415 * @} 416 */ 417 418 419 /* Exported constants --------------------------------------------------------*/ 420 421 /** @defgroup ADC_Exported_Constants ADC Exported Constants 422 * @{ 423 */ 424 425 /** @defgroup ADC_Error_Code ADC Error Code 426 * @{ 427 */ 428 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 429 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 430 enable/disable, erroneous state, ...) */ 431 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 432 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 433 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 434 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 435 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 436 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 442 * @{ 443 */ 444 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 445 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 446 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 447 448 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 449 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 450 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 451 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 452 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 453 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 454 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 455 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 456 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 457 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 458 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 459 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 465 * @{ 466 */ 467 #define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits */ 468 #define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */ 469 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 470 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 471 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 477 * @{ 478 */ 479 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 480 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 486 * @{ 487 */ 488 /* ADC group regular trigger sources for all ADC instances */ 489 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 490 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 491 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 492 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 493 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 494 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 495 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 496 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */ 497 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 498 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 499 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 500 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 501 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 502 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 503 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 504 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 505 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 506 #define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 507 #define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 508 #define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */ 509 /** 510 * @} 511 */ 512 513 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 514 * @{ 515 */ 516 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 517 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 518 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 519 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 525 * @{ 526 */ 527 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 528 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 534 * @{ 535 */ 536 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 537 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 543 * @{ 544 */ 545 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 546 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 547 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 548 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 549 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 550 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 551 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 552 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 553 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 554 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 555 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 556 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 557 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 558 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 559 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 560 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 566 * @{ 567 */ 568 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles */ 569 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 570 #define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles */ 571 #define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles */ 572 #define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles */ 573 #define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles */ 574 #define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles */ 575 #define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode 581 * @{ 582 */ 583 #define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET) 584 #define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY) 585 /** 586 * @} 587 */ 588 589 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 590 * @{ 591 */ 592 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 593 /* all ADC instances (refer to Reference Manual). */ 594 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 595 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 596 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 597 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 598 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 599 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 600 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 601 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 602 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 603 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 604 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 605 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 606 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 607 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 608 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 609 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 610 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 611 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 612 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 613 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 614 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC2. */ 615 #define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel connected to VddCore, channel specific to ADC2. */ 616 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC2. */ 617 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC2. */ 618 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 619 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 625 * @{ 626 */ 627 #define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */ 628 #define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ 629 #define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ 630 #define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */ 631 /** 632 * @} 633 */ 634 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 635 * @{ 636 */ 637 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 638 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 639 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 640 /** 641 * @} 642 */ 643 644 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 645 * @{ 646 */ 647 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 648 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 649 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 650 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 651 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 652 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 653 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 654 /** 655 * @} 656 */ 657 658 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 659 * @{ 660 */ 661 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 662 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 663 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 664 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 665 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 666 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 667 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 668 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 669 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 670 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */ 671 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */ 672 #define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 678 * @{ 679 */ 680 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 681 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 682 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 683 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 684 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 685 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 686 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 687 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 688 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 689 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 690 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 691 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 692 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 693 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 694 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 695 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 701 * @{ 702 */ 703 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 704 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 710 * @{ 711 */ 712 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 713 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 714 /** 715 * @} 716 */ 717 718 /** @defgroup ADC_Event_type ADC Event type 719 * @{ 720 */ 721 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 722 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 723 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 724 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 725 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 726 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 727 /** 728 * @} 729 */ 730 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 731 732 /** @defgroup ADC_interrupts_definition ADC interrupts definition 733 * @{ 734 */ 735 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 736 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 737 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 738 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 739 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 740 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 741 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 742 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 743 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 744 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 745 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 746 747 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 748 749 /** 750 * @} 751 */ 752 753 /** @defgroup ADC_flags_definition ADC flags definition 754 * @{ 755 */ 756 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 757 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 758 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 759 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 760 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 761 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 762 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 763 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 764 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 765 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 766 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 767 768 /** 769 * @} 770 */ 771 772 /** 773 * @} 774 */ 775 776 /* Private macro -------------------------------------------------------------*/ 777 778 /** @defgroup ADC_Private_Macros ADC Private Macros 779 * @{ 780 */ 781 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 782 /* code of final user. */ 783 784 /** 785 * @brief Verify the ADC data conversion setting. 786 * @param DATA : programmed DATA conversion mode. 787 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 788 */ 789 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 790 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 791 (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \ 792 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 793 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 794 795 /** 796 * @brief Return resolution bits in CFGR register RES[1:0] field. 797 * @param __HANDLE__ ADC handle 798 * @retval Value of bitfield RES in CFGR register. 799 */ 800 #define ADC_GET_RESOLUTION(__HANDLE__) \ 801 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 802 803 /** 804 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 805 * @param __HANDLE__ ADC handle 806 * @retval None 807 */ 808 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 809 810 /** 811 * @brief Verification of ADC state: enabled or disabled. 812 * @param __HANDLE__ ADC handle 813 * @retval SET (ADC enabled) or RESET (ADC disabled) 814 */ 815 #define ADC_IS_ENABLE(__HANDLE__) \ 816 ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 817 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 818 ) ? SET : RESET) 819 820 /** 821 * @brief Check if conversion is on going on regular group. 822 * @param __HANDLE__ ADC handle 823 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 824 */ 825 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 826 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 827 828 /** 829 * @brief Check if ADC clock mode is synchronous 830 * @param __HANDLE__: ADC handle 831 * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous) 832 */ 833 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \ 834 (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \ 835 ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL): RESET) 836 837 /** 838 * @brief Simultaneously clear and set specific bits of the handle State. 839 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 840 * the first parameter is the ADC handle State, the second parameter is the 841 * bit field to clear, the third and last parameter is the bit field to set. 842 * @retval None 843 */ 844 #define ADC_STATE_CLR_SET MODIFY_REG 845 846 /** 847 * @brief Verify that a given value is aligned with the ADC resolution range. 848 * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits). 849 * @param __ADC_VALUE__ value checked against the resolution. 850 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 851 */ 852 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 853 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 854 855 /** 856 * @brief Verify the length of the scheduled regular conversions group. 857 * @param __LENGTH__ number of programmed conversions. 858 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 859 */ 860 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 861 862 863 /** 864 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 865 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 866 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 867 */ 868 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 869 870 871 /** 872 * @brief Verify the ADC clock setting. 873 * @param __ADC_CLOCK__ programmed ADC clock. 874 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 875 */ 876 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 877 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 878 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 879 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 880 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 881 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 882 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 883 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 884 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 885 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 886 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 887 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 888 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 889 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 890 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 891 892 /** 893 * @brief Verify the ADC resolution setting. 894 * @param __RESOLUTION__ programmed ADC resolution. 895 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 896 */ 897 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 898 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 899 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 900 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 901 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 902 /** 903 * @brief Verify the ADC resolution setting when limited to 8 bits. 904 * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits. 905 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 906 */ 907 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B)) 908 909 /** 910 * @brief Verify the ADC scan mode. 911 * @param __SCAN_MODE__ programmed ADC scan mode. 912 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 913 */ 914 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 915 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 916 917 /** 918 * @brief Verify the ADC edge trigger setting for regular group. 919 * @param __EDGE__ programmed ADC edge trigger setting. 920 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 921 */ 922 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 923 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 924 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 925 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 926 927 /** 928 * @brief Verify the ADC regular conversions external trigger. 929 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 930 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 931 */ 932 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 933 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 934 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 935 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 936 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 937 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 938 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 939 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 940 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 941 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 942 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 943 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 944 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 945 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 946 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 947 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 948 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 949 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 950 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 951 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 952 953 /** 954 * @brief Verify the ADC regular conversions check for converted data availability. 955 * @param __EOC_SELECTION__ converted data availability check. 956 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 957 */ 958 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 959 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 960 961 /** 962 * @brief Verify the ADC regular conversions overrun handling. 963 * @param __OVR__ ADC regular conversions overrun handling. 964 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 965 */ 966 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 967 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 968 969 /** 970 * @brief Verify the ADC conversions sampling time. 971 * @param __TIME__ ADC conversions sampling time. 972 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 973 */ 974 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 975 ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 976 ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \ 977 ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \ 978 ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \ 979 ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \ 980 ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \ 981 ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) ) 982 983 /** 984 * @brief Verify the ADC regular channel setting. 985 * @param __CHANNEL__ programmed ADC regular channel. 986 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 987 */ 988 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 989 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 990 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 991 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 992 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 993 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 994 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 995 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 996 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 997 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 998 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 999 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1000 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1001 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1002 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1003 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1004 1005 /** 1006 * @} 1007 */ 1008 1009 1010 /* Private constants ---------------------------------------------------------*/ 1011 1012 /** @defgroup ADC_Private_Constants ADC Private Constants 1013 * @{ 1014 */ 1015 1016 /* Fixed timeout values for ADC conversion (including sampling time) */ 1017 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1018 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1019 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1020 /* Minimum ADC Clock frequency is 0.14 MHz */ 1021 /* Maximum conversion time is */ 1022 /* 653 / 0.14 MHz = 4.66 ms */ 1023 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1024 1025 /* Delay for temperature sensor stabilization time. */ 1026 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1027 /* Unit: us */ 1028 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1029 1030 /* Delay for ADC voltage regulator startup time */ 1031 /* Maximum delay is 10 microseconds */ 1032 /* (refer device RM, parameter Tadcvreg_stup). */ 1033 #define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ 1034 1035 /** 1036 * @} 1037 */ 1038 1039 /* Exported macro ------------------------------------------------------------*/ 1040 1041 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1042 * @{ 1043 */ 1044 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1045 /* final user. */ 1046 1047 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1048 * @{ 1049 */ 1050 1051 /** @brief Reset ADC handle state. 1052 * @param __HANDLE__ ADC handle 1053 * @retval None 1054 */ 1055 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1056 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1057 do{ \ 1058 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1059 (__HANDLE__)->MspInitCallback = NULL; \ 1060 (__HANDLE__)->MspDeInitCallback = NULL; \ 1061 } while(0) 1062 #else 1063 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1064 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1065 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1066 1067 /** 1068 * @brief Enable ADC interrupt. 1069 * @param __HANDLE__ ADC handle 1070 * @param __INTERRUPT__ ADC Interrupt 1071 * This parameter can be one of the following values: 1072 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1073 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1074 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1075 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1076 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1077 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1078 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1079 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1080 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1081 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1082 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1083 * @retval None 1084 */ 1085 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1086 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1087 1088 /** 1089 * @brief Disable ADC interrupt. 1090 * @param __HANDLE__ ADC handle 1091 * @param __INTERRUPT__ ADC Interrupt 1092 * This parameter can be one of the following values: 1093 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1094 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1095 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1096 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1097 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1098 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1099 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1100 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1101 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1102 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1103 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1104 * @retval None 1105 */ 1106 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1107 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1108 1109 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1110 * @param __HANDLE__ ADC handle 1111 * @param __INTERRUPT__ ADC interrupt source to check 1112 * This parameter can be one of the following values: 1113 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1114 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1115 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1116 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1117 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1118 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1119 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1120 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1121 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1122 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1123 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1124 * @retval State of interruption (SET or RESET) 1125 */ 1126 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1127 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1128 1129 /** 1130 * @brief Check whether the specified ADC flag is set or not. 1131 * @param __HANDLE__ ADC handle 1132 * @param __FLAG__ ADC flag 1133 * This parameter can be one of the following values: 1134 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1135 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1136 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1137 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1138 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1139 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1140 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1141 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1142 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1143 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1144 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1145 * @retval State of flag (TRUE or FALSE). 1146 */ 1147 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1148 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1149 1150 /** 1151 * @brief Clear the specified ADC flag. 1152 * @param __HANDLE__ ADC handle 1153 * @param __FLAG__ ADC flag 1154 * This parameter can be one of the following values: 1155 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1156 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1157 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1158 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1159 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1160 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1161 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1162 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1163 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1164 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1165 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1166 * @retval None 1167 */ 1168 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1169 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1170 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1171 1172 /** 1173 * @} 1174 */ 1175 1176 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1177 * @{ 1178 */ 1179 1180 /** 1181 * @brief Helper macro to get ADC channel number in decimal format 1182 * from literals ADC_CHANNEL_x. 1183 * @note Example: 1184 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1185 * will return decimal number "4". 1186 * @note The input can be a value from functions where a channel 1187 * number is returned, either defined with number 1188 * or with bitfield (only one bit must be set). 1189 * @param __CHANNEL__ This parameter can be one of the following values: 1190 * @arg @ref ADC_CHANNEL_0 (3) 1191 * @arg @ref ADC_CHANNEL_1 (3) 1192 * @arg @ref ADC_CHANNEL_2 (3) 1193 * @arg @ref ADC_CHANNEL_3 (3) 1194 * @arg @ref ADC_CHANNEL_4 (3) 1195 * @arg @ref ADC_CHANNEL_5 (3) 1196 * @arg @ref ADC_CHANNEL_6 1197 * @arg @ref ADC_CHANNEL_7 1198 * @arg @ref ADC_CHANNEL_8 1199 * @arg @ref ADC_CHANNEL_9 1200 * @arg @ref ADC_CHANNEL_10 1201 * @arg @ref ADC_CHANNEL_11 1202 * @arg @ref ADC_CHANNEL_12 1203 * @arg @ref ADC_CHANNEL_13 1204 * @arg @ref ADC_CHANNEL_14 1205 * @arg @ref ADC_CHANNEL_15 1206 * @arg @ref ADC_CHANNEL_16 1207 * @arg @ref ADC_CHANNEL_17 1208 * @arg @ref ADC_CHANNEL_18 1209 * @arg @ref ADC_CHANNEL_19 1210 * @arg @ref ADC_CHANNEL_VREFINT (1) 1211 * @arg @ref ADC_CHANNEL_VCORE (1) 1212 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1213 * @arg @ref ADC_CHANNEL_VBAT (1) 1214 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1215 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1216 * 1217 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1218 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1219 * Other channels are slow channels (conversion rate: refer to reference manual). 1220 * @retval Value between Min_Data=0 and Max_Data=18 1221 */ 1222 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1223 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1224 1225 /** 1226 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1227 * from number in decimal format. 1228 * @note Example: 1229 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1230 * will return a data equivalent to "ADC_CHANNEL_4". 1231 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1232 * @retval Returned value can be one of the following values: 1233 * @arg @ref ADC_CHANNEL_0 (3) 1234 * @arg @ref ADC_CHANNEL_1 (3) 1235 * @arg @ref ADC_CHANNEL_2 (3) 1236 * @arg @ref ADC_CHANNEL_3 (3) 1237 * @arg @ref ADC_CHANNEL_4 (3) 1238 * @arg @ref ADC_CHANNEL_5 (3) 1239 * @arg @ref ADC_CHANNEL_6 1240 * @arg @ref ADC_CHANNEL_7 1241 * @arg @ref ADC_CHANNEL_8 1242 * @arg @ref ADC_CHANNEL_9 1243 * @arg @ref ADC_CHANNEL_10 1244 * @arg @ref ADC_CHANNEL_11 1245 * @arg @ref ADC_CHANNEL_12 1246 * @arg @ref ADC_CHANNEL_13 1247 * @arg @ref ADC_CHANNEL_14 1248 * @arg @ref ADC_CHANNEL_15 1249 * @arg @ref ADC_CHANNEL_16 1250 * @arg @ref ADC_CHANNEL_17 1251 * @arg @ref ADC_CHANNEL_18 1252 * @arg @ref ADC_CHANNEL_19 1253 * @arg @ref ADC_CHANNEL_VREFINT (1) 1254 * @arg @ref ADC_CHANNEL_VCORE (1) 1255 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1256 * @arg @ref ADC_CHANNEL_VBAT (1) 1257 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1258 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1259 * 1260 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1261 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1262 * Other channels are slow channels (conversion rate: refer to reference manual).\n 1263 * (1) For ADC channel read back from ADC register, 1264 * comparison with internal channel parameter to be done 1265 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1266 */ 1267 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1268 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1269 1270 /** 1271 * @brief Helper macro to determine whether the selected channel 1272 * corresponds to literal definitions of driver. 1273 * @note The different literal definitions of ADC channels are: 1274 * - ADC internal channel: 1275 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1276 * - ADC external channel (channel connected to a GPIO pin): 1277 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1278 * @note The channel parameter must be a value defined from literal 1279 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1280 * ADC_CHANNEL_TEMPSENSOR, ...), 1281 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1282 * must not be a value from functions where a channel number is 1283 * returned from ADC registers, 1284 * because internal and external channels share the same channel 1285 * number in ADC registers. The differentiation is made only with 1286 * parameters definitions of driver. 1287 * @param __CHANNEL__ This parameter can be one of the following values: 1288 * @arg @ref ADC_CHANNEL_0 (3) 1289 * @arg @ref ADC_CHANNEL_1 (3) 1290 * @arg @ref ADC_CHANNEL_2 (3) 1291 * @arg @ref ADC_CHANNEL_3 (3) 1292 * @arg @ref ADC_CHANNEL_4 (3) 1293 * @arg @ref ADC_CHANNEL_5 (3) 1294 * @arg @ref ADC_CHANNEL_6 1295 * @arg @ref ADC_CHANNEL_7 1296 * @arg @ref ADC_CHANNEL_8 1297 * @arg @ref ADC_CHANNEL_9 1298 * @arg @ref ADC_CHANNEL_10 1299 * @arg @ref ADC_CHANNEL_11 1300 * @arg @ref ADC_CHANNEL_12 1301 * @arg @ref ADC_CHANNEL_13 1302 * @arg @ref ADC_CHANNEL_14 1303 * @arg @ref ADC_CHANNEL_15 1304 * @arg @ref ADC_CHANNEL_16 1305 * @arg @ref ADC_CHANNEL_17 1306 * @arg @ref ADC_CHANNEL_18 1307 * @arg @ref ADC_CHANNEL_19 1308 * @arg @ref ADC_CHANNEL_VREFINT (1) 1309 * @arg @ref ADC_CHANNEL_VCORE (1) 1310 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1311 * @arg @ref ADC_CHANNEL_VBAT (1) 1312 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1313 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1314 * 1315 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1316 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1317 * Other channels are slow channels (conversion rate: refer to reference manual). 1318 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1319 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1320 */ 1321 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1322 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1323 1324 /** 1325 * @brief Helper macro to convert a channel defined from parameter 1326 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1327 * ADC_CHANNEL_TEMPSENSOR, ...), 1328 * to its equivalent parameter definition of a ADC external channel 1329 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1330 * @note The channel parameter can be, additionally to a value 1331 * defined from parameter definition of a ADC internal channel 1332 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1333 * a value defined from parameter definition of 1334 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1335 * or a value from functions where a channel number is returned 1336 * from ADC registers. 1337 * @param __CHANNEL__ This parameter can be one of the following values: 1338 * @arg @ref ADC_CHANNEL_0 (3) 1339 * @arg @ref ADC_CHANNEL_1 (3) 1340 * @arg @ref ADC_CHANNEL_2 (3) 1341 * @arg @ref ADC_CHANNEL_3 (3) 1342 * @arg @ref ADC_CHANNEL_4 (3) 1343 * @arg @ref ADC_CHANNEL_5 (3) 1344 * @arg @ref ADC_CHANNEL_6 1345 * @arg @ref ADC_CHANNEL_7 1346 * @arg @ref ADC_CHANNEL_8 1347 * @arg @ref ADC_CHANNEL_9 1348 * @arg @ref ADC_CHANNEL_10 1349 * @arg @ref ADC_CHANNEL_11 1350 * @arg @ref ADC_CHANNEL_12 1351 * @arg @ref ADC_CHANNEL_13 1352 * @arg @ref ADC_CHANNEL_14 1353 * @arg @ref ADC_CHANNEL_15 1354 * @arg @ref ADC_CHANNEL_16 1355 * @arg @ref ADC_CHANNEL_17 1356 * @arg @ref ADC_CHANNEL_18 1357 * @arg @ref ADC_CHANNEL_19 1358 * @arg @ref ADC_CHANNEL_VREFINT (1) 1359 * @arg @ref ADC_CHANNEL_VCORE (1) 1360 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1361 * @arg @ref ADC_CHANNEL_VBAT (1) 1362 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1363 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1364 * 1365 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1366 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1367 * Other channels are slow channels (conversion rate: refer to reference manual). 1368 * @retval Returned value can be one of the following values: 1369 * @arg @ref ADC_CHANNEL_0 1370 * @arg @ref ADC_CHANNEL_1 1371 * @arg @ref ADC_CHANNEL_2 1372 * @arg @ref ADC_CHANNEL_3 1373 * @arg @ref ADC_CHANNEL_4 1374 * @arg @ref ADC_CHANNEL_5 1375 * @arg @ref ADC_CHANNEL_6 1376 * @arg @ref ADC_CHANNEL_7 1377 * @arg @ref ADC_CHANNEL_8 1378 * @arg @ref ADC_CHANNEL_9 1379 * @arg @ref ADC_CHANNEL_10 1380 * @arg @ref ADC_CHANNEL_11 1381 * @arg @ref ADC_CHANNEL_12 1382 * @arg @ref ADC_CHANNEL_13 1383 * @arg @ref ADC_CHANNEL_14 1384 * @arg @ref ADC_CHANNEL_15 1385 * @arg @ref ADC_CHANNEL_16 1386 * @arg @ref ADC_CHANNEL_17 1387 * @arg @ref ADC_CHANNEL_18 1388 */ 1389 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1390 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1391 1392 /** 1393 * @brief Helper macro to determine whether the internal channel 1394 * selected is available on the ADC instance selected. 1395 * @note The channel parameter must be a value defined from parameter 1396 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1397 * ADC_CHANNEL_TEMPSENSOR, ...), 1398 * must not be a value defined from parameter definition of 1399 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1400 * or a value from functions where a channel number is 1401 * returned from ADC registers, 1402 * because internal and external channels share the same channel 1403 * number in ADC registers. The differentiation is made only with 1404 * parameters definitions of driver. 1405 * @param __ADC_INSTANCE__ ADC instance 1406 * @param __CHANNEL__ This parameter can be one of the following values: 1407 * @arg @ref ADC_CHANNEL_VREFINT (1) 1408 * @arg @ref ADC_CHANNEL_VCORE (1) 1409 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1410 * @arg @ref ADC_CHANNEL_VBAT (1) 1411 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1412 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1413 * 1414 * (1) On STM32MP1, parameter available only on ADC instance: ADC2. 1415 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1416 * Value "1" if the internal channel selected is available on the ADC instance selected. 1417 */ 1418 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1419 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1420 1421 #if defined(ADC_MULTIMODE_SUPPORT) 1422 /** 1423 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1424 * or ADC slave from raw value with both ADC conversion data concatenated. 1425 * @note This macro is intended to be used when multimode transfer by DMA 1426 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1427 * In this case the transferred data need to processed with this macro 1428 * to separate the conversion data of ADC master and ADC slave. 1429 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1430 * @arg @ref LL_ADC_MULTI_MASTER 1431 * @arg @ref LL_ADC_MULTI_SLAVE 1432 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1433 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1434 */ 1435 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1436 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1437 #endif /* ADC_MULTIMODE_SUPPORT */ 1438 1439 /** 1440 * @brief Helper macro to select the ADC common instance 1441 * to which is belonging the selected ADC instance. 1442 * @note ADC common register instance can be used for: 1443 * - Set parameters common to several ADC instances 1444 * - Multimode (for devices with several ADC instances) 1445 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1446 * @param __ADCx__ ADC instance 1447 * @retval ADC common register instance 1448 */ 1449 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1450 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1451 1452 /** 1453 * @brief Helper macro to check if all ADC instances sharing the same 1454 * ADC common instance are disabled. 1455 * @note This check is required by functions with setting conditioned to 1456 * ADC state: 1457 * All ADC instances of the ADC common group must be disabled. 1458 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1459 * @note On devices with only 1 ADC common instance, parameter of this macro 1460 * is useless and can be ignored (parameter kept for compatibility 1461 * with devices featuring several ADC common instances). 1462 * @param __ADCXY_COMMON__ ADC common instance 1463 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1464 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1465 * are disabled. 1466 * Value "1" if at least one ADC instance sharing the same ADC common instance 1467 * is enabled. 1468 */ 1469 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1470 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1471 1472 /** 1473 * @brief Helper macro to define the ADC conversion data full-scale digital 1474 * value corresponding to the selected ADC resolution. 1475 * @note ADC conversion data full-scale corresponds to voltage range 1476 * determined by analog voltage references Vref+ and Vref- 1477 * (refer to reference manual). 1478 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1479 * @arg @ref ADC_RESOLUTION_16B 1480 * @arg @ref ADC_RESOLUTION_14B 1481 * @arg @ref ADC_RESOLUTION_12B 1482 * @arg @ref ADC_RESOLUTION_10B 1483 * @arg @ref ADC_RESOLUTION_8B 1484 * @retval ADC conversion data full-scale digital value 1485 */ 1486 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1487 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1488 1489 /** 1490 * @brief Helper macro to convert the ADC conversion data from 1491 * a resolution to another resolution. 1492 * @param __DATA__ ADC conversion data to be converted 1493 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1494 * This parameter can be one of the following values: 1495 * @arg @ref ADC_RESOLUTION_16B 1496 * @arg @ref ADC_RESOLUTION_14B 1497 * @arg @ref ADC_RESOLUTION_12B 1498 * @arg @ref ADC_RESOLUTION_10B 1499 * @arg @ref ADC_RESOLUTION_8B 1500 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1501 * This parameter can be one of the following values: 1502 * @arg @ref ADC_RESOLUTION_16B 1503 * @arg @ref ADC_RESOLUTION_14B 1504 * @arg @ref ADC_RESOLUTION_12B 1505 * @arg @ref ADC_RESOLUTION_10B 1506 * @arg @ref ADC_RESOLUTION_8B 1507 * @retval ADC conversion data to the requested resolution 1508 */ 1509 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1510 __ADC_RESOLUTION_CURRENT__,\ 1511 __ADC_RESOLUTION_TARGET__) \ 1512 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1513 (__ADC_RESOLUTION_CURRENT__),\ 1514 (__ADC_RESOLUTION_TARGET__)) 1515 1516 /** 1517 * @brief Helper macro to calculate the voltage (unit: mVolt) 1518 * corresponding to a ADC conversion data (unit: digital value). 1519 * @note Analog reference voltage (Vref+) must be either known from 1520 * user board environment or can be calculated using ADC measurement 1521 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1522 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1523 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1524 * (unit: digital value). 1525 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1526 * @arg @ref ADC_RESOLUTION_16B 1527 * @arg @ref ADC_RESOLUTION_14B 1528 * @arg @ref ADC_RESOLUTION_12B 1529 * @arg @ref ADC_RESOLUTION_10B 1530 * @arg @ref ADC_RESOLUTION_8B 1531 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1532 */ 1533 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1534 __ADC_DATA__,\ 1535 __ADC_RESOLUTION__) \ 1536 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1537 (__ADC_DATA__),\ 1538 (__ADC_RESOLUTION__)) 1539 1540 /** 1541 * @brief Helper macro to calculate analog reference voltage (Vref+) 1542 * (unit: mVolt) from ADC conversion data of internal voltage 1543 * reference VrefInt. 1544 * @note Computation is using VrefInt calibration value 1545 * stored in system memory for each device during production. 1546 * @note This voltage depends on user board environment: voltage level 1547 * connected to pin Vref+. 1548 * On devices with small package, the pin Vref+ is not present 1549 * and internally bonded to pin Vdda. 1550 * @note On this STM32 series, calibration data of internal voltage reference 1551 * VrefInt corresponds to a resolution of 12 bits, 1552 * this is the recommended ADC resolution to convert voltage of 1553 * internal voltage reference VrefInt. 1554 * Otherwise, this macro performs the processing to scale 1555 * ADC conversion data to 12 bits. 1556 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1557 * of internal voltage reference VrefInt (unit: digital value). 1558 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1559 * @arg @ref ADC_RESOLUTION_16B 1560 * @arg @ref ADC_RESOLUTION_14B 1561 * @arg @ref ADC_RESOLUTION_12B 1562 * @arg @ref ADC_RESOLUTION_10B 1563 * @arg @ref ADC_RESOLUTION_8B 1564 * @retval Analog reference voltage (unit: mV) 1565 */ 1566 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1567 __ADC_RESOLUTION__) \ 1568 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1569 (__ADC_RESOLUTION__)) 1570 1571 /** 1572 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1573 * from ADC conversion data of internal temperature sensor. 1574 * @note Computation is using temperature sensor calibration values 1575 * stored in system memory for each device during production. 1576 * @note Calculation formula: 1577 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1578 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1579 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1580 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1581 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1582 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1583 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1584 * TEMP_DEGC_CAL1 (calibrated in factory) 1585 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1586 * TEMP_DEGC_CAL2 (calibrated in factory) 1587 * Caution: Calculation relevancy under reserve that calibration 1588 * parameters are correct (address and data). 1589 * To calculate temperature using temperature sensor 1590 * datasheet typical values (generic values less, therefore 1591 * less accurate than calibrated values), 1592 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1593 * @note As calculation input, the analog reference voltage (Vref+) must be 1594 * defined as it impacts the ADC LSB equivalent voltage. 1595 * @note Analog reference voltage (Vref+) must be either known from 1596 * user board environment or can be calculated using ADC measurement 1597 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1598 * @note On this STM32 series, calibration data of temperature sensor 1599 * corresponds to a resolution of 12 bits, 1600 * this is the recommended ADC resolution to convert voltage of 1601 * temperature sensor. 1602 * Otherwise, this macro performs the processing to scale 1603 * ADC conversion data to 12 bits. 1604 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1605 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1606 * temperature sensor (unit: digital value). 1607 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1608 * sensor voltage has been measured. 1609 * This parameter can be one of the following values: 1610 * @arg @ref ADC_RESOLUTION_16B 1611 * @arg @ref ADC_RESOLUTION_14B 1612 * @arg @ref ADC_RESOLUTION_12B 1613 * @arg @ref ADC_RESOLUTION_10B 1614 * @arg @ref ADC_RESOLUTION_8B 1615 * @retval Temperature (unit: degree Celsius) 1616 */ 1617 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1618 __TEMPSENSOR_ADC_DATA__,\ 1619 __ADC_RESOLUTION__) \ 1620 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1621 (__TEMPSENSOR_ADC_DATA__),\ 1622 (__ADC_RESOLUTION__)) 1623 1624 /** 1625 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1626 * from ADC conversion data of internal temperature sensor. 1627 * @note Computation is using temperature sensor typical values 1628 * (refer to device datasheet). 1629 * @note Calculation formula: 1630 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1631 * / Avg_Slope + CALx_TEMP 1632 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1633 * (unit: digital value) 1634 * Avg_Slope = temperature sensor slope 1635 * (unit: uV/Degree Celsius) 1636 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1637 * temperature CALx_TEMP (unit: mV) 1638 * Caution: Calculation relevancy under reserve the temperature sensor 1639 * of the current device has characteristics in line with 1640 * datasheet typical values. 1641 * If temperature sensor calibration values are available on 1642 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1643 * temperature calculation will be more accurate using 1644 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1645 * @note As calculation input, the analog reference voltage (Vref+) must be 1646 * defined as it impacts the ADC LSB equivalent voltage. 1647 * @note Analog reference voltage (Vref+) must be either known from 1648 * user board environment or can be calculated using ADC measurement 1649 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1650 * @note ADC measurement data must correspond to a resolution of 12bits 1651 * (full scale digital value 4095). If not the case, the data must be 1652 * preliminarily rescaled to an equivalent resolution of 12 bits. 1653 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1654 * On STM32MP1, refer to device datasheet parameter "Avg_Slope". 1655 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1656 * On STM32MP1, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1657 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1658 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1659 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1660 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1661 * This parameter can be one of the following values: 1662 * @arg @ref ADC_RESOLUTION_16B 1663 * @arg @ref ADC_RESOLUTION_14B 1664 * @arg @ref ADC_RESOLUTION_12B 1665 * @arg @ref ADC_RESOLUTION_10B 1666 * @arg @ref ADC_RESOLUTION_8B 1667 * @retval Temperature (unit: degree Celsius) 1668 */ 1669 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1670 __TEMPSENSOR_TYP_CALX_V__,\ 1671 __TEMPSENSOR_CALX_TEMP__,\ 1672 __VREFANALOG_VOLTAGE__,\ 1673 __TEMPSENSOR_ADC_DATA__,\ 1674 __ADC_RESOLUTION__) \ 1675 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1676 (__TEMPSENSOR_TYP_CALX_V__),\ 1677 (__TEMPSENSOR_CALX_TEMP__),\ 1678 (__VREFANALOG_VOLTAGE__),\ 1679 (__TEMPSENSOR_ADC_DATA__),\ 1680 (__ADC_RESOLUTION__)) 1681 1682 /** 1683 * @} 1684 */ 1685 1686 /** 1687 * @} 1688 */ 1689 1690 /* Include ADC HAL Extended module */ 1691 #include "stm32mp1xx_hal_adc_ex.h" 1692 1693 /* Exported functions --------------------------------------------------------*/ 1694 /** @addtogroup ADC_Exported_Functions 1695 * @{ 1696 */ 1697 1698 /** @addtogroup ADC_Exported_Functions_Group1 1699 * @brief Initialization and Configuration functions 1700 * @{ 1701 */ 1702 /* Initialization and de-initialization functions ****************************/ 1703 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1704 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1705 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1706 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1707 1708 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1709 /* Callbacks Register/UnRegister functions ***********************************/ 1710 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1711 pADC_CallbackTypeDef pCallback); 1712 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1713 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1714 /** 1715 * @} 1716 */ 1717 1718 /** @addtogroup ADC_Exported_Functions_Group2 1719 * @brief IO operation functions 1720 * @{ 1721 */ 1722 /* IO operation functions *****************************************************/ 1723 1724 /* Blocking mode: Polling */ 1725 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1726 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1727 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1728 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1729 1730 /* Non-blocking mode: Interruption */ 1731 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1732 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1733 1734 /* Non-blocking mode: DMA */ 1735 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1736 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1737 1738 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1739 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1740 1741 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1742 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1743 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1744 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1745 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1746 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1747 /** 1748 * @} 1749 */ 1750 1751 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1752 * @brief Peripheral Control functions 1753 * @{ 1754 */ 1755 /* Peripheral Control functions ***********************************************/ 1756 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1757 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1758 1759 /** 1760 * @} 1761 */ 1762 1763 /* Peripheral State functions *************************************************/ 1764 /** @addtogroup ADC_Exported_Functions_Group4 1765 * @{ 1766 */ 1767 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1768 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1769 1770 /** 1771 * @} 1772 */ 1773 1774 /** 1775 * @} 1776 */ 1777 1778 /* Private functions -----------------------------------------------------------*/ 1779 /** @addtogroup ADC_Private_Functions ADC Private Functions 1780 * @{ 1781 */ 1782 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1783 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1784 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1785 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1786 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1787 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1788 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc); 1789 1790 /** 1791 * @} 1792 */ 1793 1794 /** 1795 * @} 1796 */ 1797 1798 /** 1799 * @} 1800 */ 1801 1802 #ifdef __cplusplus 1803 } 1804 #endif 1805 1806 1807 #endif /* STM32MP1xx_HAL_ADC_H */ 1808 1809 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1810