1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DAO_H 10 #define HPM_DAO_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ 15 __RW uint32_t CMD; /* 0x8: Command Register */ 16 __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ 17 __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ 18 __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ 19 __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ 20 } DAO_Type; 21 22 23 /* Bitfield definition for register: CTRL */ 24 /* 25 * HPF_EN (RW) 26 * 27 * Whether HPF is enabled. This HPF is used to filter out the DC part. 28 */ 29 #define DAO_CTRL_HPF_EN_MASK (0x20000UL) 30 #define DAO_CTRL_HPF_EN_SHIFT (17U) 31 #define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) 32 #define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) 33 34 /* 35 * MONO (RW) 36 * 37 * Asserted to let the left and right channel output the same value. 38 */ 39 #define DAO_CTRL_MONO_MASK (0x80U) 40 #define DAO_CTRL_MONO_SHIFT (7U) 41 #define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) 42 #define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) 43 44 /* 45 * RIGHT_EN (RW) 46 * 47 * Asserted to enable the right channel 48 */ 49 #define DAO_CTRL_RIGHT_EN_MASK (0x40U) 50 #define DAO_CTRL_RIGHT_EN_SHIFT (6U) 51 #define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) 52 #define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) 53 54 /* 55 * LEFT_EN (RW) 56 * 57 * Asserted to enable the left channel 58 */ 59 #define DAO_CTRL_LEFT_EN_MASK (0x20U) 60 #define DAO_CTRL_LEFT_EN_SHIFT (5U) 61 #define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) 62 #define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) 63 64 /* 65 * REMAP (RW) 66 * 67 * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative 68 * 0: Don't use remap pwm version 69 */ 70 #define DAO_CTRL_REMAP_MASK (0x10U) 71 #define DAO_CTRL_REMAP_SHIFT (4U) 72 #define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) 73 #define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) 74 75 /* 76 * INVERT (RW) 77 * 78 * all the outputs are inverted before sending to pad 79 */ 80 #define DAO_CTRL_INVERT_MASK (0x8U) 81 #define DAO_CTRL_INVERT_SHIFT (3U) 82 #define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) 83 #define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) 84 85 /* 86 * FALSE_LEVEL (RW) 87 * 88 * the pad output in False run mode, or when the module is disabled 89 * 0: all low 90 * 1: all high 91 * 2: P-high, N-low 92 * 3. output is not enabled 93 */ 94 #define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) 95 #define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) 96 #define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) 97 #define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) 98 99 /* 100 * FALSE_RUN (RW) 101 * 102 * the module continues to comsume data, but all the pads are constant, thus no audio out 103 */ 104 #define DAO_CTRL_FALSE_RUN_MASK (0x1U) 105 #define DAO_CTRL_FALSE_RUN_SHIFT (0U) 106 #define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) 107 #define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) 108 109 /* Bitfield definition for register: CMD */ 110 /* 111 * SFTRST (RW) 112 * 113 * Self-clear 114 */ 115 #define DAO_CMD_SFTRST_MASK (0x2U) 116 #define DAO_CMD_SFTRST_SHIFT (1U) 117 #define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) 118 #define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) 119 120 /* 121 * RUN (RW) 122 * 123 * Enable this module to run. 124 */ 125 #define DAO_CMD_RUN_MASK (0x1U) 126 #define DAO_CMD_RUN_SHIFT (0U) 127 #define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) 128 #define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) 129 130 /* Bitfield definition for register: RX_CFGR */ 131 /* 132 * FRAME_EDGE (RW) 133 * 134 * The start edge of a frame 135 * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) 136 * 1: Rising edge indicates a new frame 137 */ 138 #define DAO_RX_CFGR_FRAME_EDGE_MASK (0x800U) 139 #define DAO_RX_CFGR_FRAME_EDGE_SHIFT (11U) 140 #define DAO_RX_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_FRAME_EDGE_SHIFT) & DAO_RX_CFGR_FRAME_EDGE_MASK) 141 #define DAO_RX_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_FRAME_EDGE_MASK) >> DAO_RX_CFGR_FRAME_EDGE_SHIFT) 142 143 /* 144 * CH_MAX (RW) 145 * 146 * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. 147 * It must be an even number, so CH_MAX[0] is always 0. 148 * 4'h2: 2 channels 149 * 4'h4: 4 channels 150 * etc 151 */ 152 #define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) 153 #define DAO_RX_CFGR_CH_MAX_SHIFT (6U) 154 #define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) 155 #define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) 156 157 /* 158 * TDM_EN (RW) 159 * 160 * TDM mode 161 * 0: not TDM mode 162 * 1: TDM mode 163 */ 164 #define DAO_RX_CFGR_TDM_EN_MASK (0x20U) 165 #define DAO_RX_CFGR_TDM_EN_SHIFT (5U) 166 #define DAO_RX_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_TDM_EN_SHIFT) & DAO_RX_CFGR_TDM_EN_MASK) 167 #define DAO_RX_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_TDM_EN_MASK) >> DAO_RX_CFGR_TDM_EN_SHIFT) 168 169 /* 170 * STD (RW) 171 * 172 * I2S standard selection 173 * 00: I2S Philips standard. 174 * 01: MSB justified standard (left justified) 175 * 10: LSB justified standard (right justified) 176 * 11: PCM standard 177 * For more details on I2S standards. 178 * Note: For correct operation, these bits should be configured when the I2S is disabled. 179 */ 180 #define DAO_RX_CFGR_STD_MASK (0x18U) 181 #define DAO_RX_CFGR_STD_SHIFT (3U) 182 #define DAO_RX_CFGR_STD_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_STD_SHIFT) & DAO_RX_CFGR_STD_MASK) 183 #define DAO_RX_CFGR_STD_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_STD_MASK) >> DAO_RX_CFGR_STD_SHIFT) 184 185 /* 186 * DATSIZ (RW) 187 * 188 * Data length to be transferred 189 * 00: 16-bit data length 190 * 01: 24-bit data length 191 * 10: 32-bit data length 192 * 11: Not allowed 193 * Note: For correct operation, these bits should be configured when the I2S is disabled. 194 */ 195 #define DAO_RX_CFGR_DATSIZ_MASK (0x6U) 196 #define DAO_RX_CFGR_DATSIZ_SHIFT (1U) 197 #define DAO_RX_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_DATSIZ_SHIFT) & DAO_RX_CFGR_DATSIZ_MASK) 198 #define DAO_RX_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_DATSIZ_MASK) >> DAO_RX_CFGR_DATSIZ_SHIFT) 199 200 /* 201 * CHSIZ (RW) 202 * 203 * Channel length (number of bits per audio channel) 204 * 0: 16-bit wide 205 * 1: 32-bit wide 206 * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. 207 * Note: For correct operation, this bit should be configured when the I2S is disabled. 208 */ 209 #define DAO_RX_CFGR_CHSIZ_MASK (0x1U) 210 #define DAO_RX_CFGR_CHSIZ_SHIFT (0U) 211 #define DAO_RX_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CHSIZ_SHIFT) & DAO_RX_CFGR_CHSIZ_MASK) 212 #define DAO_RX_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CHSIZ_MASK) >> DAO_RX_CFGR_CHSIZ_SHIFT) 213 214 /* Bitfield definition for register: RXSLT */ 215 /* 216 * EN (RW) 217 * 218 * Slot enable for the channels. 219 */ 220 #define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) 221 #define DAO_RXSLT_EN_SHIFT (0U) 222 #define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) 223 #define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) 224 225 /* Bitfield definition for register: HPF_MA */ 226 /* 227 * COEF (RW) 228 * 229 * Composite value of coef A of the Order-1 HPF 230 */ 231 #define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) 232 #define DAO_HPF_MA_COEF_SHIFT (0U) 233 #define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) 234 #define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) 235 236 /* Bitfield definition for register: HPF_B */ 237 /* 238 * COEF (RW) 239 * 240 * coef B of the Order-1 HPF 241 */ 242 #define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) 243 #define DAO_HPF_B_COEF_SHIFT (0U) 244 #define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) 245 #define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) 246 247 248 249 250 #endif /* HPM_DAO_H */ 251