1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PLLCTL_H 10 #define HPM_PLLCTL_H 11 12 typedef struct { 13 __RW uint32_t XTAL; /* 0x0: Crystal control and status */ 14 __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ 15 struct { 16 __RW uint32_t CFG0; /* 0x80: PLLx config0 */ 17 __RW uint32_t CFG1; /* 0x84: PLLx config1 */ 18 __RW uint32_t CFG2; /* 0x88: PLLx config2 */ 19 __RW uint32_t FREQ; /* 0x8C: PLLx frac mode frequency adjust */ 20 __RW uint32_t LOCK; /* 0x90: PLLx lock control */ 21 __R uint8_t RESERVED0[12]; /* 0x94 - 0x9F: Reserved */ 22 __R uint32_t STATUS; /* 0xA0: PLLx status */ 23 __R uint8_t RESERVED1[28]; /* 0xA4 - 0xBF: Reserved */ 24 __RW uint32_t DIV0; /* 0xC0: PLLx divider0 control */ 25 __RW uint32_t DIV1; /* 0xC4: PLLx divider1 control */ 26 __R uint8_t RESERVED2[56]; /* 0xC8 - 0xFF: Reserved */ 27 } PLL[5]; 28 } PLLCTL_Type; 29 30 31 /* Bitfield definition for register: XTAL */ 32 /* 33 * RESPONSE (RO) 34 * 35 * Crystal oscillator status 36 * 0: Oscillator is not stable 37 * 1: Oscillator is stable for use 38 */ 39 #define PLLCTL_XTAL_RESPONSE_MASK (0x20000000UL) 40 #define PLLCTL_XTAL_RESPONSE_SHIFT (29U) 41 #define PLLCTL_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RESPONSE_MASK) >> PLLCTL_XTAL_RESPONSE_SHIFT) 42 43 /* 44 * ENABLE (RO) 45 * 46 * Crystal oscillator enable status 47 * 0: Oscillator is off 48 * 1: Oscillator is on 49 */ 50 #define PLLCTL_XTAL_ENABLE_MASK (0x10000000UL) 51 #define PLLCTL_XTAL_ENABLE_SHIFT (28U) 52 #define PLLCTL_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_ENABLE_MASK) >> PLLCTL_XTAL_ENABLE_SHIFT) 53 54 /* 55 * RAMP_TIME (RW) 56 * 57 * Rampup time of XTAL oscillator in cycles of IRC24M clock 58 * 0: 0 cycle 59 * 1: 1 cycle 60 * 2: 2 cycle 61 * 1048575: 1048575 cycles 62 */ 63 #define PLLCTL_XTAL_RAMP_TIME_MASK (0xFFFFFUL) 64 #define PLLCTL_XTAL_RAMP_TIME_SHIFT (0U) 65 #define PLLCTL_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTL_XTAL_RAMP_TIME_SHIFT) & PLLCTL_XTAL_RAMP_TIME_MASK) 66 #define PLLCTL_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RAMP_TIME_MASK) >> PLLCTL_XTAL_RAMP_TIME_SHIFT) 67 68 /* Bitfield definition for register of struct array PLL: CFG0 */ 69 /* 70 * SS_RSTPTR (RW) 71 * 72 * reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb 73 */ 74 #define PLLCTL_PLL_CFG0_SS_RSTPTR_MASK (0x80000000UL) 75 #define PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT (31U) 76 #define PLLCTL_PLL_CFG0_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) 77 #define PLLCTL_PLL_CFG0_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) >> PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) 78 79 /* 80 * REFDIV (RW) 81 * 82 * refclk diverder, lock when lock_en[24]&~pll_ana_pd 83 */ 84 #define PLLCTL_PLL_CFG0_REFDIV_MASK (0x3F000000UL) 85 #define PLLCTL_PLL_CFG0_REFDIV_SHIFT (24U) 86 #define PLLCTL_PLL_CFG0_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_REFDIV_SHIFT) & PLLCTL_PLL_CFG0_REFDIV_MASK) 87 #define PLLCTL_PLL_CFG0_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_REFDIV_MASK) >> PLLCTL_PLL_CFG0_REFDIV_SHIFT) 88 89 /* 90 * POSTDIV1 (RW) 91 * 92 * lock when lock_en[20]&~pll_ana_pd 93 */ 94 #define PLLCTL_PLL_CFG0_POSTDIV1_MASK (0x700000UL) 95 #define PLLCTL_PLL_CFG0_POSTDIV1_SHIFT (20U) 96 #define PLLCTL_PLL_CFG0_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) 97 #define PLLCTL_PLL_CFG0_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) 98 99 /* 100 * SS_SPREAD (RW) 101 * 102 * lock when lock_en[14]&~pll_ana_pd 103 */ 104 #define PLLCTL_PLL_CFG0_SS_SPREAD_MASK (0x7C000UL) 105 #define PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT (14U) 106 #define PLLCTL_PLL_CFG0_SS_SPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) 107 #define PLLCTL_PLL_CFG0_SS_SPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) 108 109 /* 110 * SS_DIVVAL (RW) 111 * 112 * sscg divval, lock when lock_en[8]&~pll_ana_pd 113 */ 114 #define PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (0x3F00U) 115 #define PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (8U) 116 #define PLLCTL_PLL_CFG0_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) 117 #define PLLCTL_PLL_CFG0_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) 118 119 /* 120 * SS_DOWNSPREAD (RW) 121 * 122 * Downspread control 123 * 1’b0 –> Center-Spread 124 * 1’b1 –> Downspread 125 */ 126 #define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK (0x80U) 127 #define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT (7U) 128 #define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) 129 #define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) 130 131 /* 132 * SS_RESET (RW) 133 * 134 */ 135 #define PLLCTL_PLL_CFG0_SS_RESET_MASK (0x40U) 136 #define PLLCTL_PLL_CFG0_SS_RESET_SHIFT (6U) 137 #define PLLCTL_PLL_CFG0_SS_RESET_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK) 138 #define PLLCTL_PLL_CFG0_SS_RESET_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_PLL_CFG0_SS_RESET_SHIFT) 139 140 /* 141 * SS_DISABLE_SSCG (RW) 142 * 143 */ 144 #define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK (0x20U) 145 #define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT (5U) 146 #define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) 147 #define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >> PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) 148 149 /* 150 * DSMPD (RW) 151 * 152 * 1: int mode; 0: frac mode 153 */ 154 #define PLLCTL_PLL_CFG0_DSMPD_MASK (0x8U) 155 #define PLLCTL_PLL_CFG0_DSMPD_SHIFT (3U) 156 #define PLLCTL_PLL_CFG0_DSMPD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_DSMPD_SHIFT) & PLLCTL_PLL_CFG0_DSMPD_MASK) 157 #define PLLCTL_PLL_CFG0_DSMPD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_DSMPD_MASK) >> PLLCTL_PLL_CFG0_DSMPD_SHIFT) 158 159 /* Bitfield definition for register of struct array PLL: CFG1 */ 160 /* 161 * PLLCTRL_HW_EN (RW) 162 * 163 * 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value 164 * 0: full software control PLL settings 165 */ 166 #define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK (0x80000000UL) 167 #define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT (31U) 168 #define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) 169 #define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) >> PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) 170 171 /* 172 * CLKEN_SW (RW) 173 * 174 * the clock enable used to gate pll output, should be set after lock, and clear before power down pll. 175 * pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; 176 */ 177 #define PLLCTL_PLL_CFG1_CLKEN_SW_MASK (0x4000000UL) 178 #define PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT (26U) 179 #define PLLCTL_PLL_CFG1_CLKEN_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) 180 #define PLLCTL_PLL_CFG1_CLKEN_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) >> PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) 181 182 /* 183 * PLLPD_SW (RW) 184 * 185 * pll power down. 186 * pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; 187 * pll_pd_soc is just delay of soc enable, for soc to control pll on/off; 188 * pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence 189 */ 190 #define PLLCTL_PLL_CFG1_PLLPD_SW_MASK (0x2000000UL) 191 #define PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT (25U) 192 #define PLLCTL_PLL_CFG1_PLLPD_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) 193 #define PLLCTL_PLL_CFG1_PLLPD_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) >> PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) 194 195 /* 196 * LOCK_CNT_CFG (RW) 197 * 198 * used to wait lock if set larger than lock time; 199 * default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 200 */ 201 #define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK (0x8000U) 202 #define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT (15U) 203 #define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) 204 #define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) >> PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) 205 206 /* Bitfield definition for register of struct array PLL: CFG2 */ 207 /* 208 * FBDIV_INT (RW) 209 * 210 * fbdiv used in int mode 211 */ 212 #define PLLCTL_PLL_CFG2_FBDIV_INT_MASK (0xFFFU) 213 #define PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT (0U) 214 #define PLLCTL_PLL_CFG2_FBDIV_INT_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) 215 #define PLLCTL_PLL_CFG2_FBDIV_INT_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) 216 217 /* Bitfield definition for register of struct array PLL: FREQ */ 218 /* 219 * FRAC (RW) 220 * 221 * PLL output frequency is : 222 * Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 223 * for default refdiv=1 and postdiv1=1, 24MHz refclk 224 * Fout is 24*fbdiv in int mode 225 * if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) 226 * Fout is 24*fbdiv in int mode 227 * if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) 228 */ 229 #define PLLCTL_PLL_FREQ_FRAC_MASK (0xFFFFFF00UL) 230 #define PLLCTL_PLL_FREQ_FRAC_SHIFT (8U) 231 #define PLLCTL_PLL_FREQ_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FRAC_MASK) 232 #define PLLCTL_PLL_FREQ_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FRAC_MASK) >> PLLCTL_PLL_FREQ_FRAC_SHIFT) 233 234 /* 235 * FBDIV_FRAC (RW) 236 * 237 * fbdiv used in frac mode 238 */ 239 #define PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK (0xFFU) 240 #define PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT (0U) 241 #define PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) 242 #define PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) 243 244 /* Bitfield definition for register of struct array PLL: LOCK */ 245 /* 246 * LOCK_SS_RSTPTR (RW) 247 * 248 * lock bit of field ss_rstptr 249 * 0: field is open foe software to change 250 * 1: field is locked, not changeable 251 */ 252 #define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK (0x80000000UL) 253 #define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT (31U) 254 #define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) 255 #define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) 256 257 /* 258 * LOCK_REFDIV (RW) 259 * 260 * lock bit of field refdiv 261 * 0: field is open foe software to change 262 * 1: field is locked, not changeable 263 */ 264 #define PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK (0x1000000UL) 265 #define PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT (24U) 266 #define PLLCTL_PLL_LOCK_LOCK_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) 267 #define PLLCTL_PLL_LOCK_LOCK_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) >> PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) 268 269 /* 270 * LOCK_POSTDIV1 (RW) 271 * 272 * lock bit of field postdiv1 273 * 0: field is open foe software to change 274 * 1: field is locked, not changeable 275 */ 276 #define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK (0x100000UL) 277 #define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT (20U) 278 #define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) 279 #define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) >> PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) 280 281 /* 282 * LOCK_SS_SPEAD (RW) 283 * 284 * lock bit of field ss_spead 285 * 0: field is open foe software to change 286 * 1: field is locked, not changeable 287 */ 288 #define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK (0x4000U) 289 #define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT (14U) 290 #define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) 291 #define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) 292 293 /* 294 * LOCK_SS_DIVVAL (RW) 295 * 296 * lock bit of field ss_divval 297 * 0: field is open foe software to change 298 * 1: field is locked, not changeable 299 */ 300 #define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK (0x100U) 301 #define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT (8U) 302 #define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) 303 #define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) 304 305 /* Bitfield definition for register of struct array PLL: STATUS */ 306 /* 307 * ENABLE (RO) 308 * 309 * enable from SYSCTL block 310 */ 311 #define PLLCTL_PLL_STATUS_ENABLE_MASK (0x8000000UL) 312 #define PLLCTL_PLL_STATUS_ENABLE_SHIFT (27U) 313 #define PLLCTL_PLL_STATUS_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_ENABLE_MASK) >> PLLCTL_PLL_STATUS_ENABLE_SHIFT) 314 315 /* 316 * RESPONSE (RO) 317 * 318 * response to SYSCTL, PLL is power down when both enable and response are 0. 319 */ 320 #define PLLCTL_PLL_STATUS_RESPONSE_MASK (0x4U) 321 #define PLLCTL_PLL_STATUS_RESPONSE_SHIFT (2U) 322 #define PLLCTL_PLL_STATUS_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_RESPONSE_MASK) >> PLLCTL_PLL_STATUS_RESPONSE_SHIFT) 323 324 /* 325 * PLL_LOCK_COMB (RO) 326 * 327 */ 328 #define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK (0x2U) 329 #define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT (1U) 330 #define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT) 331 332 /* 333 * PLL_LOCK_SYNC (RO) 334 * 335 */ 336 #define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK (0x1U) 337 #define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT (0U) 338 #define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT) 339 340 /* Bitfield definition for register of struct array PLL: DIV0 */ 341 /* 342 * BUSY (RO) 343 * 344 * Busy flag 345 * 0: divider is working 346 * 1: divider is changing status 347 */ 348 #define PLLCTL_PLL_DIV0_BUSY_MASK (0x80000000UL) 349 #define PLLCTL_PLL_DIV0_BUSY_SHIFT (31U) 350 #define PLLCTL_PLL_DIV0_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_BUSY_MASK) >> PLLCTL_PLL_DIV0_BUSY_SHIFT) 351 352 /* 353 * RESPONSE (RO) 354 * 355 * Crystal oscillator status 356 * 0: Oscillator is not stable 357 * 1: Oscillator is stable for use 358 */ 359 #define PLLCTL_PLL_DIV0_RESPONSE_MASK (0x20000000UL) 360 #define PLLCTL_PLL_DIV0_RESPONSE_SHIFT (29U) 361 #define PLLCTL_PLL_DIV0_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_RESPONSE_MASK) >> PLLCTL_PLL_DIV0_RESPONSE_SHIFT) 362 363 /* 364 * ENABLE (RO) 365 * 366 * Crystal oscillator enable status 367 * 0: Oscillator is off 368 * 1: Oscillator is on 369 */ 370 #define PLLCTL_PLL_DIV0_ENABLE_MASK (0x10000000UL) 371 #define PLLCTL_PLL_DIV0_ENABLE_SHIFT (28U) 372 #define PLLCTL_PLL_DIV0_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_ENABLE_MASK) >> PLLCTL_PLL_DIV0_ENABLE_SHIFT) 373 374 /* 375 * DIV (RW) 376 * 377 * Divider 378 * 0: divide by 1 379 * 1: divide by2 380 * . . . 381 * 255: divide by 256 382 */ 383 #define PLLCTL_PLL_DIV0_DIV_MASK (0xFFU) 384 #define PLLCTL_PLL_DIV0_DIV_SHIFT (0U) 385 #define PLLCTL_PLL_DIV0_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV0_DIV_SHIFT) & PLLCTL_PLL_DIV0_DIV_MASK) 386 #define PLLCTL_PLL_DIV0_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_DIV_MASK) >> PLLCTL_PLL_DIV0_DIV_SHIFT) 387 388 /* Bitfield definition for register of struct array PLL: DIV1 */ 389 /* 390 * BUSY (RO) 391 * 392 * Busy flag 393 * 0: divider is working 394 * 1: divider is changing status 395 */ 396 #define PLLCTL_PLL_DIV1_BUSY_MASK (0x80000000UL) 397 #define PLLCTL_PLL_DIV1_BUSY_SHIFT (31U) 398 #define PLLCTL_PLL_DIV1_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_BUSY_MASK) >> PLLCTL_PLL_DIV1_BUSY_SHIFT) 399 400 /* 401 * RESPONSE (RO) 402 * 403 * Crystal oscillator status 404 * 0: Oscillator is not stable 405 * 1: Oscillator is stable for use 406 */ 407 #define PLLCTL_PLL_DIV1_RESPONSE_MASK (0x20000000UL) 408 #define PLLCTL_PLL_DIV1_RESPONSE_SHIFT (29U) 409 #define PLLCTL_PLL_DIV1_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_RESPONSE_MASK) >> PLLCTL_PLL_DIV1_RESPONSE_SHIFT) 410 411 /* 412 * ENABLE (RO) 413 * 414 * Crystal oscillator enable status 415 * 0: Oscillator is off 416 * 1: Oscillator is on 417 */ 418 #define PLLCTL_PLL_DIV1_ENABLE_MASK (0x10000000UL) 419 #define PLLCTL_PLL_DIV1_ENABLE_SHIFT (28U) 420 #define PLLCTL_PLL_DIV1_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_ENABLE_MASK) >> PLLCTL_PLL_DIV1_ENABLE_SHIFT) 421 422 /* 423 * DIV (RW) 424 * 425 * Divider 426 * 0: divide by 1 427 * 1: divide by2 428 * . . . 429 * 255: divide by 256 430 */ 431 #define PLLCTL_PLL_DIV1_DIV_MASK (0xFFU) 432 #define PLLCTL_PLL_DIV1_DIV_SHIFT (0U) 433 #define PLLCTL_PLL_DIV1_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV1_DIV_SHIFT) & PLLCTL_PLL_DIV1_DIV_MASK) 434 #define PLLCTL_PLL_DIV1_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_DIV_MASK) >> PLLCTL_PLL_DIV1_DIV_SHIFT) 435 436 437 438 /* PLL register group index macro definition */ 439 #define PLLCTL_PLL_PLL0 (0UL) 440 #define PLLCTL_PLL_PLL1 (1UL) 441 #define PLLCTL_PLL_PLL2 (2UL) 442 #define PLLCTL_PLL_PLL3 (3UL) 443 #define PLLCTL_PLL_PLL4 (4UL) 444 445 446 #endif /* HPM_PLLCTL_H */ 447