1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DMAV2_H 10 #define HPM_DMAV2_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ 14 __R uint32_t IDMISC; /* 0x4: ID Misc */ 15 __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ 16 __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ 17 __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ 18 __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ 19 __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ 20 __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ 21 __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ 22 __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ 23 __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ 24 __R uint32_t CHEN; /* 0x34: Channel Enable Register */ 25 __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ 26 struct { 27 __RW uint32_t CTRL; /* 0x40: Channel Control Register */ 28 __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ 29 __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ 30 __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ 31 __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ 32 __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */ 33 __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ 34 __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ 35 } CHCTRL[32]; 36 } DMAV2_Type; 37 38 39 /* Bitfield definition for register: IDMISC */ 40 /* 41 * DMASTATE (RO) 42 * 43 * DMA state machine 44 * localparam ST_IDLE = 3'b000; 45 * localparam ST_READ = 3'b001; 46 * localparam ST_READ_ACK = 3'b010; 47 * localparam ST_WRITE = 3'b011; 48 * localparam ST_WRITE_ACK = 3'b100; 49 * localparam ST_LL = 3'b101; 50 * localparam ST_END = 3'b110; 51 * localparam ST_END_WAIT = 3'b111; 52 */ 53 #define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) 54 #define DMAV2_IDMISC_DMASTATE_SHIFT (13U) 55 #define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) 56 57 /* 58 * CURCHAN (RO) 59 * 60 * current channel in used 61 */ 62 #define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) 63 #define DMAV2_IDMISC_CURCHAN_SHIFT (8U) 64 #define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) 65 66 /* Bitfield definition for register: DMACFG */ 67 /* 68 * CHAINXFR (RO) 69 * 70 * Chain transfer 71 * 0x0: Chain transfer is not configured 72 * 0x1: Chain transfer is configured 73 */ 74 #define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) 75 #define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) 76 #define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) 77 78 /* 79 * REQSYNC (RO) 80 * 81 * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, 82 * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 83 * 0x0: Request synchronization is not configured 84 * 0x1: Request synchronization is configured 85 */ 86 #define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) 87 #define DMAV2_DMACFG_REQSYNC_SHIFT (30U) 88 #define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) 89 90 /* 91 * DATAWIDTH (RO) 92 * 93 * AXI bus data width 94 * 0x0: 32 bits 95 * 0x1: 64 bits 96 * 0x2: 128 bits 97 * 0x3: 256 bits 98 */ 99 #define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) 100 #define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) 101 #define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) 102 103 /* 104 * ADDRWIDTH (RO) 105 * 106 * AXI bus address width 107 * 0x18: 24 bits 108 * 0x19: 25 bits 109 * ... 110 * 0x40: 64 bits 111 * Others: Invalid 112 */ 113 #define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) 114 #define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) 115 #define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) 116 117 /* 118 * CORENUM (RO) 119 * 120 * DMA core number 121 * 0x0: 1 core 122 * 0x1: 2 cores 123 */ 124 #define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) 125 #define DMAV2_DMACFG_CORENUM_SHIFT (16U) 126 #define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) 127 128 /* 129 * BUSNUM (RO) 130 * 131 * AXI bus interface number 132 * 0x0: 1 AXI bus 133 * 0x1: 2 AXI busses 134 */ 135 #define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) 136 #define DMAV2_DMACFG_BUSNUM_SHIFT (15U) 137 #define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) 138 139 /* 140 * REQNUM (RO) 141 * 142 * Request/acknowledge pair number 143 * 0x0: 0 pair 144 * 0x1: 1 pair 145 * 0x2: 2 pairs 146 * ... 147 * 0x10: 16 pairs 148 */ 149 #define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) 150 #define DMAV2_DMACFG_REQNUM_SHIFT (10U) 151 #define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) 152 153 /* 154 * FIFODEPTH (RO) 155 * 156 * FIFO depth 157 * 0x4: 4 entries 158 * 0x8: 8 entries 159 * 0x10: 16 entries 160 * 0x20: 32 entries 161 * Others: Invalid 162 */ 163 #define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) 164 #define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) 165 #define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) 166 167 /* 168 * CHANNELNUM (RO) 169 * 170 * Channel number 171 * 0x1: 1 channel 172 * 0x2: 2 channels 173 * ... 174 * 0x8: 8 channels 175 * Others: Invalid 176 */ 177 #define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) 178 #define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) 179 #define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) 180 181 /* Bitfield definition for register: DMACTRL */ 182 /* 183 * RESET (WO) 184 * 185 * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. 186 * Note: The software reset may cause the in-completion of AXI transaction. 187 */ 188 #define DMAV2_DMACTRL_RESET_MASK (0x1U) 189 #define DMAV2_DMACTRL_RESET_SHIFT (0U) 190 #define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) 191 #define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) 192 193 /* Bitfield definition for register: CHABORT */ 194 /* 195 * CHABORT (WO) 196 * 197 * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. 198 * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) 199 */ 200 #define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) 201 #define DMAV2_CHABORT_CHABORT_SHIFT (0U) 202 #define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) 203 #define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) 204 205 /* Bitfield definition for register: INTHALFSTS */ 206 /* 207 * STS (RW) 208 * 209 * half transfer done irq status 210 */ 211 #define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) 212 #define DMAV2_INTHALFSTS_STS_SHIFT (0U) 213 #define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) 214 #define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) 215 216 /* Bitfield definition for register: INTTCSTS */ 217 /* 218 * STS (W1C) 219 * 220 * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 221 * 0x0: Channel n has no terminal count status 222 * 0x1: Channel n has terminal count status 223 */ 224 #define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) 225 #define DMAV2_INTTCSTS_STS_SHIFT (0U) 226 #define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) 227 #define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) 228 229 /* Bitfield definition for register: INTABORTSTS */ 230 /* 231 * STS (W1C) 232 * 233 * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 234 * 0x0: Channel n has no abort status 235 * 0x1: Channel n has abort status 236 */ 237 #define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) 238 #define DMAV2_INTABORTSTS_STS_SHIFT (0U) 239 #define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) 240 #define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) 241 242 /* Bitfield definition for register: INTERRSTS */ 243 /* 244 * STS (W1C) 245 * 246 * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: 247 * - Bus error 248 * - Unaligned address 249 * - Unaligned transfer width 250 * - Reserved configuration 251 * 0x0: Channel n has no error status 252 * 0x1: Channel n has error status 253 */ 254 #define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) 255 #define DMAV2_INTERRSTS_STS_SHIFT (0U) 256 #define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) 257 #define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) 258 259 /* Bitfield definition for register: CHEN */ 260 /* 261 * CHEN (RO) 262 * 263 * Alias of the Enable field of all ChnCtrl registers 264 */ 265 #define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) 266 #define DMAV2_CHEN_CHEN_SHIFT (0U) 267 #define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) 268 269 /* Bitfield definition for register of struct array CHCTRL: CTRL */ 270 /* 271 * INFINITELOOP (RW) 272 * 273 * set to loop current config infinitely 274 */ 275 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) 276 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) 277 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) 278 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) 279 280 /* 281 * HANDSHAKEOPT (RW) 282 * 283 * 0: one request to transfer one burst 284 * 1: one request to transfer all the data defined in ch_tts 285 */ 286 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) 287 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) 288 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) 289 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) 290 291 /* 292 * PRIORITY (RW) 293 * 294 * Channel priority level 295 * 0x0: Lower priority 296 * 0x1: Higher priority 297 */ 298 #define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) 299 #define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) 300 #define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) 301 #define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) 302 303 /* 304 * BURSTOPT (RW) 305 * 306 * set to change burst_size definition 307 */ 308 #define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) 309 #define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) 310 #define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) 311 #define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) 312 313 /* 314 * SRCBURSTSIZE (RW) 315 * 316 * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. 317 * The burst transfer byte number is (SrcBurstSize * SrcWidth). 318 * 0x0: 1 transfer 319 * 0x1: 2 transfers 320 * 0x2: 4 transfers 321 * 0x3: 8 transfers 322 * 0x4: 16 transfers 323 * 0x5: 32 transfers 324 * 0x6: 64 transfers 325 * 0x7: 128 transfers 326 * 0x8: 256 transfers 327 * 0x9:512 transfers 328 * 0xa: 1024 transfers 329 * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception 330 */ 331 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) 332 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) 333 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) 334 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) 335 336 /* 337 * SRCWIDTH (RW) 338 * 339 * Source transfer width 340 * 0x0: Byte transfer 341 * 0x1: Half-word transfer 342 * 0x2: Word transfer 343 * 0x3: Double word transfer 344 * 0x4: Quad word transfer 345 * 0x5: Eight word transfer 346 * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 347 */ 348 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) 349 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) 350 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) 351 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) 352 353 /* 354 * DSTWIDTH (RW) 355 * 356 * Destination transfer width. 357 * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. 358 * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. 359 * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 360 * 0x0: Byte transfer 361 * 0x1: Half-word transfer 362 * 0x2: Word transfer 363 * 0x3: Double word transfer 364 * 0x4: Quad word transfer 365 * 0x5: Eight word transfer 366 * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception 367 */ 368 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) 369 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) 370 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) 371 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) 372 373 /* 374 * SRCMODE (RW) 375 * 376 * Source DMA handshake mode 377 * 0x0: Normal mode 378 * 0x1: Handshake mode 379 * Normal mode is enabled and started by software set Enable bit; 380 * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block 381 */ 382 #define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) 383 #define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) 384 #define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) 385 #define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) 386 387 /* 388 * DSTMODE (RW) 389 * 390 * Destination DMA handshake mode 391 * 0x0: Normal mode 392 * 0x1: Handshake mode 393 * the difference bewteen Source/Destination handshake mode is: 394 * the dma block will response hardware request after read in Source handshake mode; 395 * the dma block will response hardware request after write in Destination handshake mode; 396 * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. 397 */ 398 #define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) 399 #define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) 400 #define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) 401 #define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) 402 403 /* 404 * SRCADDRCTRL (RW) 405 * 406 * Source address control 407 * 0x0: Increment address 408 * 0x1: Decrement address 409 * 0x2: Fixed address 410 * 0x3: Reserved, setting the field with this value triggers the error exception 411 */ 412 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) 413 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) 414 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) 415 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) 416 417 /* 418 * DSTADDRCTRL (RW) 419 * 420 * Destination address control 421 * 0x0: Increment address 422 * 0x1: Decrement address 423 * 0x2: Fixed address 424 * 0x3: Reserved, setting the field with this value triggers the error exception 425 */ 426 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) 427 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) 428 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) 429 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) 430 431 /* 432 * INTHALFCNTMASK (RW) 433 * 434 * Channel half interrupt mask 435 * 0x0: Allow the half interrupt to be triggered 436 * 0x1: Disable the half interrupt 437 */ 438 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) 439 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) 440 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) 441 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) 442 443 /* 444 * INTABTMASK (RW) 445 * 446 * Channel abort interrupt mask 447 * 0x0: Allow the abort interrupt to be triggered 448 * 0x1: Disable the abort interrupt 449 */ 450 #define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) 451 #define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) 452 #define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) 453 #define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) 454 455 /* 456 * INTERRMASK (RW) 457 * 458 * Channel error interrupt mask 459 * 0x0: Allow the error interrupt to be triggered 460 * 0x1: Disable the error interrupt 461 */ 462 #define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) 463 #define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) 464 #define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) 465 #define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) 466 467 /* 468 * INTTCMASK (RW) 469 * 470 * Channel terminal count interrupt mask 471 * 0x0: Allow the terminal count interrupt to be triggered 472 * 0x1: Disable the terminal count interrupt 473 */ 474 #define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) 475 #define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) 476 #define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) 477 #define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) 478 479 /* 480 * ENABLE (RW) 481 * 482 * Channel enable bit 483 * 0x0: Disable 484 * 0x1: Enable 485 */ 486 #define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) 487 #define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) 488 #define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) 489 #define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) 490 491 /* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ 492 /* 493 * TRANSIZE (RW) 494 * 495 * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. 496 * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 497 */ 498 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) 499 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) 500 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) 501 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) 502 503 /* Bitfield definition for register of struct array CHCTRL: SRCADDR */ 504 /* 505 * SRCADDRL (RW) 506 * 507 * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. 508 * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 509 */ 510 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) 511 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) 512 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) 513 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) 514 515 /* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ 516 /* 517 * SRCREQSEL (RW) 518 * 519 * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 520 */ 521 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) 522 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) 523 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) 524 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) 525 526 /* 527 * DSTREQSEL (RW) 528 * 529 * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 530 */ 531 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) 532 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) 533 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) 534 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) 535 536 /* Bitfield definition for register of struct array CHCTRL: DSTADDR */ 537 /* 538 * DSTADDRL (RW) 539 * 540 * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. 541 * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 542 */ 543 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) 544 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) 545 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) 546 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) 547 548 /* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ 549 /* 550 * LLPOINTERL (RW) 551 * 552 * Low part of the pointer to the next descriptor. The pointer must be double word aligned. 553 */ 554 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) 555 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) 556 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) 557 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) 558 559 560 561 /* CHCTRL register group index macro definition */ 562 #define DMAV2_CHCTRL_CH0 (0UL) 563 #define DMAV2_CHCTRL_CH1 (1UL) 564 #define DMAV2_CHCTRL_CH2 (2UL) 565 #define DMAV2_CHCTRL_CH3 (3UL) 566 #define DMAV2_CHCTRL_CH4 (4UL) 567 #define DMAV2_CHCTRL_CH5 (5UL) 568 #define DMAV2_CHCTRL_CH6 (6UL) 569 #define DMAV2_CHCTRL_CH7 (7UL) 570 #define DMAV2_CHCTRL_CH8 (8UL) 571 #define DMAV2_CHCTRL_CH9 (9UL) 572 #define DMAV2_CHCTRL_CH10 (10UL) 573 #define DMAV2_CHCTRL_CH11 (11UL) 574 #define DMAV2_CHCTRL_CH12 (12UL) 575 #define DMAV2_CHCTRL_CH13 (13UL) 576 #define DMAV2_CHCTRL_CH14 (14UL) 577 #define DMAV2_CHCTRL_CH15 (15UL) 578 #define DMAV2_CHCTRL_CH16 (16UL) 579 #define DMAV2_CHCTRL_CH17 (17UL) 580 #define DMAV2_CHCTRL_CH18 (18UL) 581 #define DMAV2_CHCTRL_CH19 (19UL) 582 #define DMAV2_CHCTRL_CH20 (20UL) 583 #define DMAV2_CHCTRL_CH21 (21UL) 584 #define DMAV2_CHCTRL_CH22 (22UL) 585 #define DMAV2_CHCTRL_CH23 (23UL) 586 #define DMAV2_CHCTRL_CH24 (24UL) 587 #define DMAV2_CHCTRL_CH25 (25UL) 588 #define DMAV2_CHCTRL_CH26 (26UL) 589 #define DMAV2_CHCTRL_CH27 (27UL) 590 #define DMAV2_CHCTRL_CH28 (28UL) 591 #define DMAV2_CHCTRL_CH29 (29UL) 592 #define DMAV2_CHCTRL_CH30 (30UL) 593 #define DMAV2_CHCTRL_CH31 (31UL) 594 595 596 #endif /* HPM_DMAV2_H */ 597