1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DMA_H 10 #define HPM_DMA_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ 14 __R uint32_t IDMISC; /* 0x4: ID Misc */ 15 __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ 16 __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ 17 __R uint8_t RESERVED2[12]; /* 0x14 - 0x1F: Reserved */ 18 __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ 19 __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ 20 __R uint8_t RESERVED3[8]; /* 0x28 - 0x2F: Reserved */ 21 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ 22 __R uint32_t CHEN; /* 0x34: Channel Enable Register */ 23 __R uint8_t RESERVED4[8]; /* 0x38 - 0x3F: Reserved */ 24 struct { 25 __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ 26 __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ 27 __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ 28 __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ 29 __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ 30 __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ 31 __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ 32 __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ 33 } CHCTRL[8]; 34 } DMA_Type; 35 36 37 /* Bitfield definition for register: IDMISC */ 38 /* 39 * IDLE_FLAG (RO) 40 * 41 * DMA Idle Flag 42 * 0 - DMA is busy 43 * 1 - DMA is dile 44 */ 45 #define DMA_IDMISC_IDLE_FLAG_MASK (0x8000U) 46 #define DMA_IDMISC_IDLE_FLAG_SHIFT (15U) 47 #define DMA_IDMISC_IDLE_FLAG_GET(x) (((uint32_t)(x) & DMA_IDMISC_IDLE_FLAG_MASK) >> DMA_IDMISC_IDLE_FLAG_SHIFT) 48 49 /* Bitfield definition for register: DMACFG */ 50 /* 51 * CHAINXFR (RO) 52 * 53 * Chain transfer 54 * 0x0: Chain transfer is not configured 55 * 0x1: Chain transfer is configured 56 */ 57 #define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) 58 #define DMA_DMACFG_CHAINXFR_SHIFT (31U) 59 #define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) 60 61 /* 62 * REQSYNC (RO) 63 * 64 * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 65 * 0x0: Request synchronization is not configured 66 * 0x1: Request synchronization is configured 67 */ 68 #define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) 69 #define DMA_DMACFG_REQSYNC_SHIFT (30U) 70 #define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) 71 72 /* 73 * DATAWIDTH (RO) 74 * 75 * AXI bus data width 76 * 0x0: 32 bits 77 * 0x1: 64 bits 78 * 0x2: 128 bits 79 * 0x3: 256 bits 80 */ 81 #define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) 82 #define DMA_DMACFG_DATAWIDTH_SHIFT (24U) 83 #define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) 84 85 /* 86 * ADDRWIDTH (RO) 87 * 88 * AXI bus address width 89 * 0x18: 24 bits 90 * 0x19: 25 bits 91 * ... 92 * 0x40: 64 bits 93 * Others: Invalid 94 */ 95 #define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) 96 #define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) 97 #define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) 98 99 /* 100 * CORENUM (RO) 101 * 102 * DMA core number 103 * 0x0: 1 core 104 * 0x1: 2 cores 105 */ 106 #define DMA_DMACFG_CORENUM_MASK (0x10000UL) 107 #define DMA_DMACFG_CORENUM_SHIFT (16U) 108 #define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) 109 110 /* 111 * BUSNUM (RO) 112 * 113 * AXI bus interface number 114 * 0x0: 1 AXI bus 115 * 0x1: 2 AXI busses 116 */ 117 #define DMA_DMACFG_BUSNUM_MASK (0x8000U) 118 #define DMA_DMACFG_BUSNUM_SHIFT (15U) 119 #define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) 120 121 /* 122 * REQNUM (RO) 123 * 124 * Request/acknowledge pair number 125 * 0x0: 0 pair 126 * 0x1: 1 pair 127 * 0x2: 2 pairs 128 * ... 129 * 0x10: 16 pairs 130 */ 131 #define DMA_DMACFG_REQNUM_MASK (0x7C00U) 132 #define DMA_DMACFG_REQNUM_SHIFT (10U) 133 #define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) 134 135 /* 136 * FIFODEPTH (RO) 137 * 138 * FIFO depth 139 * 0x4: 4 entries 140 * 0x8: 8 entries 141 * 0x10: 16 entries 142 * 0x20: 32 entries 143 * Others: Invalid 144 */ 145 #define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) 146 #define DMA_DMACFG_FIFODEPTH_SHIFT (4U) 147 #define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) 148 149 /* 150 * CHANNELNUM (RO) 151 * 152 * Channel number 153 * 0x1: 1 channel 154 * 0x2: 2 channels 155 * ... 156 * 0x8: 8 channels 157 * Others: Invalid 158 */ 159 #define DMA_DMACFG_CHANNELNUM_MASK (0xFU) 160 #define DMA_DMACFG_CHANNELNUM_SHIFT (0U) 161 #define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) 162 163 /* Bitfield definition for register: DMACTRL */ 164 /* 165 * RESET (WO) 166 * 167 * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. 168 * Note: The software reset may cause the in-completion of AXI transaction. 169 */ 170 #define DMA_DMACTRL_RESET_MASK (0x1U) 171 #define DMA_DMACTRL_RESET_SHIFT (0U) 172 #define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) 173 #define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) 174 175 /* Bitfield definition for register: CHABORT */ 176 /* 177 * CHABORT (WO) 178 * 179 * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) 180 */ 181 #define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) 182 #define DMA_CHABORT_CHABORT_SHIFT (0U) 183 #define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) 184 #define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) 185 186 /* Bitfield definition for register: INTSTATUS */ 187 /* 188 * TC (W1C) 189 * 190 * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 191 * 0x0: Channel n has no terminal count status 192 * 0x1: Channel n has terminal count status 193 */ 194 #define DMA_INTSTATUS_TC_MASK (0xFF0000UL) 195 #define DMA_INTSTATUS_TC_SHIFT (16U) 196 #define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) 197 #define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) 198 199 /* 200 * ABORT (W1C) 201 * 202 * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 203 * 0x0: Channel n has no abort status 204 * 0x1: Channel n has abort status 205 */ 206 #define DMA_INTSTATUS_ABORT_MASK (0xFF00U) 207 #define DMA_INTSTATUS_ABORT_SHIFT (8U) 208 #define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) 209 #define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) 210 211 /* 212 * ERROR (W1C) 213 * 214 * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: 215 * - Bus error 216 * - Unaligned address 217 * - Unaligned transfer width 218 * - Reserved configuration 219 * 0x0: Channel n has no error status 220 * 0x1: Channel n has error status 221 */ 222 #define DMA_INTSTATUS_ERROR_MASK (0xFFU) 223 #define DMA_INTSTATUS_ERROR_SHIFT (0U) 224 #define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) 225 #define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) 226 227 /* Bitfield definition for register: CHEN */ 228 /* 229 * CHEN (RO) 230 * 231 * Alias of the Enable field of all ChnCtrl registers 232 */ 233 #define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) 234 #define DMA_CHEN_CHEN_SHIFT (0U) 235 #define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) 236 237 /* Bitfield definition for register of struct array CHCTRL: CTRL */ 238 /* 239 * SRCBUSINFIDX (RW) 240 * 241 * Bus interface index that source data is read from 242 * 0x0: Data is read from bus interface 0 243 * 0x1: Data is read from bus interface 244 */ 245 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) 246 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) 247 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) 248 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) 249 250 /* 251 * DSTBUSINFIDX (RW) 252 * 253 * Bus interface index that destination data is written to 254 * 0x0: Data is written to bus interface 0 255 * 0x1: Data is written to bus interface 1 256 */ 257 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) 258 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) 259 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) 260 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) 261 262 /* 263 * PRIORITY (RW) 264 * 265 * Channel priority level 266 * 0x0: Lower priority 267 * 0x1: Higher priority 268 */ 269 #define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) 270 #define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) 271 #define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) 272 #define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) 273 274 /* 275 * SRCBURSTSIZE (RW) 276 * 277 * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. 278 * The burst transfer byte number is (SrcBurstSize * SrcWidth). 279 * 0x0: 1 transfer 280 * 0x1: 2 transfers 281 * 0x2: 4 transfers 282 * 0x3: 8 transfers 283 * 0x4: 16 transfers 284 * 0x5: 32 transfers 285 * 0x6: 64 transfers 286 * 0x7: 128 transfers 287 * 0x8: 256 transfers 288 * 0x9:512 transfers 289 * 0xa: 1024 transfers 290 * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception 291 * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 292 */ 293 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) 294 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) 295 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) 296 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) 297 298 /* 299 * SRCWIDTH (RW) 300 * 301 * Source transfer width 302 * 0x0: Byte transfer 303 * 0x1: Half-word transfer 304 * 0x2: Word transfer 305 * 0x3: Double word transfer 306 * 0x4: Quad word transfer 307 * 0x5: Eight word transfer 308 * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception 309 * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 310 */ 311 #define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) 312 #define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) 313 #define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) 314 #define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) 315 316 /* 317 * DSTWIDTH (RW) 318 * 319 * Destination transfer width. 320 * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. 321 * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 322 * 0x0: Byte transfer 323 * 0x1: Half-word transfer 324 * 0x2: Word transfer 325 * 0x3: Double word transfer 326 * 0x4: Quad word transfer 327 * 0x5: Eight word transfer 328 * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception 329 * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 330 */ 331 #define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) 332 #define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) 333 #define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) 334 #define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) 335 336 /* 337 * SRCMODE (RW) 338 * 339 * Source DMA handshake mode 340 * 0x0: Normal mode 341 * 0x1: Handshake mode 342 */ 343 #define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) 344 #define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) 345 #define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) 346 #define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) 347 348 /* 349 * DSTMODE (RW) 350 * 351 * Destination DMA handshake mode 352 * 0x0: Normal mode 353 * 0x1: Handshake mode 354 */ 355 #define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) 356 #define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) 357 #define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) 358 #define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) 359 360 /* 361 * SRCADDRCTRL (RW) 362 * 363 * Source address control 364 * 0x0: Increment address 365 * 0x1: Decrement address 366 * 0x2: Fixed address 367 * 0x3: Reserved, setting the field with this value triggers the error exception 368 */ 369 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) 370 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) 371 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) 372 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) 373 374 /* 375 * DSTADDRCTRL (RW) 376 * 377 * Destination address control 378 * 0x0: Increment address 379 * 0x1: Decrement address 380 * 0x2: Fixed address 381 * 0x3: Reserved, setting the field with this value triggers the error exception 382 */ 383 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) 384 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) 385 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) 386 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) 387 388 /* 389 * SRCREQSEL (RW) 390 * 391 * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 392 */ 393 #define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) 394 #define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) 395 #define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) 396 #define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) 397 398 /* 399 * DSTREQSEL (RW) 400 * 401 * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 402 */ 403 #define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) 404 #define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) 405 #define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) 406 #define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) 407 408 /* 409 * INTABTMASK (RW) 410 * 411 * Channel abort interrupt mask 412 * 0x0: Allow the abort interrupt to be triggered 413 * 0x1: Disable the abort interrupt 414 */ 415 #define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) 416 #define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) 417 #define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) 418 #define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) 419 420 /* 421 * INTERRMASK (RW) 422 * 423 * Channel error interrupt mask 424 * 0x0: Allow the error interrupt to be triggered 425 * 0x1: Disable the error interrupt 426 */ 427 #define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) 428 #define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) 429 #define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) 430 #define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) 431 432 /* 433 * INTTCMASK (RW) 434 * 435 * Channel terminal count interrupt mask 436 * 0x0: Allow the terminal count interrupt to be triggered 437 * 0x1: Disable the terminal count interrupt 438 */ 439 #define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) 440 #define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) 441 #define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) 442 #define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) 443 444 /* 445 * ENABLE (RW) 446 * 447 * Channel enable bit 448 * 0x0: Disable 449 * 0x1: Enable 450 */ 451 #define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) 452 #define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) 453 #define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) 454 #define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) 455 456 /* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ 457 /* 458 * TRANSIZE (RW) 459 * 460 * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. 461 * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 462 */ 463 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) 464 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) 465 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) 466 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) 467 468 /* Bitfield definition for register of struct array CHCTRL: SRCADDR */ 469 /* 470 * SRCADDRL (RW) 471 * 472 * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. 473 * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 474 */ 475 #define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) 476 #define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) 477 #define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) 478 #define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) 479 480 /* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ 481 /* 482 * SRCADDRH (RW) 483 * 484 * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. 485 * This register exists only when the address bus width is wider than 32 bits. 486 */ 487 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) 488 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) 489 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) 490 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) 491 492 /* Bitfield definition for register of struct array CHCTRL: DSTADDR */ 493 /* 494 * DSTADDRL (RW) 495 * 496 * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. 497 * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 498 */ 499 #define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) 500 #define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) 501 #define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) 502 #define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) 503 504 /* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ 505 /* 506 * DSTADDRH (RW) 507 * 508 * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. 509 * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 510 * This register exists only when the address bus width is wider than 32 bits. 511 */ 512 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) 513 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) 514 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) 515 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) 516 517 /* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ 518 /* 519 * LLPOINTERL (RW) 520 * 521 * Low part of the pointer to the next descriptor. The pointer must be double word aligned. 522 */ 523 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) 524 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) 525 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) 526 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) 527 528 /* 529 * LLDBUSINFIDX (RW) 530 * 531 * Bus interface index that the next descriptor is read from 532 * 0x0: The next descriptor is read from bus interface 0 533 */ 534 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) 535 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) 536 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) 537 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) 538 539 /* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ 540 /* 541 * LLPOINTERH (RW) 542 * 543 * High part of the pointer to the next descriptor. 544 * This register exists only when the address bus width is wider than 32 bits. 545 */ 546 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) 547 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) 548 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) 549 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) 550 551 552 553 /* CHCTRL register group index macro definition */ 554 #define DMA_CHCTRL_CH0 (0UL) 555 #define DMA_CHCTRL_CH1 (1UL) 556 #define DMA_CHCTRL_CH2 (2UL) 557 #define DMA_CHCTRL_CH3 (3UL) 558 #define DMA_CHCTRL_CH4 (4UL) 559 #define DMA_CHCTRL_CH5 (5UL) 560 #define DMA_CHCTRL_CH6 (6UL) 561 #define DMA_CHCTRL_CH7 (7UL) 562 563 564 #endif /* HPM_DMA_H */ 565