1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_nor.c
4 * @author MCD Application Team
5 * @brief NOR HAL module driver.
6 * This file provides a generic firmware to drive NOR memories mounted
7 * as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
16 with NOR devices. This driver is used as follows:
17
18 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
19 with control and timing parameters for both normal and extended mode.
20
21 (+) Read NOR flash memory manufacturer code and device IDs using the function
22 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
23 structure declared by the function caller.
24
25 (+) Access NOR flash memory by read/write data unit operations using the functions
26 HAL_NOR_Read(), HAL_NOR_Program().
27
28 (+) Perform NOR flash erase block/chip operations using the functions
29 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
30
31 (+) Read the NOR flash CFI (common flash interface) IDs using the function
32 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
33 structure declared by the function caller.
34
35 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
36 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
37
38 (+) You can monitor the NOR device HAL state by calling the function
39 HAL_NOR_GetState()
40 [..]
41 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
42 If a NOR flash device contains different operations and/or implementations,
43 it should be implemented separately.
44
45 *** NOR HAL driver macros list ***
46 =============================================
47 [..]
48 Below the list of most used macros in NOR HAL driver.
49
50 (+) NOR_WRITE : NOR memory write data to specified address
51
52 *** Callback registration ***
53 =============================================
54 [..]
55 The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
56 allows the user to configure dynamically the driver callbacks.
57
58 Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
59 it allows to register following callbacks:
60 (+) MspInitCallback : NOR MspInit.
61 (+) MspDeInitCallback : NOR MspDeInit.
62 This function takes as parameters the HAL peripheral handle, the Callback ID
63 and a pointer to the user callback function.
64
65 Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
66 weak (surcharged) function. It allows to reset following callbacks:
67 (+) MspInitCallback : NOR MspInit.
68 (+) MspDeInitCallback : NOR MspDeInit.
69 This function) takes as parameters the HAL peripheral handle and the Callback ID.
70
71 By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
72 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
73 Exception done for MspInit and MspDeInit callbacks that are respectively
74 reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
75 and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
76 If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
77 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
78
79 Callbacks can be registered/unregistered in READY state only.
80 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
81 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
82 during the Init/DeInit.
83 In that case first register the MspInit/MspDeInit user callbacks
84 using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
85 or @ref HAL_NOR_Init function.
86
87 When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
88 not defined, the callback registering feature is not available
89 and weak (surcharged) callbacks are used.
90
91 @endverbatim
92 ******************************************************************************
93 * @attention
94 *
95 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
96 * All rights reserved.</center></h2>
97 *
98 * This software component is licensed by ST under BSD 3-Clause license,
99 * the "License"; You may not use this file except in compliance with the
100 * License. You may obtain a copy of the License at:
101 * opensource.org/licenses/BSD-3-Clause
102 *
103 ******************************************************************************
104 */
105
106 /* Includes ------------------------------------------------------------------*/
107 #include "stm32f4xx_hal.h"
108
109 /** @addtogroup STM32F4xx_HAL_Driver
110 * @{
111 */
112
113 /** @defgroup NOR NOR
114 * @brief NOR driver modules
115 * @{
116 */
117 #ifdef HAL_NOR_MODULE_ENABLED
118 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
119 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
120 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
121 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
122 /* Private typedef -----------------------------------------------------------*/
123 /* Private define ------------------------------------------------------------*/
124
125 /** @defgroup NOR_Private_Defines NOR Private Defines
126 * @{
127 */
128
129 /* Constants to define address to set to write a command */
130 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
131 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
132 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
133 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
134 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
135 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
136 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
137
138 /* Constants to define data to program a command */
139 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
140 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
141 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
142 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
143 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
144 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
145 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
146 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
147 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
148 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
149
150 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
151 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
152 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
153
154 /* Mask on NOR STATUS REGISTER */
155 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
156 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
157
158 /**
159 * @}
160 */
161
162 /* Private macro -------------------------------------------------------------*/
163 /* Private variables ---------------------------------------------------------*/
164 /** @defgroup NOR_Private_Variables NOR Private Variables
165 * @{
166 */
167
168 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
169
170 /**
171 * @}
172 */
173
174 /* Private functions ---------------------------------------------------------*/
175 /* Exported functions --------------------------------------------------------*/
176 /** @defgroup NOR_Exported_Functions NOR Exported Functions
177 * @{
178 */
179
180 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
181 * @brief Initialization and Configuration functions
182 *
183 @verbatim
184 ==============================================================================
185 ##### NOR Initialization and de_initialization functions #####
186 ==============================================================================
187 [..]
188 This section provides functions allowing to initialize/de-initialize
189 the NOR memory
190
191 @endverbatim
192 * @{
193 */
194
195 /**
196 * @brief Perform the NOR memory Initialization sequence
197 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
198 * the configuration information for NOR module.
199 * @param Timing pointer to NOR control timing structure
200 * @param ExtTiming pointer to NOR extended mode timing structure
201 * @retval HAL status
202 */
HAL_NOR_Init(NOR_HandleTypeDef * hnor,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)203 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
204 {
205 /* Check the NOR handle parameter */
206 if(hnor == NULL)
207 {
208 return HAL_ERROR;
209 }
210
211 if(hnor->State == HAL_NOR_STATE_RESET)
212 {
213 /* Allocate lock resource and initialize it */
214 hnor->Lock = HAL_UNLOCKED;
215
216 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
217 if(hnor->MspInitCallback == NULL)
218 {
219 hnor->MspInitCallback = HAL_NOR_MspInit;
220 }
221
222 /* Init the low level hardware */
223 hnor->MspInitCallback(hnor);
224 #else
225 /* Initialize the low level hardware (MSP) */
226 HAL_NOR_MspInit(hnor);
227 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
228 }
229
230 /* Initialize NOR control Interface */
231 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
232
233 /* Initialize NOR timing Interface */
234 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
235
236 /* Initialize NOR extended mode timing Interface */
237 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
238
239 /* Enable the NORSRAM device */
240 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
241
242 /* Initialize NOR Memory Data Width*/
243 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
244 {
245 uwNORMemoryDataWidth = NOR_MEMORY_8B;
246 }
247 else
248 {
249 uwNORMemoryDataWidth = NOR_MEMORY_16B;
250 }
251
252 /* Check the NOR controller state */
253 hnor->State = HAL_NOR_STATE_READY;
254
255 return HAL_OK;
256 }
257
258 /**
259 * @brief Perform NOR memory De-Initialization sequence
260 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
261 * the configuration information for NOR module.
262 * @retval HAL status
263 */
HAL_NOR_DeInit(NOR_HandleTypeDef * hnor)264 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
265 {
266 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
267 if(hnor->MspDeInitCallback == NULL)
268 {
269 hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
270 }
271
272 /* DeInit the low level hardware */
273 hnor->MspDeInitCallback(hnor);
274 #else
275 /* De-Initialize the low level hardware (MSP) */
276 HAL_NOR_MspDeInit(hnor);
277 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
278
279 /* Configure the NOR registers with their reset values */
280 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
281
282 /* Update the NOR controller state */
283 hnor->State = HAL_NOR_STATE_RESET;
284
285 /* Release Lock */
286 __HAL_UNLOCK(hnor);
287
288 return HAL_OK;
289 }
290
291 /**
292 * @brief NOR MSP Init
293 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
294 * the configuration information for NOR module.
295 * @retval None
296 */
HAL_NOR_MspInit(NOR_HandleTypeDef * hnor)297 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
298 {
299 /* Prevent unused argument(s) compilation warning */
300 UNUSED(hnor);
301 /* NOTE : This function Should not be modified, when the callback is needed,
302 the HAL_NOR_MspInit could be implemented in the user file
303 */
304 }
305
306 /**
307 * @brief NOR MSP DeInit
308 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
309 * the configuration information for NOR module.
310 * @retval None
311 */
HAL_NOR_MspDeInit(NOR_HandleTypeDef * hnor)312 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
313 {
314 /* Prevent unused argument(s) compilation warning */
315 UNUSED(hnor);
316 /* NOTE : This function Should not be modified, when the callback is needed,
317 the HAL_NOR_MspDeInit could be implemented in the user file
318 */
319 }
320
321 /**
322 * @brief NOR MSP Wait for Ready/Busy signal
323 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
324 * the configuration information for NOR module.
325 * @param Timeout Maximum timeout value
326 * @retval None
327 */
HAL_NOR_MspWait(NOR_HandleTypeDef * hnor,uint32_t Timeout)328 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
329 {
330 /* Prevent unused argument(s) compilation warning */
331 UNUSED(hnor);
332 UNUSED(Timeout);
333
334 /* NOTE : This function Should not be modified, when the callback is needed,
335 the HAL_NOR_MspWait could be implemented in the user file
336 */
337 }
338
339 /**
340 * @}
341 */
342
343 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
344 * @brief Input Output and memory control functions
345 *
346 @verbatim
347 ==============================================================================
348 ##### NOR Input and Output functions #####
349 ==============================================================================
350 [..]
351 This section provides functions allowing to use and control the NOR memory
352
353 @endverbatim
354 * @{
355 */
356
357 /**
358 * @brief Read NOR flash IDs
359 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
360 * the configuration information for NOR module.
361 * @param pNOR_ID pointer to NOR ID structure
362 * @retval HAL status
363 */
HAL_NOR_Read_ID(NOR_HandleTypeDef * hnor,NOR_IDTypeDef * pNOR_ID)364 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
365 {
366 uint32_t deviceaddress = 0U;
367
368 /* Process Locked */
369 __HAL_LOCK(hnor);
370
371 /* Check the NOR controller state */
372 if(hnor->State == HAL_NOR_STATE_BUSY)
373 {
374 return HAL_BUSY;
375 }
376
377 /* Select the NOR device address */
378 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
379 {
380 deviceaddress = NOR_MEMORY_ADRESS1;
381 }
382 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
383 {
384 deviceaddress = NOR_MEMORY_ADRESS2;
385 }
386 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
387 {
388 deviceaddress = NOR_MEMORY_ADRESS3;
389 }
390 else /* FMC_NORSRAM_BANK4 */
391 {
392 deviceaddress = NOR_MEMORY_ADRESS4;
393 }
394
395 /* Update the NOR controller state */
396 hnor->State = HAL_NOR_STATE_BUSY;
397
398 /* Send read ID command */
399 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
400 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
401 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
402
403 /* Read the NOR IDs */
404 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
405 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
406 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
407 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
408
409 /* Check the NOR controller state */
410 hnor->State = HAL_NOR_STATE_READY;
411
412 /* Process unlocked */
413 __HAL_UNLOCK(hnor);
414
415 return HAL_OK;
416 }
417
418 /**
419 * @brief Returns the NOR memory to Read mode.
420 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
421 * the configuration information for NOR module.
422 * @retval HAL status
423 */
HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef * hnor)424 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
425 {
426 uint32_t deviceaddress = 0U;
427
428 /* Process Locked */
429 __HAL_LOCK(hnor);
430
431 /* Check the NOR controller state */
432 if(hnor->State == HAL_NOR_STATE_BUSY)
433 {
434 return HAL_BUSY;
435 }
436
437 /* Select the NOR device address */
438 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
439 {
440 deviceaddress = NOR_MEMORY_ADRESS1;
441 }
442 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
443 {
444 deviceaddress = NOR_MEMORY_ADRESS2;
445 }
446 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
447 {
448 deviceaddress = NOR_MEMORY_ADRESS3;
449 }
450 else /* FMC_NORSRAM_BANK4 */
451 {
452 deviceaddress = NOR_MEMORY_ADRESS4;
453 }
454
455 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
456
457 /* Check the NOR controller state */
458 hnor->State = HAL_NOR_STATE_READY;
459
460 /* Process unlocked */
461 __HAL_UNLOCK(hnor);
462
463 return HAL_OK;
464 }
465
466 /**
467 * @brief Read data from NOR memory
468 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
469 * the configuration information for NOR module.
470 * @param pAddress pointer to Device address
471 * @param pData pointer to read data
472 * @retval HAL status
473 */
HAL_NOR_Read(NOR_HandleTypeDef * hnor,uint32_t * pAddress,uint16_t * pData)474 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
475 {
476 uint32_t deviceaddress = 0U;
477
478 /* Process Locked */
479 __HAL_LOCK(hnor);
480
481 /* Check the NOR controller state */
482 if(hnor->State == HAL_NOR_STATE_BUSY)
483 {
484 return HAL_BUSY;
485 }
486
487 /* Select the NOR device address */
488 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
489 {
490 deviceaddress = NOR_MEMORY_ADRESS1;
491 }
492 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
493 {
494 deviceaddress = NOR_MEMORY_ADRESS2;
495 }
496 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
497 {
498 deviceaddress = NOR_MEMORY_ADRESS3;
499 }
500 else /* FMC_NORSRAM_BANK4 */
501 {
502 deviceaddress = NOR_MEMORY_ADRESS4;
503 }
504
505 /* Update the NOR controller state */
506 hnor->State = HAL_NOR_STATE_BUSY;
507
508 /* Send read data command */
509 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
510 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
511 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
512
513 /* Read the data */
514 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
515
516 /* Check the NOR controller state */
517 hnor->State = HAL_NOR_STATE_READY;
518
519 /* Process unlocked */
520 __HAL_UNLOCK(hnor);
521
522 return HAL_OK;
523 }
524
525 /**
526 * @brief Program data to NOR memory
527 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
528 * the configuration information for NOR module.
529 * @param pAddress Device address
530 * @param pData pointer to the data to write
531 * @retval HAL status
532 */
HAL_NOR_Program(NOR_HandleTypeDef * hnor,uint32_t * pAddress,uint16_t * pData)533 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
534 {
535 uint32_t deviceaddress = 0U;
536
537 /* Process Locked */
538 __HAL_LOCK(hnor);
539
540 /* Check the NOR controller state */
541 if(hnor->State == HAL_NOR_STATE_BUSY)
542 {
543 return HAL_BUSY;
544 }
545
546 /* Select the NOR device address */
547 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
548 {
549 deviceaddress = NOR_MEMORY_ADRESS1;
550 }
551 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
552 {
553 deviceaddress = NOR_MEMORY_ADRESS2;
554 }
555 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
556 {
557 deviceaddress = NOR_MEMORY_ADRESS3;
558 }
559 else /* FMC_NORSRAM_BANK4 */
560 {
561 deviceaddress = NOR_MEMORY_ADRESS4;
562 }
563
564 /* Update the NOR controller state */
565 hnor->State = HAL_NOR_STATE_BUSY;
566
567 /* Send program data command */
568 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
569 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
570 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
571
572 /* Write the data */
573 NOR_WRITE(pAddress, *pData);
574
575 /* Check the NOR controller state */
576 hnor->State = HAL_NOR_STATE_READY;
577
578 /* Process unlocked */
579 __HAL_UNLOCK(hnor);
580
581 return HAL_OK;
582 }
583
584 /**
585 * @brief Reads a half-word buffer from the NOR memory.
586 * @param hnor pointer to the NOR handle
587 * @param uwAddress NOR memory internal address to read from.
588 * @param pData pointer to the buffer that receives the data read from the
589 * NOR memory.
590 * @param uwBufferSize number of Half word to read.
591 * @retval HAL status
592 */
HAL_NOR_ReadBuffer(NOR_HandleTypeDef * hnor,uint32_t uwAddress,uint16_t * pData,uint32_t uwBufferSize)593 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
594 {
595 uint32_t deviceaddress = 0U;
596
597 /* Process Locked */
598 __HAL_LOCK(hnor);
599
600 /* Check the NOR controller state */
601 if(hnor->State == HAL_NOR_STATE_BUSY)
602 {
603 return HAL_BUSY;
604 }
605
606 /* Select the NOR device address */
607 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
608 {
609 deviceaddress = NOR_MEMORY_ADRESS1;
610 }
611 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
612 {
613 deviceaddress = NOR_MEMORY_ADRESS2;
614 }
615 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
616 {
617 deviceaddress = NOR_MEMORY_ADRESS3;
618 }
619 else /* FMC_NORSRAM_BANK4 */
620 {
621 deviceaddress = NOR_MEMORY_ADRESS4;
622 }
623
624 /* Update the NOR controller state */
625 hnor->State = HAL_NOR_STATE_BUSY;
626
627 /* Send read data command */
628 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
629 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
630 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
631
632 /* Read buffer */
633 while( uwBufferSize > 0U)
634 {
635 *pData++ = *(__IO uint16_t *)uwAddress;
636 uwAddress += 2U;
637 uwBufferSize--;
638 }
639
640 /* Check the NOR controller state */
641 hnor->State = HAL_NOR_STATE_READY;
642
643 /* Process unlocked */
644 __HAL_UNLOCK(hnor);
645
646 return HAL_OK;
647 }
648
649 /**
650 * @brief Writes a half-word buffer to the NOR memory. This function must be used
651 only with S29GL128P NOR memory.
652 * @param hnor pointer to the NOR handle
653 * @param uwAddress NOR memory internal start write address
654 * @param pData pointer to source data buffer.
655 * @param uwBufferSize Size of the buffer to write
656 * @retval HAL status
657 */
HAL_NOR_ProgramBuffer(NOR_HandleTypeDef * hnor,uint32_t uwAddress,uint16_t * pData,uint32_t uwBufferSize)658 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
659 {
660 uint16_t * p_currentaddress = (uint16_t *)NULL;
661 uint16_t * p_endaddress = (uint16_t *)NULL;
662 uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
663
664 /* Process Locked */
665 __HAL_LOCK(hnor);
666
667 /* Check the NOR controller state */
668 if(hnor->State == HAL_NOR_STATE_BUSY)
669 {
670 return HAL_BUSY;
671 }
672
673 /* Select the NOR device address */
674 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
675 {
676 deviceaddress = NOR_MEMORY_ADRESS1;
677 }
678 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
679 {
680 deviceaddress = NOR_MEMORY_ADRESS2;
681 }
682 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
683 {
684 deviceaddress = NOR_MEMORY_ADRESS3;
685 }
686 else /* FMC_NORSRAM_BANK4 */
687 {
688 deviceaddress = NOR_MEMORY_ADRESS4;
689 }
690
691 /* Update the NOR controller state */
692 hnor->State = HAL_NOR_STATE_BUSY;
693
694 /* Initialize variables */
695 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
696 p_endaddress = p_currentaddress + (uwBufferSize-1U);
697 lastloadedaddress = (uint32_t)(uwAddress);
698
699 /* Issue unlock command sequence */
700 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
701 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
702
703 /* Write Buffer Load Command */
704 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
705 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U));
706
707 /* Load Data into NOR Buffer */
708 while(p_currentaddress <= p_endaddress)
709 {
710 /* Store last loaded address & data value (for polling) */
711 lastloadedaddress = (uint32_t)p_currentaddress;
712
713 NOR_WRITE(p_currentaddress, *pData++);
714
715 p_currentaddress ++;
716 }
717
718 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
719
720 /* Check the NOR controller state */
721 hnor->State = HAL_NOR_STATE_READY;
722
723 /* Process unlocked */
724 __HAL_UNLOCK(hnor);
725
726 return HAL_OK;
727
728 }
729
730 /**
731 * @brief Erase the specified block of the NOR memory
732 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
733 * the configuration information for NOR module.
734 * @param BlockAddress Block to erase address
735 * @param Address Device address
736 * @retval HAL status
737 */
HAL_NOR_Erase_Block(NOR_HandleTypeDef * hnor,uint32_t BlockAddress,uint32_t Address)738 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
739 {
740 uint32_t deviceaddress = 0U;
741
742 /* Process Locked */
743 __HAL_LOCK(hnor);
744
745 /* Check the NOR controller state */
746 if(hnor->State == HAL_NOR_STATE_BUSY)
747 {
748 return HAL_BUSY;
749 }
750
751 /* Select the NOR device address */
752 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
753 {
754 deviceaddress = NOR_MEMORY_ADRESS1;
755 }
756 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
757 {
758 deviceaddress = NOR_MEMORY_ADRESS2;
759 }
760 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
761 {
762 deviceaddress = NOR_MEMORY_ADRESS3;
763 }
764 else /* FMC_NORSRAM_BANK4 */
765 {
766 deviceaddress = NOR_MEMORY_ADRESS4;
767 }
768
769 /* Update the NOR controller state */
770 hnor->State = HAL_NOR_STATE_BUSY;
771
772 /* Send block erase command sequence */
773 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
774 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
775 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
776 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
777 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
778 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
779
780 /* Check the NOR memory status and update the controller state */
781 hnor->State = HAL_NOR_STATE_READY;
782
783 /* Process unlocked */
784 __HAL_UNLOCK(hnor);
785
786 return HAL_OK;
787
788 }
789
790 /**
791 * @brief Erase the entire NOR chip.
792 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
793 * the configuration information for NOR module.
794 * @param Address Device address
795 * @retval HAL status
796 */
HAL_NOR_Erase_Chip(NOR_HandleTypeDef * hnor,uint32_t Address)797 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
798 {
799 uint32_t deviceaddress = 0U;
800
801 /* Prevent unused argument(s) compilation warning */
802 UNUSED(Address);
803
804 /* Process Locked */
805 __HAL_LOCK(hnor);
806
807 /* Check the NOR controller state */
808 if(hnor->State == HAL_NOR_STATE_BUSY)
809 {
810 return HAL_BUSY;
811 }
812
813 /* Select the NOR device address */
814 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
815 {
816 deviceaddress = NOR_MEMORY_ADRESS1;
817 }
818 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
819 {
820 deviceaddress = NOR_MEMORY_ADRESS2;
821 }
822 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
823 {
824 deviceaddress = NOR_MEMORY_ADRESS3;
825 }
826 else /* FMC_NORSRAM_BANK4 */
827 {
828 deviceaddress = NOR_MEMORY_ADRESS4;
829 }
830
831 /* Update the NOR controller state */
832 hnor->State = HAL_NOR_STATE_BUSY;
833
834 /* Send NOR chip erase command sequence */
835 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
836 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
837 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
838 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
839 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
840 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
841
842 /* Check the NOR memory status and update the controller state */
843 hnor->State = HAL_NOR_STATE_READY;
844
845 /* Process unlocked */
846 __HAL_UNLOCK(hnor);
847
848 return HAL_OK;
849 }
850
851 /**
852 * @brief Read NOR flash CFI IDs
853 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
854 * the configuration information for NOR module.
855 * @param pNOR_CFI pointer to NOR CFI IDs structure
856 * @retval HAL status
857 */
HAL_NOR_Read_CFI(NOR_HandleTypeDef * hnor,NOR_CFITypeDef * pNOR_CFI)858 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
859 {
860 uint32_t deviceaddress = 0U;
861
862 /* Process Locked */
863 __HAL_LOCK(hnor);
864
865 /* Check the NOR controller state */
866 if(hnor->State == HAL_NOR_STATE_BUSY)
867 {
868 return HAL_BUSY;
869 }
870
871 /* Select the NOR device address */
872 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
873 {
874 deviceaddress = NOR_MEMORY_ADRESS1;
875 }
876 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
877 {
878 deviceaddress = NOR_MEMORY_ADRESS2;
879 }
880 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
881 {
882 deviceaddress = NOR_MEMORY_ADRESS3;
883 }
884 else /* FMC_NORSRAM_BANK4 */
885 {
886 deviceaddress = NOR_MEMORY_ADRESS4;
887 }
888
889 /* Update the NOR controller state */
890 hnor->State = HAL_NOR_STATE_BUSY;
891
892 /* Send read CFI query command */
893 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
894
895 /* read the NOR CFI information */
896 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
897 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
898 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
899 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
900
901 /* Check the NOR controller state */
902 hnor->State = HAL_NOR_STATE_READY;
903
904 /* Process unlocked */
905 __HAL_UNLOCK(hnor);
906
907 return HAL_OK;
908 }
909
910 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
911 /**
912 * @brief Register a User NOR Callback
913 * To be used instead of the weak (surcharged) predefined callback
914 * @param hnor : NOR handle
915 * @param CallbackId : ID of the callback to be registered
916 * This parameter can be one of the following values:
917 * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
918 * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
919 * @param pCallback : pointer to the Callback function
920 * @retval status
921 */
HAL_NOR_RegisterCallback(NOR_HandleTypeDef * hnor,HAL_NOR_CallbackIDTypeDef CallbackId,pNOR_CallbackTypeDef pCallback)922 HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
923 {
924 HAL_StatusTypeDef status = HAL_OK;
925 HAL_NOR_StateTypeDef state;
926
927 if(pCallback == NULL)
928 {
929 return HAL_ERROR;
930 }
931
932 /* Process locked */
933 __HAL_LOCK(hnor);
934
935 state = hnor->State;
936 if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
937 {
938 switch (CallbackId)
939 {
940 case HAL_NOR_MSP_INIT_CB_ID :
941 hnor->MspInitCallback = pCallback;
942 break;
943 case HAL_NOR_MSP_DEINIT_CB_ID :
944 hnor->MspDeInitCallback = pCallback;
945 break;
946 default :
947 /* update return status */
948 status = HAL_ERROR;
949 break;
950 }
951 }
952 else
953 {
954 /* update return status */
955 status = HAL_ERROR;
956 }
957
958 /* Release Lock */
959 __HAL_UNLOCK(hnor);
960 return status;
961 }
962
963 /**
964 * @brief Unregister a User NOR Callback
965 * NOR Callback is redirected to the weak (surcharged) predefined callback
966 * @param hnor : NOR handle
967 * @param CallbackId : ID of the callback to be unregistered
968 * This parameter can be one of the following values:
969 * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
970 * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
971 * @retval status
972 */
HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef * hnor,HAL_NOR_CallbackIDTypeDef CallbackId)973 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
974 {
975 HAL_StatusTypeDef status = HAL_OK;
976 HAL_NOR_StateTypeDef state;
977
978 /* Process locked */
979 __HAL_LOCK(hnor);
980
981 state = hnor->State;
982 if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
983 {
984 switch (CallbackId)
985 {
986 case HAL_NOR_MSP_INIT_CB_ID :
987 hnor->MspInitCallback = HAL_NOR_MspInit;
988 break;
989 case HAL_NOR_MSP_DEINIT_CB_ID :
990 hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
991 break;
992 default :
993 /* update return status */
994 status = HAL_ERROR;
995 break;
996 }
997 }
998 else
999 {
1000 /* update return status */
1001 status = HAL_ERROR;
1002 }
1003
1004 /* Release Lock */
1005 __HAL_UNLOCK(hnor);
1006 return status;
1007 }
1008 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
1014 * @brief management functions
1015 *
1016 @verbatim
1017 ==============================================================================
1018 ##### NOR Control functions #####
1019 ==============================================================================
1020 [..]
1021 This subsection provides a set of functions allowing to control dynamically
1022 the NOR interface.
1023
1024 @endverbatim
1025 * @{
1026 */
1027
1028 /**
1029 * @brief Enables dynamically NOR write operation.
1030 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
1031 * the configuration information for NOR module.
1032 * @retval HAL status
1033 */
HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef * hnor)1034 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
1035 {
1036 /* Process Locked */
1037 __HAL_LOCK(hnor);
1038
1039 /* Enable write operation */
1040 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
1041
1042 /* Update the NOR controller state */
1043 hnor->State = HAL_NOR_STATE_READY;
1044
1045 /* Process unlocked */
1046 __HAL_UNLOCK(hnor);
1047
1048 return HAL_OK;
1049 }
1050
1051 /**
1052 * @brief Disables dynamically NOR write operation.
1053 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
1054 * the configuration information for NOR module.
1055 * @retval HAL status
1056 */
HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef * hnor)1057 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
1058 {
1059 /* Process Locked */
1060 __HAL_LOCK(hnor);
1061
1062 /* Update the SRAM controller state */
1063 hnor->State = HAL_NOR_STATE_BUSY;
1064
1065 /* Disable write operation */
1066 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
1067
1068 /* Update the NOR controller state */
1069 hnor->State = HAL_NOR_STATE_PROTECTED;
1070
1071 /* Process unlocked */
1072 __HAL_UNLOCK(hnor);
1073
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
1082 * @brief Peripheral State functions
1083 *
1084 @verbatim
1085 ==============================================================================
1086 ##### NOR State functions #####
1087 ==============================================================================
1088 [..]
1089 This subsection permits to get in run-time the status of the NOR controller
1090 and the data flow.
1091
1092 @endverbatim
1093 * @{
1094 */
1095
1096 /**
1097 * @brief return the NOR controller state
1098 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
1099 * the configuration information for NOR module.
1100 * @retval NOR controller state
1101 */
HAL_NOR_GetState(NOR_HandleTypeDef * hnor)1102 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
1103 {
1104 return hnor->State;
1105 }
1106
1107 /**
1108 * @brief Returns the NOR operation status.
1109 * @param hnor pointer to a NOR_HandleTypeDef structure that contains
1110 * the configuration information for NOR module.
1111 * @param Address Device address
1112 * @param Timeout NOR programming Timeout
1113 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
1114 * or HAL_NOR_STATUS_TIMEOUT
1115 */
HAL_NOR_GetStatus(NOR_HandleTypeDef * hnor,uint32_t Address,uint32_t Timeout)1116 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
1117 {
1118 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
1119 uint16_t tmpSR1 = 0, tmpSR2 = 0;
1120 uint32_t tickstart = 0U;
1121
1122 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
1123 HAL_NOR_MspWait(hnor, Timeout);
1124
1125 /* Get the NOR memory operation status -------------------------------------*/
1126
1127 /* Get tick */
1128 tickstart = HAL_GetTick();
1129 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
1130 {
1131 /* Check for the Timeout */
1132 if(Timeout != HAL_MAX_DELAY)
1133 {
1134 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1135 {
1136 status = HAL_NOR_STATUS_TIMEOUT;
1137 }
1138 }
1139
1140 /* Read NOR status register (DQ6 and DQ5) */
1141 tmpSR1 = *(__IO uint16_t *)Address;
1142 tmpSR2 = *(__IO uint16_t *)Address;
1143
1144 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1145 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1146 {
1147 return HAL_NOR_STATUS_SUCCESS ;
1148 }
1149
1150 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1151 {
1152 status = HAL_NOR_STATUS_ONGOING;
1153 }
1154
1155 tmpSR1 = *(__IO uint16_t *)Address;
1156 tmpSR2 = *(__IO uint16_t *)Address;
1157
1158 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
1159 if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
1160 {
1161 return HAL_NOR_STATUS_SUCCESS;
1162 }
1163 if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
1164 {
1165 return HAL_NOR_STATUS_ERROR;
1166 }
1167 }
1168
1169 /* Return the operation status */
1170 return status;
1171 }
1172
1173 /**
1174 * @}
1175 */
1176
1177 /**
1178 * @}
1179 */
1180 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
1181 STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
1182 STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\
1183 STM32F423xx */
1184 #endif /* HAL_NOR_MODULE_ENABLED */
1185 /**
1186 * @}
1187 */
1188
1189 /**
1190 * @}
1191 */
1192
1193 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1194