1 /** 2 ****************************************************************************** 3 * @file stm32f4x7_eth.h 4 * @author MCD Application Team 5 * @version V1.1.0 6 * @date 31-July-2013 7 * @brief This file contains all the functions prototypes for the Ethernet 8 * firmware driver. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F4x7_ETH_H 31 #define __STM32F4x7_ETH_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f4x7_eth_conf.h" 39 40 /** @addtogroup STM32F4x7_ETH_Driver 41 * @{ 42 */ 43 44 /** @defgroup ETH_Exported_Types 45 * @{ 46 */ 47 48 /** 49 * @brief ETH MAC Init structure definition 50 * @note The user should not configure all the ETH_InitTypeDef structure's fields. 51 * By calling the ETH_StructInit function the structure抯 fields are set to their default values. 52 * Only the parameters that will be set to a non-default value should be configured. 53 */ 54 typedef struct { 55 /** 56 * @brief / * MAC 57 */ 58 uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 59 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 60 and the mode (half/full-duplex). 61 This parameter can be a value of @ref ETH_AutoNegotiation */ 62 63 uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer 64 When enabled, the MAC allows no more then 2048 bytes to be received. 65 When disabled, the MAC can receive up to 16384 bytes. 66 This parameter can be a value of @ref ETH_watchdog */ 67 68 uint32_t ETH_Jabber; /*!< Selects or not Jabber timer 69 When enabled, the MAC allows no more then 2048 bytes to be sent. 70 When disabled, the MAC can send up to 16384 bytes. 71 This parameter can be a value of @ref ETH_Jabber */ 72 73 uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission 74 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 75 76 uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense 77 This parameter can be a value of @ref ETH_Carrier_Sense */ 78 79 uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps 80 This parameter can be a value of @ref ETH_Speed */ 81 82 uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn 83 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 84 in Half-Duplex mode 85 This parameter can be a value of @ref ETH_Receive_Own */ 86 87 uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode 88 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 89 90 uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 91 This parameter can be a value of @ref ETH_Duplex_Mode */ 92 93 uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 94 This parameter can be a value of @ref ETH_Checksum_Offload */ 95 96 uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 97 when a collision occurs (Half-Duplex mode) 98 This parameter can be a value of @ref ETH_Retry_Transmission */ 99 100 uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping 101 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 102 103 uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value 104 This parameter can be a value of @ref ETH_Back_Off_Limit */ 105 106 uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) 107 This parameter can be a value of @ref ETH_Deferral_Check */ 108 109 uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering) 110 This parameter can be a value of @ref ETH_Receive_All */ 111 112 uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode 113 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 114 115 uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 116 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 117 118 uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames 119 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 120 121 uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames 122 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 123 124 uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode 125 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 126 127 uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter 128 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 129 130 uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter 131 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 132 133 uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ 134 135 uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ 136 137 uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the 138 transmit control frame */ 139 140 uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames 141 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 142 143 uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 144 automatic retransmission of PAUSE Frame 145 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 146 147 uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 148 unicast address and unique multicast address) 149 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 150 151 uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 152 disable its transmitter for a specified time (Pause Time) 153 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 154 155 uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 156 or the MAC back-pressure operation (Half-Duplex mode) 157 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 158 159 uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 160 comparison and filtering 161 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 162 163 uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 164 165 /** 166 * @brief / * DMA 167 */ 168 169 uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames 170 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 171 172 uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode 173 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 174 175 uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames 176 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 177 178 uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode 179 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 180 181 uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control 182 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 183 184 uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames 185 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 186 187 uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 188 and length less than 64 bytes) including pad-bytes and CRC) 189 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 190 191 uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO 192 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 193 194 uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 195 frame of Transmit data even before obtaining the status for the first frame. 196 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 197 198 uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats 199 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 200 201 uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers 202 This parameter can be a value of @ref ETH_Fixed_Burst */ 203 204 uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction 205 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 206 207 uint32_t ETH_TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction 208 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 209 210 uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ 211 212 uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration 213 This parameter can be a value of @ref ETH_DMA_Arbitration */ 214 }ETH_InitTypeDef; 215 216 /**--------------------------------------------------------------------------**/ 217 /** 218 * @brief DMA descriptors types 219 */ 220 /**--------------------------------------------------------------------------**/ 221 222 /** 223 * @brief ETH DMA Descriptors data structure definition 224 */ 225 typedef struct { 226 __IO uint32_t Status; /*!< Status */ 227 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 228 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 229 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 230 /* Enhanced ETHERNET DMA PTP Descriptors */ 231 #ifdef USE_ENHANCED_DMA_DESCRIPTORS 232 uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */ 233 uint32_t Reserved1; /* Reserved */ 234 uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */ 235 uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */ 236 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ 237 } ETH_DMADESCTypeDef; 238 239 240 typedef struct{ 241 u32 length; 242 u32 buffer; 243 __IO ETH_DMADESCTypeDef *descriptor; 244 }FrameTypeDef; 245 246 247 typedef struct { 248 __IO ETH_DMADESCTypeDef *FS_Rx_Desc; /*!< First Segment Rx Desc */ 249 __IO ETH_DMADESCTypeDef *LS_Rx_Desc; /*!< Last Segment Rx Desc */ 250 __IO uint32_t Seg_Count; /*!< Segment count */ 251 } ETH_DMA_Rx_Frame_infos; 252 253 254 /** 255 * @} 256 */ 257 258 /** @defgroup ETH_Exported_Constants 259 * @{ 260 */ 261 262 /**--------------------------------------------------------------------------**/ 263 /** 264 * @brief ETH Frames defines 265 */ 266 /**--------------------------------------------------------------------------**/ 267 268 /** @defgroup ENET_Buffers_setting 269 * @{ 270 */ 271 #define ETH_MAX_PACKET_SIZE 1524 /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 272 #define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 273 #define ETH_CRC 4 /*!< Ethernet CRC */ 274 #define ETH_EXTRA 2 /*!< Extra bytes in some cases */ 275 #define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ 276 #define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ 277 #define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ 278 #define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ 279 280 /* Ethernet driver receive buffers are organized in a chained linked-list, when 281 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 282 to the driver receive buffers memory. 283 284 Depending on the size of the received ethernet packet and the size of 285 each ethernet driver receive buffer, the received packet can take one or more 286 ethernet driver receive buffer. 287 288 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 289 and the total count of the driver receive buffers ETH_RXBUFNB. 290 291 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 292 example, they can be reconfigured in the application layer to fit the application 293 needs */ 294 295 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 296 packet */ 297 #ifndef ETH_RX_BUF_SIZE 298 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 299 #endif 300 301 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 302 #ifndef ETH_RXBUFNB 303 #define ETH_RXBUFNB 5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 304 #endif 305 306 307 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 308 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 309 driver transmit buffers memory to the TxFIFO. 310 311 Depending on the size of the Ethernet packet to be transmitted and the size of 312 each ethernet driver transmit buffer, the packet to be transmitted can take 313 one or more ethernet driver transmit buffer. 314 315 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 316 and the total count of the driver transmit buffers ETH_TXBUFNB. 317 318 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 319 example, they can be reconfigured in the application layer to fit the application 320 needs */ 321 322 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 323 packet */ 324 #ifndef ETH_TX_BUF_SIZE 325 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 326 #endif 327 328 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 329 #ifndef ETH_TXBUFNB 330 #define ETH_TXBUFNB 5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 331 #endif 332 333 #define ETH_DMARxDesc_FrameLengthShift 16 334 335 /**--------------------------------------------------------------------------**/ 336 /** 337 * @brief Ethernet DMA descriptors registers bits definition 338 */ 339 /**--------------------------------------------------------------------------**/ 340 341 /** 342 @code 343 DMA Tx Desciptor 344 ----------------------------------------------------------------------------------------------- 345 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 346 ----------------------------------------------------------------------------------------------- 347 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 348 ----------------------------------------------------------------------------------------------- 349 TDES2 | Buffer1 Address [31:0] | 350 ----------------------------------------------------------------------------------------------- 351 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 352 ----------------------------------------------------------------------------------------------- 353 @endcode 354 */ 355 356 /** 357 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 358 */ 359 #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ 360 #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ 361 #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ 362 #define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ 363 #define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ 364 #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ 365 #define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ 366 #define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ 367 #define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ 368 #define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ 369 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 370 #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 371 #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ 372 #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ 373 #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ 374 #define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ 375 #define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 376 #define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ 377 #define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 378 #define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ 379 #define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ 380 #define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ 381 #define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ 382 #define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ 383 #define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ 384 #define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ 385 #define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ 386 #define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ 387 #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ 388 389 /** 390 * @brief Bit definition of TDES1 register 391 */ 392 #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ 393 #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ 394 395 /** 396 * @brief Bit definition of TDES2 register 397 */ 398 #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ 399 400 /** 401 * @brief Bit definition of TDES3 register 402 */ 403 #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ 404 405 /*--------------------------------------------------------------------------------------------- 406 TDES6 | Transmit Time Stamp Low [31:0] | 407 ----------------------------------------------------------------------------------------------- 408 TDES7 | Transmit Time Stamp High [31:0] | 409 ----------------------------------------------------------------------------------------------*/ 410 411 /* Bit definition of TDES6 register */ 412 #define ETH_DMAPTPTxDesc_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */ 413 414 /* Bit definition of TDES7 register */ 415 #define ETH_DMAPTPTxDesc_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */ 416 417 /** 418 * @} 419 */ 420 421 422 /** @defgroup DMA_Rx_descriptor 423 * @{ 424 */ 425 426 /** 427 @code 428 DMA Rx Descriptor 429 -------------------------------------------------------------------------------------------------------------------- 430 RDES0 | OWN(31) | Status [30:0] | 431 --------------------------------------------------------------------------------------------------------------------- 432 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 433 --------------------------------------------------------------------------------------------------------------------- 434 RDES2 | Buffer1 Address [31:0] | 435 --------------------------------------------------------------------------------------------------------------------- 436 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 437 --------------------------------------------------------------------------------------------------------------------- 438 @endcode 439 */ 440 441 /** 442 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 443 */ 444 #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ 445 #define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ 446 #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ 447 #define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 448 #define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ 449 #define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ 450 #define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ 451 #define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ 452 #define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ 453 #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ 454 #define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ 455 #define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 456 #define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ 457 #define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ 458 #define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 459 #define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ 460 #define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 461 #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ 462 #define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 463 464 /** 465 * @brief Bit definition of RDES1 register 466 */ 467 #define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ 468 #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ 469 #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ 470 #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ 471 #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ 472 473 /** 474 * @brief Bit definition of RDES2 register 475 */ 476 #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ 477 478 /** 479 * @brief Bit definition of RDES3 register 480 */ 481 #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ 482 483 /*--------------------------------------------------------------------------------------------------------------------- 484 RDES4 | Reserved[31:15] | Extended Status [14:0] | 485 --------------------------------------------------------------------------------------------------------------------- 486 RDES5 | Reserved[31:0] | 487 --------------------------------------------------------------------------------------------------------------------- 488 RDES6 | Receive Time Stamp Low [31:0] | 489 --------------------------------------------------------------------------------------------------------------------- 490 RDES7 | Receive Time Stamp High [31:0] | 491 --------------------------------------------------------------------------------------------------------------------*/ 492 493 /* Bit definition of RDES4 register */ 494 #define ETH_DMAPTPRxDesc_PTPV ((uint32_t)0x00002000) /* PTP Version */ 495 #define ETH_DMAPTPRxDesc_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ 496 #define ETH_DMAPTPRxDesc_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ 497 #define ETH_DMAPTPRxDesc_PTPMT_Sync ((uint32_t)0x00000100) /* SYNC message (all clock types) */ 498 #define ETH_DMAPTPRxDesc_PTPMT_FollowUp ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ 499 #define ETH_DMAPTPRxDesc_PTPMT_DelayReq ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ 500 #define ETH_DMAPTPRxDesc_PTPMT_DelayResp ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ 501 #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 502 #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 503 #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 504 #define ETH_DMAPTPRxDesc_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ 505 #define ETH_DMAPTPRxDesc_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ 506 #define ETH_DMAPTPRxDesc_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ 507 #define ETH_DMAPTPRxDesc_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ 508 #define ETH_DMAPTPRxDesc_IPHE ((uint32_t)0x00000008) /* IP Header Error */ 509 #define ETH_DMAPTPRxDesc_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ 510 #define ETH_DMAPTPRxDesc_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ 511 #define ETH_DMAPTPRxDesc_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ 512 #define ETH_DMAPTPRxDesc_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ 513 514 /* Bit definition of RDES6 register */ 515 #define ETH_DMAPTPRxDesc_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */ 516 517 /* Bit definition of RDES7 register */ 518 #define ETH_DMAPTPRxDesc_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */ 519 520 521 /**--------------------------------------------------------------------------**/ 522 /** 523 * @brief Description of common PHY registers 524 */ 525 /**--------------------------------------------------------------------------**/ 526 527 /** 528 * @} 529 */ 530 531 /** @defgroup PHY_Read_write_Timeouts 532 * @{ 533 */ 534 #define PHY_READ_TO ((uint32_t)0x0004FFFF) 535 #define PHY_WRITE_TO ((uint32_t)0x0004FFFF) 536 537 /** 538 * @} 539 */ 540 541 /** @defgroup PHY_Register_address 542 * @{ 543 */ 544 #define PHY_BCR 0 /*!< Transceiver Basic Control Register */ 545 #define PHY_BSR 1 /*!< Transceiver Basic Status Register */ 546 547 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) 548 #define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ 549 ((REG) == PHY_BSR) || \ 550 ((REG) == PHY_SR)) 551 /** 552 * @} 553 */ 554 555 /** @defgroup PHY_basic_Control_register 556 * @{ 557 */ 558 #define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */ 559 #define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */ 560 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ 561 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ 562 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ 563 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ 564 #define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ 565 #define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ 566 #define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */ 567 #define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */ 568 569 /** 570 * @} 571 */ 572 573 /** @defgroup PHY_basic_status_register 574 * @{ 575 */ 576 #define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ 577 #define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */ 578 #define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */ 579 580 /** 581 * @} 582 */ 583 584 /**--------------------------------------------------------------------------**/ 585 /** 586 * @brief MAC defines 587 */ 588 /**--------------------------------------------------------------------------**/ 589 590 /** @defgroup ETH_AutoNegotiation 591 * @{ 592 */ 593 #define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) 594 #define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) 595 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ 596 ((CMD) == ETH_AutoNegotiation_Disable)) 597 598 /** 599 * @} 600 */ 601 602 /** @defgroup ETH_watchdog 603 * @{ 604 */ 605 #define ETH_Watchdog_Enable ((uint32_t)0x00000000) 606 #define ETH_Watchdog_Disable ((uint32_t)0x00800000) 607 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ 608 ((CMD) == ETH_Watchdog_Disable)) 609 610 /** 611 * @} 612 */ 613 614 /** @defgroup ETH_Jabber 615 * @{ 616 */ 617 #define ETH_Jabber_Enable ((uint32_t)0x00000000) 618 #define ETH_Jabber_Disable ((uint32_t)0x00400000) 619 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ 620 ((CMD) == ETH_Jabber_Disable)) 621 622 /** 623 * @} 624 */ 625 626 /** @defgroup ETH_Inter_Frame_Gap 627 * @{ 628 */ 629 #define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ 630 #define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ 631 #define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ 632 #define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ 633 #define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ 634 #define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ 635 #define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ 636 #define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ 637 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ 638 ((GAP) == ETH_InterFrameGap_88Bit) || \ 639 ((GAP) == ETH_InterFrameGap_80Bit) || \ 640 ((GAP) == ETH_InterFrameGap_72Bit) || \ 641 ((GAP) == ETH_InterFrameGap_64Bit) || \ 642 ((GAP) == ETH_InterFrameGap_56Bit) || \ 643 ((GAP) == ETH_InterFrameGap_48Bit) || \ 644 ((GAP) == ETH_InterFrameGap_40Bit)) 645 646 /** 647 * @} 648 */ 649 650 /** @defgroup ETH_Carrier_Sense 651 * @{ 652 */ 653 #define ETH_CarrierSense_Enable ((uint32_t)0x00000000) 654 #define ETH_CarrierSense_Disable ((uint32_t)0x00010000) 655 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ 656 ((CMD) == ETH_CarrierSense_Disable)) 657 658 /** 659 * @} 660 */ 661 662 /** @defgroup ETH_Speed 663 * @{ 664 */ 665 #define ETH_Speed_10M ((uint32_t)0x00000000) 666 #define ETH_Speed_100M ((uint32_t)0x00004000) 667 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ 668 ((SPEED) == ETH_Speed_100M)) 669 670 /** 671 * @} 672 */ 673 674 /** @defgroup ETH_Receive_Own 675 * @{ 676 */ 677 #define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) 678 #define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) 679 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ 680 ((CMD) == ETH_ReceiveOwn_Disable)) 681 682 /** 683 * @} 684 */ 685 686 /** @defgroup ETH_Loop_Back_Mode 687 * @{ 688 */ 689 #define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) 690 #define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) 691 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ 692 ((CMD) == ETH_LoopbackMode_Disable)) 693 694 /** 695 * @} 696 */ 697 698 /** @defgroup ETH_Duplex_Mode 699 * @{ 700 */ 701 #define ETH_Mode_FullDuplex ((uint32_t)0x00000800) 702 #define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) 703 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ 704 ((MODE) == ETH_Mode_HalfDuplex)) 705 706 /** 707 * @} 708 */ 709 710 /** @defgroup ETH_Checksum_Offload 711 * @{ 712 */ 713 #define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) 714 #define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) 715 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ 716 ((CMD) == ETH_ChecksumOffload_Disable)) 717 718 /** 719 * @} 720 */ 721 722 /** @defgroup ETH_Retry_Transmission 723 * @{ 724 */ 725 #define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) 726 #define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) 727 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ 728 ((CMD) == ETH_RetryTransmission_Disable)) 729 730 /** 731 * @} 732 */ 733 734 /** @defgroup ETH_Automatic_Pad_CRC_Strip 735 * @{ 736 */ 737 #define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) 738 #define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) 739 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ 740 ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) 741 742 /** 743 * @} 744 */ 745 746 /** @defgroup ETH_Back_Off_Limit 747 * @{ 748 */ 749 #define ETH_BackOffLimit_10 ((uint32_t)0x00000000) 750 #define ETH_BackOffLimit_8 ((uint32_t)0x00000020) 751 #define ETH_BackOffLimit_4 ((uint32_t)0x00000040) 752 #define ETH_BackOffLimit_1 ((uint32_t)0x00000060) 753 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ 754 ((LIMIT) == ETH_BackOffLimit_8) || \ 755 ((LIMIT) == ETH_BackOffLimit_4) || \ 756 ((LIMIT) == ETH_BackOffLimit_1)) 757 758 /** 759 * @} 760 */ 761 762 /** @defgroup ETH_Deferral_Check 763 * @{ 764 */ 765 #define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) 766 #define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) 767 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ 768 ((CMD) == ETH_DeferralCheck_Disable)) 769 770 /** 771 * @} 772 */ 773 774 /** @defgroup ETH_Receive_All 775 * @{ 776 */ 777 #define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) 778 #define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) 779 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ 780 ((CMD) == ETH_ReceiveAll_Disable)) 781 782 /** 783 * @} 784 */ 785 786 /** @defgroup ETH_Source_Addr_Filter 787 * @{ 788 */ 789 #define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) 790 #define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) 791 #define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) 792 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ 793 ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ 794 ((CMD) == ETH_SourceAddrFilter_Disable)) 795 796 /** 797 * @} 798 */ 799 800 /** @defgroup ETH_Pass_Control_Frames 801 * @{ 802 */ 803 #define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ 804 #define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 805 #define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ 806 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ 807 ((PASS) == ETH_PassControlFrames_ForwardAll) || \ 808 ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) 809 810 /** 811 * @} 812 */ 813 814 /** @defgroup ETH_Broadcast_Frames_Reception 815 * @{ 816 */ 817 #define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) 818 #define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) 819 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ 820 ((CMD) == ETH_BroadcastFramesReception_Disable)) 821 822 /** 823 * @} 824 */ 825 826 /** @defgroup ETH_Destination_Addr_Filter 827 * @{ 828 */ 829 #define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) 830 #define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) 831 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ 832 ((FILTER) == ETH_DestinationAddrFilter_Inverse)) 833 834 /** 835 * @} 836 */ 837 838 /** @defgroup ETH_Promiscuous_Mode 839 * @{ 840 */ 841 #define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) 842 #define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) 843 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ 844 ((CMD) == ETH_PromiscuousMode_Disable)) 845 846 /** 847 * @} 848 */ 849 850 /** @defgroup ETH_Multicast_Frames_Filter 851 * @{ 852 */ 853 #define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) 854 #define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) 855 #define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) 856 #define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) 857 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ 858 ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ 859 ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ 860 ((FILTER) == ETH_MulticastFramesFilter_None)) 861 862 863 /** 864 * @} 865 */ 866 867 /** @defgroup ETH_Unicast_Frames_Filter 868 * @{ 869 */ 870 #define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) 871 #define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) 872 #define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) 873 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ 874 ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ 875 ((FILTER) == ETH_UnicastFramesFilter_Perfect)) 876 877 /** 878 * @} 879 */ 880 881 /** @defgroup ETH_Pause_Time 882 * @{ 883 */ 884 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) 885 886 /** 887 * @} 888 */ 889 890 /** @defgroup ETH_Zero_Quanta_Pause 891 * @{ 892 */ 893 #define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) 894 #define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) 895 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ 896 ((CMD) == ETH_ZeroQuantaPause_Disable)) 897 /** 898 * @} 899 */ 900 901 /** @defgroup ETH_Pause_Low_Threshold 902 * @{ 903 */ 904 #define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ 905 #define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ 906 #define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ 907 #define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ 908 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ 909 ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ 910 ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ 911 ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) 912 913 /** 914 * @} 915 */ 916 917 /** @defgroup ETH_Unicast_Pause_Frame_Detect 918 * @{ 919 */ 920 #define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) 921 #define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) 922 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ 923 ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) 924 925 /** 926 * @} 927 */ 928 929 /** @defgroup ETH_Receive_Flow_Control 930 * @{ 931 */ 932 #define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) 933 #define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) 934 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ 935 ((CMD) == ETH_ReceiveFlowControl_Disable)) 936 937 /** 938 * @} 939 */ 940 941 /** @defgroup ETH_Transmit_Flow_Control 942 * @{ 943 */ 944 #define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) 945 #define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) 946 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ 947 ((CMD) == ETH_TransmitFlowControl_Disable)) 948 949 /** 950 * @} 951 */ 952 953 /** @defgroup ETH_VLAN_Tag_Comparison 954 * @{ 955 */ 956 #define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) 957 #define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) 958 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ 959 ((COMPARISON) == ETH_VLANTagComparison_16Bit)) 960 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) 961 962 /** 963 * @} 964 */ 965 966 /** @defgroup ETH_MAC_Flags 967 * @{ 968 */ 969 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ 970 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ 971 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ 972 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ 973 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ 974 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 975 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 976 ((FLAG) == ETH_MAC_FLAG_PMT)) 977 /** 978 * @} 979 */ 980 981 /** @defgroup ETH_MAC_Interrupts 982 * @{ 983 */ 984 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ 985 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ 986 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ 987 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ 988 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ 989 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) 990 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 991 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 992 ((IT) == ETH_MAC_IT_PMT)) 993 /** 994 * @} 995 */ 996 997 /** @defgroup ETH_MAC_addresses 998 * @{ 999 */ 1000 #define ETH_MAC_Address0 ((uint32_t)0x00000000) 1001 #define ETH_MAC_Address1 ((uint32_t)0x00000008) 1002 #define ETH_MAC_Address2 ((uint32_t)0x00000010) 1003 #define ETH_MAC_Address3 ((uint32_t)0x00000018) 1004 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ 1005 ((ADDRESS) == ETH_MAC_Address1) || \ 1006 ((ADDRESS) == ETH_MAC_Address2) || \ 1007 ((ADDRESS) == ETH_MAC_Address3)) 1008 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ 1009 ((ADDRESS) == ETH_MAC_Address2) || \ 1010 ((ADDRESS) == ETH_MAC_Address3)) 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames 1016 * @{ 1017 */ 1018 #define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) 1019 #define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) 1020 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ 1021 ((FILTER) == ETH_MAC_AddressFilter_DA)) 1022 /** 1023 * @} 1024 */ 1025 1026 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes 1027 * @{ 1028 */ 1029 #define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ 1030 #define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ 1031 #define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ 1032 #define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ 1033 #define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ 1034 #define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ 1035 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ 1036 ((MASK) == ETH_MAC_AddressMask_Byte5) || \ 1037 ((MASK) == ETH_MAC_AddressMask_Byte4) || \ 1038 ((MASK) == ETH_MAC_AddressMask_Byte3) || \ 1039 ((MASK) == ETH_MAC_AddressMask_Byte2) || \ 1040 ((MASK) == ETH_MAC_AddressMask_Byte1)) 1041 1042 /**--------------------------------------------------------------------------**/ 1043 /** 1044 * @brief Ethernet DMA Descriptors defines 1045 */ 1046 /**--------------------------------------------------------------------------**/ 1047 /** 1048 * @} 1049 */ 1050 1051 /** @defgroup ETH_DMA_Tx_descriptor_flags 1052 * @{ 1053 */ 1054 #define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ 1055 ((FLAG) == ETH_DMATxDesc_IC) || \ 1056 ((FLAG) == ETH_DMATxDesc_LS) || \ 1057 ((FLAG) == ETH_DMATxDesc_FS) || \ 1058 ((FLAG) == ETH_DMATxDesc_DC) || \ 1059 ((FLAG) == ETH_DMATxDesc_DP) || \ 1060 ((FLAG) == ETH_DMATxDesc_TTSE) || \ 1061 ((FLAG) == ETH_DMATxDesc_TER) || \ 1062 ((FLAG) == ETH_DMATxDesc_TCH) || \ 1063 ((FLAG) == ETH_DMATxDesc_TTSS) || \ 1064 ((FLAG) == ETH_DMATxDesc_IHE) || \ 1065 ((FLAG) == ETH_DMATxDesc_ES) || \ 1066 ((FLAG) == ETH_DMATxDesc_JT) || \ 1067 ((FLAG) == ETH_DMATxDesc_FF) || \ 1068 ((FLAG) == ETH_DMATxDesc_PCE) || \ 1069 ((FLAG) == ETH_DMATxDesc_LCA) || \ 1070 ((FLAG) == ETH_DMATxDesc_NC) || \ 1071 ((FLAG) == ETH_DMATxDesc_LCO) || \ 1072 ((FLAG) == ETH_DMATxDesc_EC) || \ 1073 ((FLAG) == ETH_DMATxDesc_VF) || \ 1074 ((FLAG) == ETH_DMATxDesc_CC) || \ 1075 ((FLAG) == ETH_DMATxDesc_ED) || \ 1076 ((FLAG) == ETH_DMATxDesc_UF) || \ 1077 ((FLAG) == ETH_DMATxDesc_DB)) 1078 1079 /** 1080 * @} 1081 */ 1082 1083 /** @defgroup ETH_DMA_Tx_descriptor_segment 1084 * @{ 1085 */ 1086 #define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ 1087 #define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ 1088 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ 1089 ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) 1090 1091 /** 1092 * @} 1093 */ 1094 1095 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control 1096 * @{ 1097 */ 1098 #define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ 1099 #define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ 1100 #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 1101 #define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 1102 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ 1103 ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ 1104 ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ 1105 ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) 1106 /** 1107 * @brief ETH DMA Tx Desciptor buffer size 1108 */ 1109 #define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) 1110 1111 /** 1112 * @} 1113 */ 1114 1115 /** @defgroup ETH_DMA_Rx_descriptor_flags 1116 * @{ 1117 */ 1118 #define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ 1119 ((FLAG) == ETH_DMARxDesc_AFM) || \ 1120 ((FLAG) == ETH_DMARxDesc_ES) || \ 1121 ((FLAG) == ETH_DMARxDesc_DE) || \ 1122 ((FLAG) == ETH_DMARxDesc_SAF) || \ 1123 ((FLAG) == ETH_DMARxDesc_LE) || \ 1124 ((FLAG) == ETH_DMARxDesc_OE) || \ 1125 ((FLAG) == ETH_DMARxDesc_VLAN) || \ 1126 ((FLAG) == ETH_DMARxDesc_FS) || \ 1127 ((FLAG) == ETH_DMARxDesc_LS) || \ 1128 ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ 1129 ((FLAG) == ETH_DMARxDesc_LC) || \ 1130 ((FLAG) == ETH_DMARxDesc_FT) || \ 1131 ((FLAG) == ETH_DMARxDesc_RWT) || \ 1132 ((FLAG) == ETH_DMARxDesc_RE) || \ 1133 ((FLAG) == ETH_DMARxDesc_DBE) || \ 1134 ((FLAG) == ETH_DMARxDesc_CE) || \ 1135 ((FLAG) == ETH_DMARxDesc_MAMPCE)) 1136 1137 /* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/ 1138 #define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \ 1139 ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \ 1140 ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \ 1141 ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \ 1142 ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \ 1143 ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \ 1144 ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \ 1145 ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \ 1146 ((FLAG) == ETH_DMAPTPRxDesc_IPPT)) 1147 1148 /** 1149 * @} 1150 */ 1151 1152 /** @defgroup ETH_DMA_Rx_descriptor_buffers_ 1153 * @{ 1154 */ 1155 #define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ 1156 #define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ 1157 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ 1158 ((BUFFER) == ETH_DMARxDesc_Buffer2)) 1159 1160 /**--------------------------------------------------------------------------**/ 1161 /** 1162 * @brief Ethernet DMA defines 1163 */ 1164 /**--------------------------------------------------------------------------**/ 1165 /** 1166 * @} 1167 */ 1168 1169 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 1170 * @{ 1171 */ 1172 #define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) 1173 #define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) 1174 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ 1175 ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) 1176 /** 1177 * @} 1178 */ 1179 1180 /** @defgroup ETH_Receive_Store_Forward 1181 * @{ 1182 */ 1183 #define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) 1184 #define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) 1185 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ 1186 ((CMD) == ETH_ReceiveStoreForward_Disable)) 1187 /** 1188 * @} 1189 */ 1190 1191 /** @defgroup ETH_Flush_Received_Frame 1192 * @{ 1193 */ 1194 #define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) 1195 #define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) 1196 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ 1197 ((CMD) == ETH_FlushReceivedFrame_Disable)) 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup ETH_Transmit_Store_Forward 1203 * @{ 1204 */ 1205 #define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) 1206 #define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) 1207 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ 1208 ((CMD) == ETH_TransmitStoreForward_Disable)) 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup ETH_Transmit_Threshold_Control 1214 * @{ 1215 */ 1216 #define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 1217 #define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 1218 #define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 1219 #define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 1220 #define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 1221 #define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 1222 #define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 1223 #define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 1224 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ 1225 ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ 1226 ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ 1227 ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ 1228 ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ 1229 ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ 1230 ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ 1231 ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) 1232 /** 1233 * @} 1234 */ 1235 1236 /** @defgroup ETH_Forward_Error_Frames 1237 * @{ 1238 */ 1239 #define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) 1240 #define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) 1241 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ 1242 ((CMD) == ETH_ForwardErrorFrames_Disable)) 1243 /** 1244 * @} 1245 */ 1246 1247 /** @defgroup ETH_Forward_Undersized_Good_Frames 1248 * @{ 1249 */ 1250 #define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) 1251 #define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) 1252 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ 1253 ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) 1254 1255 /** 1256 * @} 1257 */ 1258 1259 /** @defgroup ETH_Receive_Threshold_Control 1260 * @{ 1261 */ 1262 #define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 1263 #define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 1264 #define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 1265 #define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 1266 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ 1267 ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ 1268 ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ 1269 ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup ETH_Second_Frame_Operate 1275 * @{ 1276 */ 1277 #define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) 1278 #define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) 1279 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ 1280 ((CMD) == ETH_SecondFrameOperate_Disable)) 1281 1282 /** 1283 * @} 1284 */ 1285 1286 /** @defgroup ETH_Address_Aligned_Beats 1287 * @{ 1288 */ 1289 #define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) 1290 #define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) 1291 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ 1292 ((CMD) == ETH_AddressAlignedBeats_Disable)) 1293 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup ETH_Fixed_Burst 1299 * @{ 1300 */ 1301 #define ETH_FixedBurst_Enable ((uint32_t)0x00010000) 1302 #define ETH_FixedBurst_Disable ((uint32_t)0x00000000) 1303 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ 1304 ((CMD) == ETH_FixedBurst_Disable)) 1305 1306 /** 1307 * @} 1308 */ 1309 1310 /** @defgroup ETH_Rx_DMA_Burst_Length 1311 * @{ 1312 */ 1313 #define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 1314 #define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 1315 #define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1316 #define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1317 #define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1318 #define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1319 #define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 1320 #define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 1321 #define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 1322 #define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 1323 #define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 1324 #define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 1325 1326 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ 1327 ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ 1328 ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ 1329 ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ 1330 ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ 1331 ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ 1332 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ 1333 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ 1334 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ 1335 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ 1336 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ 1337 ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) 1338 1339 /** 1340 * @} 1341 */ 1342 1343 /** @defgroup ETH_Tx_DMA_Burst_Length 1344 * @{ 1345 */ 1346 #define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 1347 #define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 1348 #define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1349 #define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1350 #define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1351 #define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1352 #define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 1353 #define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 1354 #define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 1355 #define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 1356 #define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 1357 #define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 1358 1359 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ 1360 ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ 1361 ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ 1362 ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ 1363 ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ 1364 ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ 1365 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ 1366 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ 1367 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ 1368 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ 1369 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ 1370 ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) 1371 /** 1372 * @brief ETH DMA Descriptor SkipLength 1373 */ 1374 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) 1375 1376 /** 1377 * @} 1378 */ 1379 1380 /** @defgroup ETH_DMA_Arbitration 1381 * @{ 1382 */ 1383 #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) 1384 #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) 1385 #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) 1386 #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) 1387 #define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) 1388 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ 1389 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ 1390 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ 1391 ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ 1392 ((RATIO) == ETH_DMAArbitration_RxPriorTx)) 1393 /** 1394 * @} 1395 */ 1396 1397 /** @defgroup ETH_DMA_Flags 1398 * @{ 1399 */ 1400 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ 1401 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ 1402 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ 1403 #define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 1404 #define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ 1405 #define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ 1406 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ 1407 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ 1408 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ 1409 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ 1410 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ 1411 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ 1412 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ 1413 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ 1414 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ 1415 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ 1416 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ 1417 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ 1418 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ 1419 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ 1420 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ 1421 1422 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) 1423 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 1424 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ 1425 ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ 1426 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 1427 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 1428 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 1429 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 1430 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 1431 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 1432 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 1433 ((FLAG) == ETH_DMA_FLAG_T)) 1434 /** 1435 * @} 1436 */ 1437 1438 /** @defgroup ETH_DMA_Interrupts 1439 * @{ 1440 */ 1441 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ 1442 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ 1443 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ 1444 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ 1445 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ 1446 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ 1447 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ 1448 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ 1449 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ 1450 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ 1451 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ 1452 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ 1453 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ 1454 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ 1455 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ 1456 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ 1457 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ 1458 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ 1459 1460 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) 1461 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 1462 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 1463 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 1464 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 1465 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 1466 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 1467 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 1468 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 1469 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 1470 1471 /** 1472 * @} 1473 */ 1474 1475 /** @defgroup ETH_DMA_transmit_process_state_ 1476 * @{ 1477 */ 1478 #define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ 1479 #define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ 1480 #define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ 1481 #define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ 1482 #define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ 1483 #define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ 1484 1485 /** 1486 * @} 1487 */ 1488 1489 1490 /** @defgroup ETH_DMA_receive_process_state_ 1491 * @{ 1492 */ 1493 #define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ 1494 #define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ 1495 #define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ 1496 #define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ 1497 #define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ 1498 #define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ 1499 1500 /** 1501 * @} 1502 */ 1503 1504 /** @defgroup ETH_DMA_overflow_ 1505 * @{ 1506 */ 1507 #define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ 1508 #define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ 1509 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ 1510 ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) 1511 1512 /**--------------------------------------------------------------------------**/ 1513 /** 1514 * @brief Ethernet PMT defines 1515 */ 1516 /**--------------------------------------------------------------------------**/ 1517 /** 1518 * @} 1519 */ 1520 1521 /** @defgroup ETH_PMT_Flags 1522 * @{ 1523 */ 1524 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ 1525 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ 1526 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ 1527 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 1528 ((FLAG) == ETH_PMT_FLAG_MPR)) 1529 1530 /**--------------------------------------------------------------------------**/ 1531 /** 1532 * @brief Ethernet MMC defines 1533 */ 1534 /**--------------------------------------------------------------------------**/ 1535 /** 1536 * @} 1537 */ 1538 1539 /** @defgroup ETH_MMC_Tx_Interrupts 1540 * @{ 1541 */ 1542 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ 1543 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ 1544 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ 1545 1546 /** 1547 * @} 1548 */ 1549 1550 /** @defgroup ETH_MMC_Rx_Interrupts 1551 * @{ 1552 */ 1553 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ 1554 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ 1555 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ 1556 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ 1557 ((IT) != 0x00)) 1558 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 1559 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 1560 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 1561 /** 1562 * @} 1563 */ 1564 1565 /** @defgroup ETH_MMC_Registers 1566 * @{ 1567 */ 1568 #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ 1569 #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ 1570 #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ 1571 #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ 1572 #define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ 1573 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ 1574 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ 1575 #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ 1576 #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ 1577 #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ 1578 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ 1579 1580 /** 1581 * @brief ETH MMC registers 1582 */ 1583 #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ 1584 ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ 1585 ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ 1586 ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ 1587 ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ 1588 ((REG) == ETH_MMCRGUFCR)) 1589 1590 /**--------------------------------------------------------------------------**/ 1591 /** 1592 * @brief Ethernet PTP defines 1593 */ 1594 /**--------------------------------------------------------------------------**/ 1595 /** 1596 * @} 1597 */ 1598 1599 /** @defgroup ETH_PTP_time_update_method 1600 * @{ 1601 */ 1602 #define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ 1603 #define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ 1604 #define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ 1605 ((UPDATE) == ETH_PTP_CoarseUpdate)) 1606 1607 /** 1608 * @} 1609 */ 1610 1611 1612 /** @defgroup ETH_PTP_Flags 1613 * @{ 1614 */ 1615 #define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ 1616 #define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ 1617 #define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ 1618 #define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ 1619 1620 #define ETH_PTP_FLAG_TSTTR ((uint32_t)0x10000002) /* Time stamp target time reached */ 1621 #define ETH_PTP_FLAG_TSSO ((uint32_t)0x10000001) /* Time stamp seconds overflow */ 1622 1623 #define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ 1624 ((FLAG) == ETH_PTP_FLAG_TSITE) || \ 1625 ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ 1626 ((FLAG) == ETH_PTP_FLAG_TSSTI) || \ 1627 ((FLAG) == ETH_PTP_FLAG_TSTTR) || \ 1628 ((FLAG) == ETH_PTP_FLAG_TSSO)) 1629 1630 /** 1631 * @brief ETH PTP subsecond increment 1632 */ 1633 #define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) 1634 1635 /** 1636 * @} 1637 */ 1638 1639 1640 /** @defgroup ETH_PTP_time_sign 1641 * @{ 1642 */ 1643 #define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ 1644 #define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ 1645 #define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ 1646 ((SIGN) == ETH_PTP_NegativeTime)) 1647 1648 /** 1649 * @brief ETH PTP time stamp low update 1650 */ 1651 #define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) 1652 1653 /** 1654 * @brief ETH PTP registers 1655 */ 1656 #define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ 1657 #define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ 1658 #define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ 1659 #define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ 1660 #define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ 1661 #define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ 1662 #define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ 1663 #define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ 1664 #define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ 1665 1666 #define ETH_PTPTSSR ((uint32_t)0x00000728) /* PTP TSSR register */ 1667 1668 #define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ 1669 ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ 1670 ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ 1671 ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ 1672 ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) 1673 1674 /** 1675 * @brief ETHERNET PTP clock 1676 */ 1677 #define ETH_PTP_OrdinaryClock ((uint32_t)0x00000000) /* Ordinary Clock */ 1678 #define ETH_PTP_BoundaryClock ((uint32_t)0x00010000) /* Boundary Clock */ 1679 #define ETH_PTP_EndToEndTransparentClock ((uint32_t)0x00020000) /* End To End Transparent Clock */ 1680 #define ETH_PTP_PeerToPeerTransparentClock ((uint32_t)0x00030000) /* Peer To Peer Transparent Clock */ 1681 1682 #define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \ 1683 ((CLOCK) == ETH_PTP_BoundaryClock) || \ 1684 ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \ 1685 ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock)) 1686 /** 1687 * @brief ETHERNET snapshot 1688 */ 1689 #define ETH_PTP_SnapshotMasterMessage ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ 1690 #define ETH_PTP_SnapshotEventMessage ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ 1691 #define ETH_PTP_SnapshotIPV4Frames ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ 1692 #define ETH_PTP_SnapshotIPV6Frames ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ 1693 #define ETH_PTP_SnapshotPTPOverEthernetFrames ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ 1694 #define ETH_PTP_SnapshotAllReceivedFrames ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ 1695 1696 #define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \ 1697 ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \ 1698 ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \ 1699 ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \ 1700 ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \ 1701 ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames)) 1702 1703 /** 1704 * @} 1705 */ 1706 /* ETHERNET MAC address offsets */ 1707 #define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ 1708 #define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ 1709 1710 /* ETHERNET MACMIIAR register Mask */ 1711 #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) 1712 1713 /* ETHERNET MACCR register Mask */ 1714 #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) 1715 1716 /* ETHERNET MACFCR register Mask */ 1717 #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) 1718 1719 1720 /* ETHERNET DMAOMR register Mask */ 1721 #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) 1722 1723 1724 /* ETHERNET Remote Wake-up frame register length */ 1725 #define ETH_WAKEUP_REGISTER_LENGTH 8 1726 1727 /* ETHERNET Missed frames counter Shift */ 1728 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 1729 1730 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 1731 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 1732 1733 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 1734 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 1735 1736 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 1737 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 1738 1739 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 1740 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 1741 1742 /* ETHERNET errors */ 1743 #define ETH_ERROR ((uint32_t)0) 1744 #define ETH_SUCCESS ((uint32_t)1) 1745 1746 /** 1747 * @} 1748 */ 1749 1750 /** @defgroup ETH_Exported_Macros 1751 * @{ 1752 */ 1753 /** 1754 * @} 1755 */ 1756 1757 /** @defgroup ETH_Exported_Functions 1758 * @{ 1759 */ 1760 void ETH_DeInit(void); 1761 uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress); 1762 void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); 1763 void ETH_SoftwareReset(void); 1764 FlagStatus ETH_GetSoftwareResetStatus(void); 1765 void ETH_Start(void); 1766 uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc); 1767 1768 1769 #ifdef USE_ENHANCED_DMA_DESCRIPTORS 1770 void ETH_EnhancedDescriptorCmd(FunctionalState NewState); 1771 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ 1772 1773 /** 1774 * @brief PHY 1775 */ 1776 uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); 1777 uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); 1778 uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); 1779 1780 /** 1781 * @brief MAC 1782 */ 1783 void ETH_MACTransmissionCmd(FunctionalState NewState); 1784 void ETH_MACReceptionCmd(FunctionalState NewState); 1785 FlagStatus ETH_GetFlowControlBusyStatus(void); 1786 void ETH_InitiatePauseControlFrame(void); 1787 void ETH_BackPressureActivationCmd(FunctionalState NewState); 1788 FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); 1789 ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); 1790 void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); 1791 void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); 1792 void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); 1793 void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); 1794 void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); 1795 void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); 1796 1797 /** 1798 * @brief DMA Tx/Rx descriptors 1799 */ 1800 void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 1801 void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 1802 uint32_t ETH_CheckFrameReceived(void); 1803 uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength); 1804 FrameTypeDef ETH_Get_Received_Frame(void); 1805 FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); 1806 uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); 1807 void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); 1808 void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); 1809 void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); 1810 void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); 1811 void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); 1812 void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); 1813 void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); 1814 void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); 1815 FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); 1816 #ifdef USE_ENHANCED_DMA_DESCRIPTORS 1817 FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag); 1818 #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ 1819 void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); 1820 uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); 1821 void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); 1822 void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); 1823 uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); 1824 FrameTypeDef ETH_Get_Received_Frame_interrupt(void); 1825 /** 1826 * @brief DMA 1827 */ 1828 FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); 1829 void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); 1830 ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); 1831 void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); 1832 uint32_t ETH_GetTransmitProcessState(void); 1833 uint32_t ETH_GetReceiveProcessState(void); 1834 void ETH_FlushTransmitFIFO(void); 1835 FlagStatus ETH_GetFlushTransmitFIFOStatus(void); 1836 void ETH_DMATransmissionCmd(FunctionalState NewState); 1837 void ETH_DMAReceptionCmd(FunctionalState NewState); 1838 void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); 1839 FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); 1840 uint32_t ETH_GetRxOverflowMissedFrameCounter(void); 1841 uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); 1842 uint32_t ETH_GetCurrentTxDescStartAddress(void); 1843 uint32_t ETH_GetCurrentRxDescStartAddress(void); 1844 uint32_t ETH_GetCurrentTxBufferAddress(void); 1845 uint32_t ETH_GetCurrentRxBufferAddress(void); 1846 void ETH_ResumeDMATransmission(void); 1847 void ETH_ResumeDMAReception(void); 1848 void ETH_SetReceiveWatchdogTimer(uint8_t Value); 1849 1850 1851 /** 1852 * @brief PMT 1853 */ 1854 void ETH_ResetWakeUpFrameFilterRegisterPointer(void); 1855 void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); 1856 void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); 1857 FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); 1858 void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); 1859 void ETH_MagicPacketDetectionCmd(FunctionalState NewState); 1860 void ETH_PowerDownCmd(FunctionalState NewState); 1861 1862 /** 1863 * @brief MMC 1864 */ 1865 void ETH_MMCCounterFullPreset(void); 1866 void ETH_MMCCounterHalfPreset(void); 1867 void ETH_MMCCounterFreezeCmd(FunctionalState NewState); 1868 void ETH_MMCResetOnReadCmd(FunctionalState NewState); 1869 void ETH_MMCCounterRolloverCmd(FunctionalState NewState); 1870 void ETH_MMCCountersReset(void); 1871 void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); 1872 ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); 1873 uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); 1874 1875 #ifdef __cplusplus 1876 } 1877 #endif 1878 1879 #endif /* __STM32F4x7_ETH_H */ 1880 /** 1881 * @} 1882 */ 1883 1884 1885 /** 1886 * @} 1887 */ 1888 1889 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 1890